JPH0898510A - Booster circuit and its drive method - Google Patents

Abstract

PURPOSE: To reduce a loss of a booster circuit by connecting the output of a control means to a first switch and a second switch out of N switches constituting a booster means. CONSTITUTION: A booster circuit consists of a power supply 1, a control means 4 consisting of an oscillation means 2 and a ring counter means 3, and a booster means 5 and a clock system 6 is used as a load. The control means 4 consists of the oscillation means 2 and the ring counter means 3 for outputting a time- multiplexed control signal. In the booster means 5, N charging means consisting of capacitors 28-32, first switches 18--22 which are connected to one terminal of the capacitors 28-32 and supply the potential of one terminal of the power supply 1 and second switches 23-27 which are connected to the other terminal of the capacitors 28-32 and supply the potential of the other terminal of the power supply 1 are connected in series. Then, the output of the control means 4 is connected to N switches 18-22 for constituting the booster means 5 and second switches 23-27, thus generating a booster voltage which is nearly N times the power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a driving method of a booster circuit for boosting a voltage of a power source and generating a voltage higher than that of the power source in a load.

[0002]

2. Description of the Related Art As a conventional technique, for example, Japanese Patent Laid-Open No.
There is a booster circuit disclosed in Japanese Unexamined Patent Publication No. 60227. Figure 4
FIG. 3 is a circuit diagram showing a configuration of a booster circuit described in JP-A-48-60227. FIG. 5 is an equivalent circuit showing a state in which electric charge is accumulated in each capacitor of the conventional booster circuit shown in FIG. FIG. 6 is an equivalent circuit showing how charges are accumulated in the boosted output capacitance of the conventional booster circuit shown in FIG.

The configuration of the conventional booster circuit shown in FIG. 4 will be described. The conventional booster circuit includes a power supply E, a switch operation circuit 41, a plurality of (three in the figure) capacitors C, a booster output capacitor C0, and an N-type field effect that switches the connection between the capacitor C and the booster output capacitor C0. It is composed of transistors (hereinafter referred to as NFET) S1 to S10 and an inverter I1 that controls the NFETs S1 to S10, and the load RL is a load resistance.

The operation of the conventional booster circuit will now be described with reference to the circuit diagram of the conventional booster circuit shown in FIG. 4 and the equivalent circuits shown in FIGS. First, the output signal P1 of the switch operating circuit 41 is set to "L", and NFETS1
To S6 are made conductive, NFETS7 to S10 are made non-conductive, and as shown in FIG.
Connect in parallel to charge.

Next, the output signal P of the switch operating circuit 41
1 is set to "H" to make NFETs S1 to S6 non-conductive,
NFETS S7-S10 are made conductive, and as shown in FIG.
The three capacitors C and the power source E are connected in series, and NFETS1 is connected.
The boost output capacitance C0 is connected in parallel via 0 to charge the boost output capacitance C0. After that, the booster circuit is configured to obtain a boosted output in the boosted output capacitor C0 by switching the output signal P1.

[0006]

However, in the booster circuit of the conventional example, it is necessary to charge the charges charged in the plurality of capacitors C again to the booster output capacitor C0, and the charge from the capacitor C to the booster output capacitor C0 is charged. Losses for movement are inevitable. In addition, NFETS7 to connect a plurality of capacitors C in series
The internal loss due to the on-resistance of S10 becomes too large,
There is a problem that a large amount of power cannot be taken out.

Further, there is a problem that the output voltage of the boosted output capacitance C0 has a voltage fluctuation due to the repetition of charging time by a plurality of capacitances C and discharging time by the load RL.

Further, there is a problem that it is not possible to deal with the case where the polarities of the power supply voltages are reversed.

The object of the present invention is to solve these problems,
It is an object of the present invention to provide a booster circuit that reduces unnecessary loss.

It is another object of the present invention to provide a booster circuit that reduces voltage fluctuations.

A further object of the present invention is to provide a booster circuit which always generates a boosted voltage having a fixed polarity regardless of the polarity of the power source.

[0012]

In order to achieve the above object, the structure of the booster circuit of the present invention and the driving method thereof adopt the following means.

The structure of the booster circuit of the present invention comprises a power supply, a control means including an oscillating means and a ring counter means for outputting a time-division control signal, and a capacitor and one terminal of the capacitor connected to one of the power supplies. N (N ≧ 2) charging means are connected in series having a first switch for supplying the potential of the terminal and a second switch connected to the other terminal of the capacitor for supplying the potential of the other terminal of the power supply. Boosting means, and the output of the control means is connected to N first switches and second switches constituting the boosting means.

The structure of the booster circuit of the present invention comprises a power supply, a rectifier circuit located between the power supply and the boosting means and the control means, an oscillating means and a ring counter means for outputting a time-division control signal. And a first switch connected to the capacitance and one terminal of the capacitance to supply the potential of one output terminal of the rectifier circuit and a switch connected to the other terminal of the capacitance to supply the potential of the other output terminal of the rectifier circuit. And a boosting means for connecting N (N ≧ 2) charging means in series with a second switch, and the output of the control means is N first and second switches forming the boosting means. Connect to and.

The configuration of the booster circuit of the present invention is such that the power supply, the rectifier circuit located between the power supply and the boosting means and the first control means, the oscillating means and the time-division first control signal are output. First ring counter means, first tristate buffer means for inputting the output of the first ring counter means, and first switching means for controlling the first tristate buffer means; Second control means including second ring counter means for outputting a second control signal and second tri-state buffer means for inputting the output of the second ring counter means, and a capacitance and one terminal of the capacitance. And a second switch connected to the second rectifier circuit for supplying the potential of one output terminal of the rectifier circuit and a second switch connected to the other terminal of the capacitor for supplying the potential of the other output terminal of the rectifier circuit. Are connected in series (N ≧ 2) in series, and the output of the first control means and the output of the second control means are the N first switches and the output of the second control means. It is characterized in that it is connected to two switches.

In the configuration of the booster circuit of the present invention, the power source, the oscillation means, the first ring counter means for outputting the time-division first control signal, and the first ring counter means for inputting the output of the first ring counter means are inputted. First control means including a tri-state buffer means and a first switching circuit for controlling the first tri-state buffer means, a detection circuit for detecting the polarity of the power supply, and a time-division second control signal are output. Second ring counter means and a selection circuit for selectively outputting the output of the second ring counter means with the output of the detection circuit, a second tri-state buffer means for inputting the output of the selection circuit, and a second
Second control circuit including a second switching circuit for controlling the tri-state buffer circuit, and a first switch connected to the capacitor and one terminal of the capacitor for supplying the potential of one terminal of the power source and the capacitor. Boosting means for connecting N (N ≧ 2) charging means in series with a second switch connected to the other terminal and supplying the potential of the other output terminal of the power supply; And the output of the second control means are connected to the N first switches and the second switches constituting the boosting means.

A method of driving a booster circuit according to the present invention comprises a power supply,
Control means including an oscillating means and a ring counter means for outputting a time-division control signal, a first switch connected to the capacitance and one terminal of the capacitance to supply the potential of one terminal of the power supply, and the other of the capacitance Boosting means for connecting N (N ≧ 2) charging means in series with a second switch connected to the terminal and supplying the potential of the other terminal of the power supply, and the output of the control means is the boosting means. The N first switches and the second
, And controls the first switch and the second switch to sequentially connect the power supplies to N capacitors in a time-division manner and charge the boosted voltage of about N times the power supply voltage. It is characterized by occurring.

A method of driving a booster circuit according to the present invention comprises a power supply,
A rectifying circuit connected between a power source and a boosting means and a control means, a control means including an oscillating means and a ring counter means for outputting a time-division control signal, and a rectifier circuit connected to a capacitor and one terminal of the capacitor. N charging means in series having a first switch for supplying the potential of one output terminal and a second switch connected to the other terminal of the capacitor for supplying the potential of the other output terminal of the rectifier circuit ( N ≧ 2) boosting means to be connected, and the output of the control means is connected to the N first switches and the second switch forming the boosting means, and the rectifier circuit even if the polarity of the power supply changes. Always outputs polarities in the same direction, and controls the first switch and the second switch by the output of the control means to sequentially connect the output voltage of the rectifier circuit to the N capacitors in a time division manner. Charged by charging, boosted voltage almost N times the power supply voltage Characterized in that it occurs.

A method of driving a booster circuit according to the present invention comprises a power supply,
A rectifier circuit located between the power source, the boosting means and the first control means, an oscillation means and a first ring counter means for outputting a time-division first control signal and an output of the first ring counter means. First control means including first tri-state buffer means for inputting and a switching circuit for controlling the first tri-state buffer means, and second ring counter means for outputting a time-division second control signal Second control means including second tri-state buffer means for inputting the output of the second ring counter means, and a potential of one output terminal of the rectifier circuit connected to the capacitance and one terminal of the capacitance. Boosting means for connecting N (N ≧ 2) charging means in series with a first switch and a second switch connected to the other terminal of the capacitor and supplying the potential of the other output terminal of the rectifier circuit. Existence , The output of the first control means and the output of the second control means are connected to the N first switches and the second switch constituting the boosting means, and the polarity of the power supply changes in the rectifier circuit. Always supplies a voltage having the same polarity to the boosting means and the first control means, and controls the first switch and the second switch forming the boosting means by the output of the first control means, The output voltage of the rectifier circuit is sequentially connected to N capacitors in a time-division manner and charged, and a boosted voltage that is approximately N times the power supply voltage is supplied to the second control means and the load to drive the load, The clock is input to the second ring counter means constituting the second control means, the signal output by the load stops the oscillating means, and the signal output by the load is transferred to the first switching circuit via the first switching circuit. Disabling the output of the tri-state buffer means Signal to force to enable the output of the second tri-state buffer means, and switches the control pressure-increasing means from the first control means to the second control means.

A method of driving a booster circuit according to the present invention comprises a power supply,
Controlling the oscillation means, the first ring counter means for outputting the time-division first control signal, the first tri-state buffer means for inputting the output of the first ring counter means, and the first tri-state buffer means The first control means including a first switching circuit, the detection circuit for detecting the polarity of the power supply, the second ring counter means and the second ring counter means for outputting the time-division second control signal, A selection circuit for selectively outputting an output as an output of the detection circuit; second tri-state buffer means for inputting the output of the selection circuit; and a second switching circuit for controlling the second tri-state buffer means. A second control means and a first capacitor connected to one terminal of the capacitor and one of the terminals of the power source for supplying a potential
And a boosting means for connecting N (N ≧ 2) charging means in series with a second switch connected to the other terminal of the capacitor and supplying the potential of the other output terminal of the power source, The output of the first control means and the output of the second control means are connected to the N first switches and the second switch which constitute the boosting means, and the power source is the boosting means and the first control means. Voltage is supplied to the first control means and the output of the first control means is used to control the first switch and the second switch forming the boosting means to charge the power sources sequentially into N capacitors in a time-division manner. Then, a boosted voltage that is approximately N times the power supply voltage is supplied to the second control means and the load to drive the load, and the clock of the load is input to the second ring counter means that constitutes the second control means. The signal output from the load is the first control signal that stops the oscillating means, and the load outputs the signal. That signal the output of the first tri-state buffer means to disenable via the first switching circuit, and the signal that the load is outputted to enable the output of the second tri-state buffer means, first
The control circuit switches the control of the boosting means from the control means to the second control means to boost the voltage, and the detection circuit detects a change in the negative polarity of the power supply, and the selection circuit configures the second control means by the detection circuit output. By switching the output of the second ring counter means according to the above, the charging direction to the capacitor is always set to a constant direction, so that the boosted voltage is generated regardless of the polarity of the power source.

[0021]

According to the booster circuit of the present invention, the first switch is connected to the capacitance and one terminal of the capacitance to supply the potential of one terminal of the power supply, and the potential of the other terminal of the power supply is connected to the other switch of the capacitance. Has a boosting means for connecting N charging means in series with a second switch for supplying the voltage to the ring counter means, and the output of the oscillating means oscillating at the voltage of the power supply is input to the ring counter means. By outputting the control signal to the boosting means, a boosted voltage that is almost N times higher is output.

By providing a rectifying circuit between the power source and the boosting means and the control means, a constant boosted voltage is always generated regardless of the polarity of the power source.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a circuit diagram showing a circuit configuration of a booster circuit according to a first embodiment of the present invention. FIG. 2 is a waveform diagram showing the waveform of the control signal of the control means that constitutes the booster circuit according to the first embodiment of the present invention. FIG. 3 is a graph showing a state in which each of the capacitors forming the booster circuit according to the first embodiment of the present invention is charged.

First, the configuration of the booster circuit according to the first embodiment of the present invention will be described with reference to FIG. The booster circuit according to the first embodiment of the present invention shown in FIG. 1 includes a power supply 1, a control means 4 including an oscillation means 2 and a ring counter means 3,
The timepiece system 6 is used as the load.

As the oscillating means 2 constituting the control means 4, an RC oscillating circuit having resistance and capacitance, a multivibrator or an oscillating circuit using a crystal oscillator or a ceramic oscillator is used. The output of the oscillator 2 is connected to the clock input of the ring counter 3.

The ring counter means 3 constituting the control means 4 includes N (five in the figure) data flip-flops (hereinafter referred to as DFFs) 7 to 11 and DFFs 7-1.
The NOR gate 12 connects the outputs of the DFFs 7 to 10 except the output of the DFF 11 in the final stage of 1 to the data input terminals of the DFF 7 in the first stage, and the inverters 13 to 17 that invert the outputs of the DFFs 7 to 11. To do. The clock input terminals of the DFFs 7 to 11 are connected to the output of the oscillation means 2, and the outputs of the DFFs 7 to 11 and the inverters 13 to 1 are connected.
The output of 7 becomes the output of the control means 4 and becomes the control signal of the boosting means 5.

The boosting means 5 includes capacitors 28-32 and capacitors 28-32.
To 32 of P-type field effect transistors (hereinafter referred to as a first switch) 18 to 22 connected to one terminal of each of the power sources 1 to supply the potential of one terminal of the power source 1 and a capacitor 28 to
N charging means consisting of N-type field effect transistors (hereinafter referred to as second switches) 23 to 27 connected to the other terminal of each of the 32 and supplying the potential of the other terminal of the power supply 1 are connected in series N ( (5 in the figure) are connected.

Further, one terminal of the capacitance 28 is connected to the ground of the timepiece system 6, and the other terminal of the capacitance 32 is connected to the power source of the timepiece system 6. Also, each of the first switches 18 to 22 and each of the second switches 23 to 27
A control signal output from the control means is connected to the gate terminals of and.

Although the internal structure of the timepiece system 6 is not shown, a crystal oscillator circuit, a frequency divider circuit, and a crystal oscillator of a general quartz wristwatch are provided.
It is a system including a waveform generation circuit, a drive circuit, a converter, and the like.

The power source 1 is a thermoelectric generator that generates power by the temperature difference between the human body temperature and the atmosphere according to the Seebeck effect principle, and although not shown, a P-type semiconductor material and an N-type semiconductor material are connected in series. It is composed of a module in which a plurality of the element pairs are combined. The wristwatch is placed inside the wristwatch so that the back side in contact with human skin is the hot pole and the front side in contact with the atmosphere is the cold pole.

Next, a method of driving the booster circuit according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2 and 3.

By mounting an electronic wrist watch having a built-in power supply 1, the power supply 1 can be operated by the temperature difference between the human body temperature and the atmosphere.
A voltage is generated in the oscillator, and the oscillating means 2 starts oscillating. The output of the oscillation means 2 enters the clock input terminal of the ring counter means 3, and the ring counter means 3 has the waveform Φ1 shown in FIG.
˜Φ10 is output as a control signal to control the first switches 18 to 22 and the second switches 23 to 27 of the booster 5.

First, Φ1 sets the second switch 23 to Φ2
Shows the first switch 18 at time t = t1 to t2 shown in FIG.
During the period, the capacitor 28 is electrically connected, and the capacitor 28 is connected in parallel to the power source 1 to be charged. Next, Φ3 conducts the second switch 24 and Φ4 conducts the first switch 19 for the time t = t2 to t3, and the capacitance 29
Are connected in parallel to the power source 1 to charge.

Further, Φ5 is the second switch 25, Φ
6 conducts the first switch 20 for a time t = t3 to t4, and connects the capacitor 30 in parallel to the power supply 1 to charge it. Then Φ
7 is the second switch 26, and Φ8 is the first switch 21.
During time t = t4 to t5, the capacitor 31 is connected in parallel to the power source 1 to be charged.

Further, Φ9 is the second switch 27, Φ
10 conducts the first switch 22 for a time t = t5 to t6, and connects the capacitor 32 in parallel with the power source 1 to charge the same. By repeatedly charging the capacitors 28 to 32 in a time-division manner in this manner, a boosted voltage that is approximately five times the voltage of the power supply 1 can be obtained at the other terminal of the capacitor 32 in a short time. Is supplied to the timepiece system 6 to drive the timepiece system 6.

Here, how each of the capacities 28 to 32 is charged will be described with reference to FIG. Let C be the capacitance value of one capacitor and R be the internal resistance of the power supply 1.
If the voltage is set to E1 and the load is infinite for simplicity,
Assuming that the capacity 28 is charged from time t = 0, the charging voltage v
Is as follows: v = E1 (1−exp (−t / RC)) Considering charging in time division, the result is as shown in FIG. However, for simplification, the charging time interval of each capacity is made equal to the time constant RC, and the horizontal axis is drawn with RC (second) as one unit.

For example, with respect to the capacity 28, it is charged for t = 0 to 1 and becomes v = 0.63E1, which is held until t = 5. Next, the battery is charged for t = 5 to 6 and v = 0.86E.
It becomes 1 and is held until t = 10. Furthermore, t = 10
It is charged for 11 and becomes v = 0.95E1. At 15 RC, the charging voltage of all capacitors is v = 0.95E1,
The outputs are all added, and an output voltage that is approximately five times that of the power supply 1 is obtained.

Next, a second embodiment of the present invention will be described. FIG. 7 is a block diagram of a booster circuit according to the second embodiment of the present invention. FIG. 8 is a circuit diagram showing a circuit configuration of a rectifier circuit which constitutes a booster circuit according to the second embodiment of the present invention.

The booster circuit according to the second embodiment of the present invention shown in FIG. 7 is a power supply 1, a rectifier circuit 33 located between the power supply 1 and the control means 4 and the boosting means 5, the oscillating means 2 and the ring. It comprises a control means 4 having a counter means 3 and a boosting means 5, and a timepiece system 6 is used as a load.

The configurations of the power source 1, the oscillating means 2, the ring counter means 3, the boosting means 5 and the timepiece system 6 are the same as those described in the first embodiment of the present invention, and therefore their explanations are omitted. To do.

Even if the polarity of the power supply 1 changes, the rectifier circuit 33 always outputs the power supply voltage of the same polarity to the oscillating means 2, the ring counter means 3 and the boosting means 5. The configuration of the rectifier circuit that constitutes the booster circuit according to the second embodiment of the present invention will be described with reference to FIG.

The rectifier circuit shown in FIG. 8 has a first PFET 35.
And the second PFET 36, the first NFET 39 and the second NFET
It is composed of an FET 40, a first diode 37, a second diode 38, a third diode 41 and a fourth diode 42.

One terminal of the power supply 1 is connected to the first PFET 3
5, one terminal of the first NFET 39, the gate terminal of the second PFET 36, and the second NFE.
It is connected to the gate terminal of T40, the anode terminal of the first diode 37, and the cathode terminal of the third diode 41.

The other terminal of the power source 1 is connected to the second PFE.
One terminal of T36, one terminal of the second NFET 40, the gate terminal of the first PFET 35, and the first NF
It is connected to the gate terminal of ET39, the anode terminal of the second diode 38, and the cathode terminal of the fourth diode 42.

The other terminal of the first PFET 35 is connected to the other terminal of the second PFET 36 and one output terminal of the rectifier circuit, and the other terminal of the first NFET 39 is connected to the other terminal of the second NFET 40. It is connected to the terminal and the other output terminal of the rectifier circuit.

Further, the cathode terminal of the first diode 37 is the cathode terminal of the second diode 38, the substrate of the first PFET 35, and the second PFET 36.
Connect to the substrate. Third diode 41
Is connected to the anode terminal of the fourth diode 42, the substrate of the first NFET 41, and the substrate of the second NFET 42.

Next, the operation of the rectifier circuit shown in FIG. 8 will be described. Normally, the temperature of the atmosphere is lower than the temperature of the skin, so power
The polarity of the generated voltage of the first PF is as shown by the arrow 34.
The gate terminals of the ET 35 and the first NFET 39 are on the negative potential side, and the second PFET 36 and the second NFET 40 are
The gate terminals of and are grounded to the positive potential side. Therefore, if the generated voltage of the power supply 1 is equal to or higher than the threshold voltage, the first PF
The ET 35 and the second NFET 40 are electrically connected, and the polarity of the voltage after rectification is as shown by an arrow 44.

At this time, the first PFET 35 and the second NFET 35
The FET 40 is electrically connected to the second PFET 36 and the first PFET 36.
The NFET 39 does not conduct. For this purpose, the first diode 37 causes the first PFET 35 and the second PF
A positive potential is applied to the substrate with the ET 36 by the fourth diode 42 and the first NFET 39 and the second NF.
A negative potential is applied to the substrate with ET40.

When the temperature of the atmosphere becomes higher than the temperature of the skin and the voltage generated by the power source 1 has a polarity opposite to that of the arrow 34 in the figure, the gate terminals of the second PFET 36 and the second NFET 40 are placed on the negative potential side. First PFET 35 and first NF
The gate terminal of ET39 is grounded to the positive potential side. For this reason, the second PFET 36 and the first NFET 39 are brought into conduction, and the polarity of the voltage after rectification is as indicated by the arrow 44, which is the same as usual.

At this time, the second PFET 36 and the first NFET
It is electrically connected to the FET 39, and is connected to the first PFET 35 and the second PFET 35.
NFET 40 does not conduct. To this end, the second diode 38 causes the first PFET 35 and the second PF to
A positive potential is applied to the substrate with the ET 36 by the third diode 41 and the first NFET 39 and the second NF.
A negative potential is applied to the substrate with ET40.

Similar to the first embodiment, the output voltage of the rectifier circuit is supplied to the oscillating means 2, the ring counter means 3 and the boosting means 5 which are the controlling means 4 in FIG. 7, and a boosted output can be obtained. it can.

Next, a third embodiment of the present invention will be described. FIG. 9 is a block diagram showing a booster circuit according to the third embodiment of the present invention. FIG. 10 is a circuit diagram showing the circuit configuration of the booster circuit according to the third embodiment of the present invention. Figure 11
FIG. 9 is a circuit diagram showing a circuit configuration of a switching circuit which constitutes a first control means in a third embodiment of the present invention.

The configuration of the booster circuit according to the third embodiment of the present invention shown in FIG. 9 is the power supply 1, the rectifier circuit 33, the boosting means 51, the oscillating means 54, and the first ring counter means 5.
5, first tri-state buffer means 56 and switching circuit 57, first control means 52, second ring counter means 58 and second tri-state buffer means 6
And a second control means 53 having 0, and the timepiece system 6 is used as a load.

The rectifier circuit 33 is located between the power supply 1 and the booster 51 and the first controller 52. The output of the oscillating means 54 which constitutes the first control means 52 is the clock input terminal of the first ring counter means 55 which constitutes the first control means 52, and the switching circuit 57 which constitutes the first control means 52. It is connected to the clock input terminal of.

The input terminal of the first tri-state buffer means 56 constituting the first control means 52 is connected to the first control signal output from the first ring counter means 55. Furthermore, the first tri-state buffer means 56
Is connected to the switching signal output from the switching circuit 57, and the output of the first tri-state buffer means 56 is connected to the control terminal of the boosting means 51.

The clock input terminal of the second ring counter means 58 constituting the second control means 53 is connected to the signal F2 output by the timepiece system 6. Second tri-state buffer means 6 constituting the second control means 53
The input terminal of 0 connects the second control signal output from the second ring counter means 58 to the input terminal, and the switching terminal of the second tri-state buffer means 60 connects the switching signal output from the switching circuit 57. However, the output of the second tri-state buffer means 60 is connected to the control terminal of the boosting means 51.

The boosted voltage output by the boosting means 51 is
It is connected to the power supply terminals of the timepiece system 6 and the second control means 53. The signal F1 output from the timepiece system 6 is connected to the oscillation stop terminal of the oscillating means 54 which constitutes the first control means 52 and the switching control terminal of the switching circuit 57 which constitutes the first control means 52.

Power source 1, rectifying circuit 33, and oscillating means 54
The first ring counter means 55, the second ring counter means 58, the boosting means 51, and the timepiece system 6 have the same configurations as those described in the first and second embodiments of the present invention. Therefore, the description is omitted.

However, the first switches 101 to 105 constituting the boosting means 51 shown in FIG. 10 correspond to the first switches 18 to 22 constituting the boosting means 5 shown in FIG.
The second switch 108 constituting the boosting means 51 shown in FIG.
1 to 112 correspond to the first switches 23 to 27 constituting the boosting means 5 shown in FIG.

The booster circuit according to the third embodiment of the present invention is the first booster circuit.
The first tri-state buffer means 56 constituting the control means 52 and the second tri-state buffer means 60 constituting the second control means 53 are connected to the first control means 52.
The first tri-state buffer means 56 is enabled and the second tri-state buffer means 60 is disabled when the power is turned on, and the first control means 52 outputs the first signal.
The boosting means 51 is controlled by the control signal.

Also, after a lapse of a fixed time after the power is turned on, that is, by switching the signal F1 output from the clock system 6, the first tri-state buffer means 56 is disabled and the second tri-state buffer means 60 is enabled, and the second tri-state buffer means 60 is enabled. The control means 53 controls the boosting means 51 with the second control signal.

The first tri-state buffer means 56, the second tri-state buffer means 60 and the switching circuit 57 which constitute the booster circuit of the present invention will be described with reference to FIGS. 10 and 11.
The configuration will be described.

The first tri-state buffer means 56 shown in FIG. 10 includes an inverter 80 for inverting the switching signal output from the switching circuit 57, and tri-state buffers 81-81.
And 90. Tri-state buffers 81-90
The input terminal of is connected to the first control signal which is the output of the first ring counter means 55. The output of the inverter 80 is connected to the switching terminals of the tri-state buffers 81 to 90, and the output of the tri-state buffers 81 to 90 is connected to the control terminal of the boosting means 51.

The second tristate buffer means 60 shown in FIG. 10 is composed of an inverter 120 for inverting the switching signal output from the switching circuit 57 and tristate buffers 121 to 130. The input terminals of the tri-state buffers 121 to 130 are connected to the second control signal output from the second ring counter means 58.
The output of the inverter 120 is the tristate buffer 1
The output terminals of the tri-state buffers 121 to 130 are connected to the control terminals of the boosting means 51.

The switching circuit shown in FIG. 11 has a resistor 70 and a capacitor 7
1 and a time constant circuit having a time constant larger than the oscillation period of the oscillating means 54, a one-shot circuit composed of the DFF 72, the DFF 73, the inverter 74, and the 2-input AND gate 75, and an RS flip-flop (hereinafter referred to as RSFF). (Described) 76 and an inverter 77.

The output of the time constant circuit is connected to the data input terminal of the DFF 72 in the preceding stage which constitutes the one-shot circuit.
The output of the DFF 72 at the preceding stage forming the one-shot circuit is the input terminal of the inverter 74 and the 2-input AND gate 7.
5 is connected to one of the input terminals, and the output of the inverter 74 is connected to the data input terminal of the DFF 73 in the subsequent stage.
The output of the FF 73 is connected to the other input terminal of the 2-input AND gate 75. The output of the 2-input AND gate 75 forming the one-shot circuit is connected to the reset terminal of the RSFF 76, and the output of the RSFF 76 becomes the switching signal of the switching circuit 57 shown in FIG. 9 or 10 via the inverter 77.

The clock input terminals of the DFF 72 and DFF 73 forming the one-shot circuit shown in FIG.
The output terminal of the RSFF is connected to the output signal F1 of the timepiece system 6 shown in FIG.

Next, the operation of the booster circuit according to the third embodiment of the present invention will be described with reference to FIGS. 9, 10, and 11. When an electronic wristwatch incorporating the power source 1 which is a thermoelectric generator is mounted, a voltage is generated in the power source 1 and the oscillating means 54 starts oscillating, as in the first embodiment.

When a voltage is generated in the power supply 1, the output of the one-shot circuit constituting the switching circuit shown in FIG. 11 rises when the output voltage of the time constant circuit rises and the data input terminal of the one-shot circuit becomes "H". The one-shot circuit outputs the “H” pulse for one clock of the oscillation means 54 to the RSFF76.
It outputs to the reset terminal of and resets RSFF76,
The output of the RSFF 76 is set to "L", and the switching signal which is the output of the inverter 77 forming the switching circuit 57 is set to "H".

When the switching signal of the switching circuit 57 becomes "H", the first tristate buffer 56 constituting the first control means 52 is enabled, and the second control means 5 is enabled.
The second tri-state buffer 60 that composes 3 is disabled.

The output of the oscillating means 54 enters the clock input terminal of the first ring counter means 55, and the first ring counter means 55 outputs the waveforms Φ1 to Φ10 shown in FIG. 2 as the first control signal, The first switch 1 of the boosting means 51 via the first tri-state buffer means 56.
01-105 and the second switches 108-112 are time-divisionally controlled. As a result, a boosted voltage is generated and the boosted voltage is output to the timepiece system 6 and the second control means.

When the boosted voltage is generated, the timepiece system 6 is activated, and the output signal F2 of the timepiece system 6 enters the clock input terminal of the second ring counter means 58 constituting the second control means 53, and the second ring. The counter means 58 is activated, and the output of the second ring counter means 58 outputs the waveforms Φ1 to Φ10 shown in FIG. 2 as the second control signals and inputs them to the second tri-state buffer means 60. , The output of the second tri-state buffer means 60 remains high impedance because the second tri-state buffer means 60 is disabled.

Next, the timepiece system 6 outputs the output signal F1 to the oscillation stop terminal of the oscillating means 54 and the set terminal of the switching circuit 57 constituting the first control means 52, and the oscillating means. 54 is stopped, and the switching signal output from the inverter 77 forming the switching circuit 57 is set to "L".

When the switching signal of the switching circuit 57 becomes "L", the first tri-state buffer means 56 constituting the first control means 52 is disabled and the output of the first tri-state buffer means 56 becomes high. It will be pedestal.

Further, the second tristate buffer means 60 constituting the second control means 53 is enabled,
The output of the second ring counter means 58 constituting the second control means 53 is converted into the second tri-state buffer means 60.
Output via the first switch 101 of the boosting means 51.
-105 and the second switches 108-112 are time-divisionally controlled to generate a boosted voltage.
And continues to output the boosted voltage to the second control means.

Next, a fourth embodiment of the present invention will be described. FIG. 12 is a block diagram showing a booster circuit according to the fourth embodiment of the present invention. FIG. 13 is a circuit diagram showing the circuit configuration of the booster circuit according to the fourth embodiment of the present invention.

FIG. 14 is a circuit diagram showing the circuit configuration of the second ring counter means and the selection circuit which constitute the second control means in the fourth embodiment of the present invention. FIG. 15 is a circuit diagram showing the circuit configuration of the detection circuit according to the fourth embodiment of the present invention.

FIG. 16 is a circuit diagram showing the circuit arrangement of the boosting means when the power source has a positive polarity in the fourth embodiment of the present invention. FIG. 17 is a circuit diagram showing the circuit configuration of the boosting means when the power supply has a negative polarity in the fourth embodiment of the present invention. FIG. 18 is a waveform diagram showing the waveforms of the control signals of the first control means and the second control means in the fourth embodiment of the present invention.

The booster circuit according to the fourth embodiment of the present invention shown in FIG. 12 is a power supply 1, a booster 51, and an oscillator 5.
4, first ring counter means 55, first tri-state buffer means 56, and first switching circuit 57, first control means 52, and second ring counter means 58.
Selection circuit 59 and second tri-state buffer means 6
0 and a second control circuit 53 having a second switching circuit 61
And a detection circuit 50, and the timepiece system 6 is used as a load.

The power supply 1 is connected to the boosting means 51 and the power supply terminal of the first control means 52. The output of the oscillating means 54 which constitutes the first control means 52 is the clock input terminal of the first ring counter means 55 which constitutes the first control means 52, and the switching circuit 57 which constitutes the first control means 52. It is connected to the clock input terminal of.

The input terminal of the first tri-state buffer means 56 constituting the first control means 52 is connected to the first control signal output from the first ring counter means 55, and the first tri-state is also connected. The switching terminal of the state buffer means 56 is connected to the first switching signal output from the first switching circuit 57.

The first switching signal output from the first switching circuit 57 is connected to the first substrate switching terminal of the boosting means 51, and the output of the first tristate buffer means 56 is controlled by the boosting means 51. It is connected to the terminal.

The clock input terminal of the second ring counter means 58 constituting the second control means 53 is connected to the signal F2 output by the timepiece system 6. The input terminal of the selection circuit 59 that constitutes the second control means 53 is the second
To the second control signal output from the ring counter means 58. The detection terminal of the selection circuit 59 is the detection circuit 50.
Connected to the detection signal output by.

The input terminal of the second tri-state buffer means 60 constituting the second control means 53 has a second control signal which the selection circuit 59 selectively outputs the output of the second ring counter means 58. Connect to. The switching terminal of the second tri-state buffer means 60 is connected to the second switching signal output from the second switching circuit 61. The output of the second tristate buffer means 60 is connected to the control terminal of the boosting means 51.

The second switching signal output from the second switching circuit 61 is connected to the second substrate switching terminal of the boosting means 51.

The boosted voltage output by the boosting means 51 is
It is connected to the power supply terminals of the timepiece system 6, the detection circuit 50, and the second control means 53. The signal F1 output by the timepiece system 6 includes the oscillation stop terminal of the oscillation means 54 that constitutes the first control means 52, the set terminal of the first switching circuit 57 that constitutes the first control means 52, and the second Of the switching circuit 61.

The configurations of the power source 1, the oscillating means 54, the first ring counter means 55 and the timepiece system 6 are the same as those of the first, second and third embodiments of the present invention. The configuration is the same as that described, and the first switching circuit 57
Since the second switching circuit 61 has the same structure as the switching circuit described in the third embodiment, the description thereof will be omitted.

The booster circuit according to the fourth embodiment of the present invention is the first
The first tri-state buffer means 56 constituting the control means 52, the second tri-state buffer means 60 constituting the second control means 53, and the substrate potential of the boosting means 51. The first switching signal and the first substrate switching signal of the first switching circuit 57 which constitutes the control means 52, and the second which constitutes the second control means 53.
When the power is turned on, the first tristate buffer means 56 is enabled and the second tristate buffer means 60 is disabled by the second switch signal of the switch circuit 61 and the second substrate switch signal.
Of the boosting means 5 by the first control signal output from the control means 52 of
Control 1

Also, after a fixed time from the power-on, the first tri-state buffer means 56 is disabled and the second tri-state buffer means 60 is enabled, and the second control signal output from the second control means 53 is used. It controls the boosting means 51.

Boosting means constituting the boosting circuit of the present invention and the first tri-state buffer means 5 will be described with reference to FIG.
6 and the second tri-state buffer means 60 will be described. The configuration of the first switching circuit 57 and the second switching circuit 61 forming the booster circuit of the present invention will be described with reference to FIG.

The first tri-state buffer means 56 shown in FIG. 13 comprises an inverter 80 which inverts the first switching signal output from the first switching circuit 57, and tri-state buffers 81 to 90. The input terminals of the tri-state buffers 81 to 90 are connected to the first control signal which is the output of the first ring counter means 55. The output of the inverter 80 is the tristate buffer 81.
To 90 switching terminals. The outputs of the tri-state buffers 81 to 90 are connected to the control terminal of the booster 51.

In addition, the second tri-state buffer means 60 shown in FIG.
The inverter 120 for inverting the switching signal and the tri-state buffers 121 to 132. The input terminals of the tri-state buffers 121 to 132 are connected to the output of the selection circuit 59. Further, the output of the inverter 120 is connected to the switching terminals of the tristate buffers 121 to 132. And tristate buffers 121 to 1
The output of 32 is connected to the control terminal of the boosting means 51.

The boosting means 51 shown in FIG.
13 to 117, the first switches 101 to 105 connected to one terminal of each of the capacitors 113 to 117 to supply the potential of one terminal of the power source 1, and the capacitors 113 to 1
N (five in the figure) second switches 107 to 111 connected to one terminal of each of the seventeen and supplying the potential of the other terminal of the power supply 1 are connected in series.

The boosting means 51 shown in FIG.
A first switch 106 connected to the other terminal of the power source 1 to supply the potential of one terminal of the power source 1 and a second switch 106 connected to the other terminal of the capacitor 117 to supply the potential of the other terminal of the power source 1. It is composed of the switch 112.

The boosting means 51 shown in FIG.
One terminal of 3 is connected to the ground of the clock system 6,
The other terminal of the capacity 117 is connected to the power supply of the timepiece system 6.

Each substrate of the first switches 101 to 106 is a PFET 93 arranged in series between one terminal of the power source 1 and the ground of the timepiece system 6.
And a PFET 94 are connected to the output of the first substrate switching circuit 136. The second switch 10
Each of the substrates 7 to 112 is connected to the output of a second substrate switching circuit 135 composed of NFET 91 and NFET 92 arranged in series between the other terminal of the power source 1 and the power source of the timepiece system 6.

The first switches 101 to 106 and the second switch
The first control signal output from the first control means 52 and the second control signal output from the second control means 53 are connected to the control terminals, which are the gate terminals of the switches 107 to 112, respectively. ing.

The configuration of the second ring counter means 58 and the selection circuit 59 which constitute the booster circuit of the present invention will be described with reference to FIG.

Second ring counter means 5 shown in FIG.
8 is a configuration excluding the inverters 13 to 17 of the output of the ring counter means 3 shown in the first embodiment of the present invention, and
It is composed of FFs 140 to 144 and a NOR gate 145. Further, the clock inputs of the DFFs 140 to 144 connect the signal F2 of the timepiece system 6. And DFF140 ~
The output of 144 is connected to the input terminal of the selection circuit 59.

The selection circuit 59 shown in FIG. 14 connects the gate elements 152 to 163 for inputting the second control signal which is the output of the second ring counter means 58 and the detection signal which is the output of the detection circuit 50. And an inverter 151 that operates. This is a general selection circuit that selectively outputs the output of the second ring counter means 58 to the second tri-state buffer means 60 according to the level of the detection signal.

The structure of the detection circuit 50 constituting the booster circuit of the present invention will be described with reference to FIG.

The detection circuit 50 shown in FIG.
It is a zero cross detector composed of 50, and both terminals of the power supply 1 are connected to both inputs of the operational amplifier 150, and the output of the operational amplifier 150 is connected to the detection terminal of the selection circuit 59. The output of the operational amplifier 150 outputs “L” when the polarity of the power source 1 is positive, and outputs “H” when the polarity of the power source 1 is negative.

The operation of the booster circuit according to the fourth embodiment of the present invention will be described with reference to FIGS. 12, 13, 14, 15, 16, 17, and 18.

When an electronic wristwatch incorporating the power source 1 which is a thermoelectric generator is mounted, a voltage is generated in the power source 1 and the oscillating means 54 starts oscillating, as in the first embodiment.

When the power source 1 is set to generate a positive polarity voltage and a positive polarity voltage is generated, the one switching circuit 57 and the second switching circuit 61 shown in FIG. As for the output of the shot circuit, the output voltage of the time constant circuit rises and the data input terminal of the one shot circuit becomes "H".

Then, the one-shot circuit operates as the oscillating means 54.
1 clock of "H" pulse is output to the reset terminal of RSFF76, RSFF76 is reset and RSFF
When the output of 76 becomes "L", the first switching signal and the second switching signal, which are the outputs of the inverter 77 forming the first switching circuit 57 and the second switching circuit 61, become "H". Become.

When the first switching signal output from the inverter 77 constituting the first switching circuit 57 becomes "H", the first tristate buffer means constituting the first control means 52 shown in FIG. 56 is enabled. In addition, the NFET forming the second substrate switching circuit 135
91 becomes conductive, the output of the inverter 133 becomes "L", and the PFET 93 constituting the first substrate switching circuit 136 also becomes conductive.

When the second switching signal output from the inverter 77 constituting the second switching circuit 61 becomes "H", the second tri-state buffer constituting the second control means 53 shown in FIG. The means 60 is disabled. As a result, the output of the second tri-state buffer means 60 becomes high impedance, and the PFET 94 that constitutes the first substrate switching circuit 136 is formed.
Becomes non-conductive. The output of the inverter 134 is "L".
Therefore, the NFET 92 forming the second substrate switching circuit 135 is also non-conductive.

Therefore, when the NFET 91 forming the second substrate switching circuit 135 becomes conductive, the substrates of the NFETs 107 to 112 forming the boosting means 51 become the potential of the other terminal of the power supply 1. In addition, a PFET that constitutes the first substrate switching circuit 136
The PF that constitutes the boosting means 51 by conducting 93
The substrates of the ETs 101 to 106 are at the potential of one terminal of the power supply 1.

The output of the oscillating means 54 enters the clock input terminal of the first ring counter means 55, and the first ring counter means 55 outputs the waveforms Φ6 to Φ15 shown in FIG. 18 as the first control signal, The voltage is output to the boosting means 51 via the first tri-state buffer 56.

At this time, the boosting means 51 has the first switches 101 to 105 and the second switch 10 as shown in FIG.
8 to 112 and capacitors 113 to 117, the first switches 101 to 105 and the second switches 108 to 112.
The boosted voltage is generated by controlling and in a time division manner, and the boosted voltage is output to the timepiece system 6, the detection circuit 50, and the second control means 53.

When the boosted voltage is generated, the timepiece system 6 is activated, the output signal F2 of the timepiece system 6 enters the clock input terminal of the second ring counter means 58 constituting the second control means 53, and the second ring. The counter means 58 is activated, and the output of the second ring counter means 58 outputs the waveforms Φ6 to Φ15 shown in FIG. 18 as the second control signal via the selection circuit 59, and the second tri-state buffer 6 is output.
Enter 0.

However, at this time, since the second tri-state buffer 60 is disabled, the output of the second tri-state buffer 60 remains high impedance.

Next, the timepiece system 6 configures the output signal F1 as the oscillation stop terminal of the oscillation means 54 constituting the first control means 52, the set terminal of the first switching circuit 57, and the second control means 53. Output to the set terminal of the second switching circuit 60 to stop the oscillation means 54, and the first switching signal of the first switching circuit 57 and the second switching signal of the second switching circuit 60 are "L". "

The first switching signal of the first switching circuit 57 is "
When it becomes L ″, the first tri-state buffer means 56 constituting the first control means 52 is disabled, so that the first tri-state buffer means 56 is disabled.
Output is high impedance. Further, the NFET 91 forming the second substrate switching circuit 135 becomes non-conductive, and the output of the inverter 133 becomes "H",
PFE configuring the first substrate switching circuit 136
T93 also becomes non-conductive.

Further, the switching signal of the second switching circuit 61 is "
When it becomes L ″, the second tri-state buffer 60 which constitutes the second control means 53 is enabled. Further, the PFET which constitutes the first substrate switching circuit 136.
94 becomes conductive, the output of the inverter 134 becomes "H", and the NFET 92 constituting the second substrate switching circuit 135 also becomes conductive.

Therefore, the NF which constitutes the boosting means 51.
The substrates of ETs 107 to 112 have a boosted voltage, which is the power supply potential of the timepiece system 6. Further, the substrates of the PFETs 101 to 106 forming the boosting means 51 become the ground potential of the timepiece system 6.

The second ring counter means 58 constituting the second control means 53 uses the waveforms Φ6 to Φ15 shown in FIG. 18 as the second control signals via the selection circuit 59 and the second tri-state buffer 60. Output to the boosting means 51.

At this time, when the power source 1 has a positive polarity voltage, the detection signal of the detection circuit 50 becomes "L", and the output of the selection circuit 59 is a positive polarity signal as shown in FIG.
Output to. As a result, the boosting means 51 has a circuit configuration as shown in FIG. 16, and the first switches 101 to 1
05 and the second switches 108 to 112 are time-divisionally controlled to generate a boosted voltage, and the boosted voltage is continuously output to the timepiece system 6, the second control means, and the detection circuit 50.

When the power source 1 has a negative polarity voltage, the detection signal of the detection circuit 50 becomes "H" and the output of the selection circuit 59 outputs a negative signal as shown in FIG. As a result, the boosting means 51 has a circuit configuration as shown in FIG. 17 and the first switches 102 to 106.
And the second switches 107 to 111 are time-divisionally controlled to generate a boosted voltage, and the boosted voltage is continuously output to the timepiece system 6, the second control means, and the detection circuit 50.

As described above, in the fourth embodiment of the present invention, the first switch 1 constituting the boosting means 51 when the control is transferred from the first control means 52 to the second control means 53.
01-106 and the second switches 107-112 are switched between the substrate potentials depending on the gate voltage applied to the gate terminals of the first switches 101-106 and the second switches 107-112. Are switching.

This is to eliminate the back gate effect due to the difference in gate voltage applied to the gate terminal.

The first and second embodiments of the present invention described above
In the third embodiment, the third embodiment, and the fourth embodiment, the boosting means is composed of five charging means, but the charging means is charged according to the output voltage of the power source 1 or the power consumption of the load. Means 2
It may consist of more than one piece.

Further, the first switch and the second switch forming the boosting means in the first, second, third, and fourth embodiments of the present invention are P Type field effect transistor and N type field effect transistor are used, a transmission type analog switch may be used.

The rectifier circuit used in the second and third embodiments of the present invention may use a diode ring or the like if the power supply voltage is large to some extent.

Further, although the first tri-state buffer means and the second tri-state buffer means in the third and fourth embodiments of the present invention use tri-state buffers, they are of the transmission type. You may use an analog switch.

[0127]

According to the booster circuit of the present invention, it is necessary to connect the N capacitors in series in the booster circuit of the conventional example by adopting a configuration in which N capacitors are connected in series in advance. Since a switch is unnecessary, loss due to the on resistance of the switch is eliminated, and a large amount of power can be taken out.

Further, in the booster circuit of the conventional example, it is necessary to recharge the boosted voltage charged in each capacitance to the boosted output capacitance, but in the booster circuit of the present invention, the capacitance connected in series determines the boosted output capacitance. In addition, the boosted voltage can be directly taken out from the other terminal of the capacitor connected in series, and there is no loss due to the transfer of electric power from the capacitor to the capacitor, so that the efficiency is improved.

Further, since each of the capacitors is always charged in a time-division manner, the ripple of the boosted voltage can be suppressed small and the boosted output voltage can be kept substantially constant.

Further, by providing the rectifier circuit between the power source and the boosting means and the control means, it is possible to always output the boosted voltage having a constant polarity to the load even if the polarity of the power source changes.

By providing a detection circuit for detecting the polarity of the power supply and a selection circuit for selectively outputting the second control signal output by the second ring counter means by the detection signal output by the detection circuit, Even if the polarity of the power supply changes, it is possible to always output a boosted voltage having a constant polarity to the load.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing a waveform of a control signal of the control means that constitutes the booster circuit according to the first exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a state in which each of the capacitors forming the booster circuit according to the first embodiment of the present invention is charged.

FIG. 4 is a circuit diagram showing a circuit configuration of a booster circuit of a conventional example.

FIG. 5 is a diagram showing how the respective capacities of the booster circuit of the conventional example are charged.

FIG. 6 is a diagram showing a manner in which a boosted output capacitance forming a booster circuit of a conventional example is charged.

FIG. 7 is a diagram showing a block diagram of a booster circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a circuit configuration of a rectifier circuit which constitutes a booster circuit according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a block diagram of a booster circuit according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram showing a circuit configuration of a booster circuit according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram showing a circuit configuration of a switching circuit which constitutes a first control means in a third exemplary embodiment of the present invention.

FIG. 12 is a diagram showing a block diagram of a booster circuit according to a fourth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a circuit configuration of a booster circuit according to a fourth embodiment of the present invention.

FIG. 14 is a circuit diagram showing a circuit configuration of a second ring counter means and a selection circuit which constitute a second control means in the fourth exemplary embodiment of the present invention.

FIG. 15 is a circuit diagram showing a circuit configuration of a detection circuit according to a fourth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a circuit configuration of boosting means when a power source has a positive polarity in a fourth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a circuit configuration of booster means when a power source has a negative polarity in a fourth embodiment of the present invention.

FIG. 18 is a waveform diagram showing waveforms of control signals of the first control means and the second control means in the fourth example of the present invention.

[Explanation of symbols]

 1 Power Supply 2 Oscillation Means 3 Ring Counter Means 4 Control Means 5 Booster Means 6 Clock System

Claims (9)

[Claims] 1. A control means comprising a power supply, an oscillating means and a ring counter means for outputting a time-division control signal, and a capacitor and a capacitor connected to one terminal of the capacitor to supply the potential of one terminal of the power supply. Boosting means for connecting N (N ≧ 2) charging means in series with one switch and a second switch connected to the other terminal of the capacitor and supplying the potential of the other terminal of the power source, The booster circuit is characterized in that the output of the control means is connected to N first switches and second switches constituting the booster means. 2. A control means comprising a power supply, a rectifier circuit located between the power supply, the boosting means and the control means, an oscillating means and a ring counter means for outputting a time-division control signal, and a capacitance and a capacitance. It has a first switch connected to one terminal to supply the potential of one output terminal of the rectifier circuit and a second switch connected to the other terminal of the capacitor to supply the potential of the other output terminal of the rectifier circuit. And a boosting means for connecting N (N ≧ 2) charging means in series, and the output of the control means is connected to N first switches and second switches constituting the boosting means. And booster circuit. 3. A power supply, a rectifier circuit located between the power supply, the boosting means and the first control means, a first ring counter means for outputting a first control signal for time division with an oscillating means, and a first ring counter means. First tri-state buffer means for inputting the output of the first ring counter means and first control means comprising a switching circuit for controlling the first tri-state buffer means, and a time-division second control signal are output. Second control means comprising second ring counter means and second tri-state buffer means for inputting the output of the second ring counter means, and one of the rectifier circuit connected to the capacitance and one terminal of the capacitance. N charging means having a first switch for supplying the electric potential of the output terminal and a second switch connected to the other terminal of the capacitor for supplying the electric potential of the other output terminal of the rectifier circuit in series (N ≧ 2) Contact The output of the first control means and the output of the second control means are connected to N first switches and second switches constituting the boosting means. And booster circuit. 4. A power supply, an oscillation means, a first ring counter means for outputting a time-division first control signal, a first tri-state buffer means for inputting an output of the first ring counter means, and a first. First switching circuit for controlling the tri-state buffer circuit, the detection circuit for detecting the polarity of the power supply, and the second ring counter circuit for outputting the time-divisional second control signal. And a selection circuit for selectively outputting the output of the second ring counter means as the output of the detection circuit, a second tri-state buffer means for inputting the output of the selection circuit, and a second tri-state buffer means for controlling the second tri-state buffer means. Second control means composed of two switching circuits, a first switch connected to the capacitance and one terminal of the capacitance to supply the potential of one terminal of the power supply, and the other switch of the power supply connected to the other terminal of the capacitance And a boosting means for connecting N (N ≧ 2) charging means in series with a second switch for supplying the potential of the output terminal of the first control means and the second switch.
The output of the control means is connected to N first switches and second switches constituting the boosting means. 5. The rectifier circuit comprises a first rectifier between both terminals of the power supply.
Of the second P-type field effect transistor, the second P-type field effect transistor, the second N-type field effect transistor and the second N-type field effect transistor are connected in series.
Type field effect transistor and the second N type field effect transistor have their gate terminals connected to one terminal of the power source,
Connecting the gate terminals of the P-type field effect transistor and the first N-type field effect transistor to the other terminal of the power source,
The connection point between the first P-type field effect transistor and the second P-type field effect transistor and the connection point between the first N-type field effect transistor and the second N-type field effect transistor are output terminals of the rectifier circuit. The booster circuit according to claim 2 or 3, wherein: 6. A power supply, a control means comprising an oscillating means and a ring counter means for outputting a time-division control signal, and a capacitor and a capacitor connected to one terminal of the capacitor to supply the potential of one terminal of the power supply. Boosting means for connecting N (N ≧ 2) charging means in series with one switch and a second switch connected to the other terminal of the capacitor and supplying the potential of the other terminal of the power source, The output of the control means is connected to the N first switches and the second switch which constitute the boosting means, and controls the first switch and the second switch to sequentially supply the power to N capacitors. A method of driving a booster circuit, characterized in that the booster circuit is connected in a time-division manner and charged to generate a boosted voltage that is approximately N times the power supply voltage. 7. A control means comprising a power supply, a rectifier circuit located between the power supply, the boosting means and the control means, an oscillating means and a ring counter means for outputting a time-division control signal, and a capacitance and a capacitance. It has a first switch connected to one terminal to supply the potential of one output terminal of the rectifier circuit and a second switch connected to the other terminal of the capacitor to supply the potential of the other output terminal of the rectifier circuit. There is a boosting means for connecting N (N ≧ 2) charging means in series, and the output of the control means is connected to the N first switches and the second switch which constitute the boosting means. Even if the polarity changes, the output of the rectifier circuit always outputs the polarity in the same direction, and the output of the control means controls the first switch and the second switch,
A method of driving a booster circuit, which comprises sequentially charging the output voltage of the rectifier circuit into N capacitors in a time-division manner and charging them to generate a boosted voltage that is approximately N times the power supply voltage. 8. A power supply, a rectifier circuit located between the power supply, the boosting means, and the first control means, a first ring counter means for outputting a first control signal for time division, the oscillation means, and a first ring counter means. First tri-state buffer means for inputting the output of the first ring counter means and first control means comprising a switching circuit for controlling the first tri-state buffer means, and a time-division second control signal are output. Second control means comprising second ring counter means and second tri-state buffer means for inputting the output of the second ring counter means, and one of the rectifier circuit connected to the capacitance and one terminal of the capacitance. N charging means having a first switch for supplying the electric potential of the output terminal and a second switch connected to the other terminal of the capacitor for supplying the electric potential of the other output terminal of the rectifier circuit in series (N ≧ 2) Contact And a second rectifying circuit for connecting the output of the first control means and the output of the second control means to the N first switches and the second switch forming the boosting means. Always supplies a voltage having the same polarity to the boosting means and the first control means even if the polarity of the power source changes, and the first switch and the second switch forming the boosting means by the output of the first control means. , And the output voltage of the rectifier circuit is sequentially connected to the N capacitors in a time-sharing manner to charge,
The boosted voltage which is approximately N times the power supply voltage is supplied to the second control means and the load to drive the load, and the clock of the load is input to the second ring counter means that constitutes the second control means. The output signal stops the oscillating means, the load output signal disables the output of the first tri-state buffer means via the first switching circuit, and the load output signal outputs the second tri-state. A method of driving a boosting circuit, characterized in that the output of the state buffer means is enabled and the control of the boosting means is switched from the first control means to the second control means. 9. A power supply, an oscillation means, a first ring counter means for outputting a time-division first control signal, a first tri-state buffer means for inputting an output of the first ring counter means, and a first. First switching circuit for controlling the tri-state buffer circuit, the detection circuit for detecting the polarity of the power supply, and the second ring counter circuit for outputting the time-divisional second control signal. And a selection circuit for selectively outputting the output of the second ring counter means as the output of the detection circuit, a second tri-state buffer means for inputting the output of the selection circuit, and a second tri-state buffer means for controlling the second tri-state buffer means. Second control means composed of two switching circuits, a first switch connected to the capacitance and one terminal of the capacitance to supply the potential of one terminal of the power supply, and the other switch of the power supply connected to the other terminal of the capacitance And a boosting means for connecting N (N ≧ 2) charging means in series with a second switch for supplying the potential of the output terminal of the first control means and the second switch.
The output of the control means is connected to the N first switches and the second switch that constitute the boosting means, and the power supply supplies the voltage to the boosting means and the first control means, and the first control A first switch and a second switch which constitute a boosting means by the output of the means.
, The power source is sequentially connected to the N capacitors in a time-sharing manner to charge, and a boosted voltage that is approximately N times the power source voltage is supplied to the second control means and the load to drive the load. Then, the clock of the load is input to the second ring counter means constituting the second control means, the signal output by the load is the first control signal that stops the oscillation means, and the signal output by the load is the first signal. The output of the first tri-state buffer means is disabled through the first switching circuit, and the signal output by the load enables the output of the second tri-state buffer means, and the first control means outputs the second tri-state buffer means. The second ring counter means by the selection circuit which switches the control of the boosting means to the control means to boost the voltage, detects the change in the negative polarity of the power supply by the detection circuit, and uses the output of the detection circuit to form the second control means. of By switching the power, by always constant direction charging direction into the capacitor, the driving method of the booster circuit, characterized in that for generating a boosted voltage regardless of the polarity of the power supply.