JPH0897693A - Output buffer compensation circuit - Google Patents

Abstract

PURPOSE: To prevent a change in an output slew rate depending on deterioration with aging, working conditions, etc., by detecting a current drive capability of a semiconductor element in an internal circuit so as to correct the slew rate of an output buffer corresponding to the capability. CONSTITUTION: A detection means P4 detecting at least a current drive capability of a semiconductor element in an internal circuit P2 is provided in a semiconductor substrate P3 including an output buffer P1. Since the detection means P4 is set on the same semiconductor substrate as the output buffer P1, the manufacturing dispersion, deterioration with aging, operating temperature conditions, etc., are respectively identical to each other, the current drive capability of the output buffer P1 is estimated by using the detection means P4 to detect a current drive capability of the semiconductor element of the internal circuit P2. Thus, how much unsharpened the slew rate of the output buffer P1 is confirmed and a correction means P5 corrects the slew rate of the output buffer P1 based thereon. Thus, a change in the slew rate of the output buffer P1 is prevented due to manufacturing dispersion, deterioration with age and working conditions or the like and any malfunction caused by simultaneous switching noise and ground bounce is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an output buffer for amplifying a weak signal from an internal circuit formed on a semiconductor substrate as a signal output from the semiconductor substrate (improving current driving capability). Such an output buffer compensation circuit.

[0002]

2. Description of the Related Art Conventionally, as the output buffer of the above example,
For example, there is a circuit configuration shown in FIG. That is, P is provided between the input terminal 81 for inputting a weak signal from the internal circuit and the output terminal 82 for outputting a current-amplified output signal.
Channel MOS transistor 83 and N channel MO
C-MOS with S transistor 84 connected as shown
(Complementary MOS) is an output buffer.

The P-channel MOS transistor 8 described above
3 is OF when the high level signal H is applied to its gate
It becomes F (non-conducting) and becomes ON (conducting) when the low level signal L is applied. On the contrary, the N-channel MOS transistor 84 is turned on (conductive) when a high level signal H is applied to its gate, and turned off (non-conductive) when a low level signal L is applied.

Therefore, when the low level signal L is applied to the input terminal 81 as shown in FIG. 8, the current amplified high level signal H is output to the output terminal 82, and as shown in FIG. When the high level signal H is applied to the input terminal 81 of the above, the current amplified low level signal L is output to the output terminal 82. In short, an output signal in which the input signal is current-amplified (current-driving capability is increased) and logically inverted is obtained. Then, normally, an output buffer having a C-MOS structure as shown in FIGS. 8 and 9 is combined in the front stage and the rear stage, and the physical size of the MOS transistor in the front stage is made small and the physical size of the MOS transistor in the rear stage is made small. It is used with a large size. On the other hand, since the MOS transistor has a large gate impedance, the gate and the ground (same as the ground) 87 as shown by the phantom lines in FIGS.
A parasitic capacitance (capacitor) 85 is formed between and in the form of an equivalent circuit.

By the way, when the internal circuit and the above-mentioned output buffer are housed in a package for packaging and a lead frame is attached to this package, there is an inductance component in this lead frame,
There were the following problems.

That is, since the inductance due to the lead frame described above exists on the side of the power supply terminal 86 and the side of the ground 87 in FIGS. 8 and 9, for example, when the current starts being supplied, that is, the P-channel MOS transistor 83 is turned on.
When switching from FF to ON, the counter electromotive force shown in [Equation 1] is generated next due to the above-mentioned inductance.

[0007]

[Equation 1]

Under the influence of this counter electromotive force, the power supply terminal 86
10, for example, drops from 5V to 4V, and similarly, the voltage on the ground 87 side also rises from 0V to 1V due to the influence of the back electromotive force. Due to the presence of the inductance component in the lead frame as described above,
The voltage of the power supply line that circulates inside the semiconductor substrate and the voltage of the ground line fluctuate, and a high level H and a low level L for a signal input to the semiconductor substrate.
Since the determination area of 1 becomes narrow, it becomes difficult to determine the high level H and the low level L, and malfunction occurs. Such malfunctions have been conventionally recognized as simultaneous switching noise and ground bounce (floating of ground level).

In order to solve such a problem, there is a means for reducing di / dt (time change rate of current) in the above [Formula 1]. That is, the means for reducing the number of output buffers that are output at the same time, and the current change rate di / dt are smoothed (here, “Nanara” means slowing down the speed at which the current changes). Rate d
It is roughly divided into two means for reducing i / dt.

The former means is a means for reducing di / dt by limiting the number of output buffers that are switched at the same time. However, because a data bus is usually used in a microcomputer or the like, an application (appl) is used.
There is a problem in ication, and it is not practical. The latter means smoothes the output of the output buffer from changing from the high level H to the low level L or from the low level L to the high level H, and lowers the current change rate di / dt, thereby reducing the simultaneous switching noise. However, this latter means also has the following problems.

That is, as shown in FIG. 11 showing the slew rate (change rate of output), this slew rate has an upper limit and a lower limit. If it is excessively smoothed, the lower limit of the slew rate is inevitably determined due to the flow-through current from the power supply to the ground at the input stage of the next-stage IC (integrated circuit formed on another semiconductor substrate), which results in insufficient annealing. Simultaneous switching noise occurs when it occurs, so the upper limit of the slew rate is inevitably determined, and the allowable range of the slew rate is specified by the upper limit and the lower limit of the slew rate.

Therefore, the slew rate capability of the output buffer in the state where the slew rate control is not executed should be controlled so as to fall within the above-mentioned slew rate allowable range. conditions,
In addition to variations in the slew rate capability of the IC due to changes over time, there are variations in the target slew rate (slew rate allowable range), and it is difficult to make it uniform. In particular, the slew rate of the output buffer itself is difficult. There is a problem that an appropriate slew rate cannot be obtained when the target allowable range of the slew rate is narrow with respect to the range of the rate capability variation.

On the other hand, as disclosed in Japanese Unexamined Patent Publication No. 5-110401, a MOS transistor as a switching element is provided on the power supply side and the ground side of an inverter having a C-MOS structure to effectively reduce the through current. Although there is an output buffer configured, this conventional output buffer also has the same problem as described above.

[0014]

SUMMARY OF THE INVENTION The invention according to claim 1 of the present invention detects at least the current driving capability of a semiconductor element in an internal circuit, and the slew rate of an output buffer corresponding to the detected current driving capability. To prevent the output buffer slew rate from changing due to manufacturing variations, aging, operating temperature conditions, etc., and to properly prevent malfunctions due to simultaneous switching noise and ground bounce. It is an object of the present invention to provide an output buffer compensation circuit capable of

According to a second aspect of the present invention, in addition to the object of the first aspect of the invention, the current drive capability of the semiconductor element is detected by the oscillation frequency of the ring oscillator provided in the same semiconductor substrate. Therefore, an object of the present invention is to provide an output buffer compensating circuit that can correct the slew rate of the output buffer based on the output from the ring oscillator without attaching an additional device to the outside of the semiconductor substrate.

[0016]

According to a first aspect of the present invention, there is provided an output buffer compensating circuit having an output buffer for amplifying a weak signal from an internal circuit as a signal output from a semiconductor substrate. Detecting means for detecting at least the current driving capability of the semiconductor element in the internal circuit on the same substrate, and correcting means for correcting the slew rate of the output buffer in accordance with the current driving capability detected by the detecting means. It is an output buffer compensating circuit provided with.

According to a second aspect of the present invention, in addition to the configuration of the first aspect of the invention, the detecting means is a ring oscillator in which the current driving capability of the semiconductor element is provided in the semiconductor substrate. The output buffer compensation circuit detects the oscillation frequency.

[0018]

According to the invention described in claim 1 of the present invention, as shown in the claim correspondence diagram of FIG. 7, the output buffer P1 outputs the weak signal from the internal circuit P2 from the semiconductor substrate P3. The detected signal P4 detects at least the current drivability of the semiconductor elements in the internal circuit P2 in the same semiconductor substrate P3, and the correction device P5 detects the detected signal P4. The slew rate (rate of change in output) of the output buffer P1 is corrected in accordance with the current driving capability detected by.

In order to judge the current driving capability of the output buffer P1 in this way, the above-mentioned detecting means P4 is formed in the same semiconductor substrate P3. In other words, since they are on the same semiconductor substrate P3, there is no manufacturing variation, and the secular change and the operating temperature condition are the same.
By detecting the current drivability of the semiconductor element, the current drivability of the output buffer P1 can be estimated,
With this, it is possible to confirm how much the slew rate of the output buffer P1 should be rounded, and the correction means P5 corrects the slew rate of the output buffer P1 based on this, so that manufacturing variations, aging changes, operating temperature conditions, etc. As a result, it is possible to prevent the slew rate of the output buffer P1 from changing, and consequently to prevent malfunctions due to simultaneous switching noise and ground bounce.

According to the second aspect of the present invention,
In addition to the effect of the invention described in claim 1, the above-mentioned detecting means is constituted by a ring oscillator provided in the same semiconductor substrate, and the current drive capability of the semiconductor element is detected by the oscillation frequency of the ring oscillator.

That is, by detecting the oscillation frequency of the ring oscillator, the delay time per one stage of the output buffer can be recognized. The shorter the delay time, the larger the current driving capability (when the oscillation frequency of the ring oscillator is high, Since the current driving capability is large), the slew rate can be appropriately corrected.

As described above, by detecting the current driving capability of the semiconductor element by the oscillation frequency of the ring oscillator provided in the same semiconductor substrate, the output of the ring oscillator can be output without adding any additional device outside the semiconductor substrate. Based on the above, there is an effect that the slew rate of the output buffer can always be statically corrected so that noise and shoot-through current are not generated.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. The drawing shows an output buffer compensation circuit, and in FIG. 1, a plurality of input buffers 2, ..., An internal circuit 3, a plurality of output buffers 4, and a slew rate control circuit 5 are formed on a semiconductor substrate 1. .

The input buffers 2 ... Are circuits that receive a signal from the outside of the semiconductor substrate 1 and convert the signal into a signal that can be handled by the internal circuit 3. Also, the output buffer 4 described above
Is a circuit that current-amplifies a weak signal from the internal circuit 3 as a signal output from the semiconductor substrate 1. The specific circuit configurations of the output buffer 4 and the slew rate control circuit 5 described above are as shown in FIG.

First, the circuit structure of the output buffer 4 will be described. In this embodiment, C-MOSs are formed in the front and rear stages. That is, a P-channel MOS transistor 8 and an N-channel MO are provided between the power supply terminal 6 and the ground 7.
The S-transistor 9 is connected to form the rear amplification section 10, while the P-channel MOS transistors 11 and 12 and the N-channel M are provided between the power supply terminal 6 and the ground 7.
The OS transistors 13 and 14 are connected to form the front-stage amplification units 15 and 16.

Moreover, the front side amplification section 15 corresponds to the P-channel MOS transistor 8 of the rear side amplification section 10.
An N-channel MOS transistor 17 acting as a variable resistor is interposed between the source S of the N-channel MOS transistor 13 and the ground 7 in the above, while corresponding to the N-channel MOS transistor 9 of the post-stage amplification section 10, P-channel MOS in the front amplification section 16
A P-channel MOS transistor 18 acting as a variable resistance is provided between the source S of the transistor 12 and the power supply terminal 6.

Further, the drain D of the P-channel MOS transistor 8 and the N-channel N
An intersection 19 of the OS transistor 9 and the drain D is connected to an output pad (output terminal) 20. Further, an MO that constitutes a C-MOS in the front-stage side amplification units 15 and 16
The S transistors 11, 13, 12, and 14 are respectively connected to the input terminal 21 that receives a weak signal from the internal circuit 3. Here, the N-channel MOS transistor 17 and the P-channel MOS transistor 1 separately provided for the C-MOS in the above-mentioned front-stage side amplification units 15 and 16
Reference numeral 8 has the same function as a variable resistor according to slew rate control signals e and f described later.

Next, the circuit configuration of the slew rate control circuit 5 will be described. An odd number of inverters (inversion circuits) 2 are provided.
A ring oscillator 23 configured by serially and ring-connecting 2 ... Is provided, the output side of the ring oscillator 23 is connected to a counter 24 (pulse counter), and the reference signal b (for example, crystal oscillation is divided by this counter 24). The reference signal thus formed) is configured to count the number of pulses oscillated from the ring oscillator 23 while the high level H.

Since the ring oscillator 23 has an odd number of inverters 22, the output a, that is, the oscillation waveform shown in FIG. 3 is obtained at the output side thereof, and the half cycle α of this oscillation waveform is the above-mentioned. Since the delay time td of the inverter 22 is added to obtain a value Σtd, the delay time per one stage of the C-MOS can be estimated from the oscillation waveform of the ring oscillator 23.

That is, the above-mentioned delay time Σtd is in inverse proportion to the current drive capability, and the shorter the delay time Σtd,
This means that the current drive capacity is large. In other words, a signal cannot be obtained until electric charges are stored in a parasitic capacitor (capacitance) existing between the gate of the MOS transistor that constitutes the inverter 22 of the next stage and the ground. The signal will be transmitted soon. That is, when the delay time td of the ring oscillator 23 is short and the oscillation frequency thereof is high, the current driving capability becomes large.

Further, the counter 24 mentioned above has a line 2
Digital / analog converters (hereinafter simply referred to as D / A converters) 27 and 28 are connected via 5 and 26 respectively,
It is configured to convert the digital count outputs c and d into analog signals. Here, one D / A converter 28
, The counter output d of a predetermined number of bits is applied as it is,
The other D / A converter 27 is applied with a counter output c obtained by inverting the counter output d having a predetermined number of bits. For example,
When the counter output c is "00000100", the counter output d is its inverse, and therefore "1111101".
1 ”.

Then, the slew rate control signal e is obtained at the output of the one D / A converter 27, and the slew rate control signal e is supplied to the gate of the N channel MOS transistor 17 of the output buffer 4 via the line 29. The slew rate control signal f is obtained at the output of the other D / A converter 28, and the slew rate control signal f is applied to the gate of the P channel MOS transistor 18 of the output buffer 4 via the line 30. It is configured to be applied to.

Each of these MOS transistors 17, 18
Acts as a variable resistor by the slew rate control signals e and f described above, and one of the N-channel MOS transistors 1
7 controls the slew rate when the output buffer 4 changes from the low level to the high level (at the time of rising), and the other P-channel MOS transistor 18 controls the output buffer 4
Controls the slew rate when changes from high level to low level (falling edge).

The illustrated embodiment is configured as described above, and the operation will be described below. First, the case where the current driving capability of the IC is increased based on FIG. 3 will be described. When the current driving capability is increased, the ring oscillator 23 will be described.
Of the ring oscillator output a increased while the reference signal b is at the high level H, the number of pulses of the ring oscillator output a increases. Therefore, assuming that the current count value is n, the relational expression of previous count value <current count value n 1 holds.

The present count value n and the inversion signal of the present count value n are applied to the D / A converters 28 and 27 as counter outputs d and c, respectively. Slew rate control signals f and e shown in 3 are obtained.

One slew rate control signal e is, for example, 4
V to 1.5V, this voltage is N channel MO
Since it is applied to the gate of the S-transistor 17, the resistance value of this MOS transistor 17 acting as a variable resistance becomes large, and the rise of the output buffer 4 becomes slow,
The slew rate decreases.

The other slew rate control signal f is, for example, 1
Raise from V to 3.5V, and this voltage is P channel MO
Since it is applied to the gate of the S-transistor 18, the resistance value of this MOS transistor 18, which acts as a variable resistance, becomes large, and the fall of the output buffer 4 is delayed,
The slew rate decreases.

In this way, when the oscillation frequency of the ring oscillator 23 becomes high (when the processing speed of the ring oscillator 23 is high), the slew rate of the output buffer 4 is lowered as shown in FIG. 4 (from the solid line to the dotted line). Control to be transferred)
At, the slew rate of the output buffer 4 is kept within the allowable range. The slew rate control signals e and f shown in FIG.
Corresponds to FIG.

Next, referring to FIG. 5, the case where the current driving capability of the IC is reduced will be described. When the current driving capability is reduced, the oscillation frequency of the ring oscillator 23 is lowered, so that the reference signal b is reduced. During the high level, the number of pulses of the ring oscillator output a counted by the counter 24 decreases. Therefore, assuming that the current count value is m, the relational expression of previous count value> current count value m is established.

The present count value m and the inverted signal of the present count value m are applied to the D / A converters 28 and 27 as counter outputs d and c, respectively. The slew rate control signals f and e shown in 5 are obtained.

On the other hand, the slew rate control signal e rises from 1.5V to 4V, for example, and this voltage is N channel M.
Since it is applied to the gate of the OS transistor 17, the low resistance value of this MOS transistor 17 acting as a variable resistance is reduced, the rise of the output buffer 4 is accelerated, and the slew rate is increased.

The other slew rate control signal f drops from 3.5V to 1V, for example, and this voltage is applied to the P channel M.
Since the voltage is applied to the gate of the OS transistor 18, the resistance value of the MOS transistor 18, which acts as a variable resistance, becomes small, the fall of the output buffer 4 is accelerated, and the slew rate is increased.

In this way, when the oscillation frequency of the ring oscillator 23 becomes low (when the processing speed of the ring oscillator 23 is slow), the control for increasing the slew rate of the output buffer 4 (from the solid line to the dotted line) as shown in FIG. Control to be transferred)
At, the slew rate of the output buffer 4 is kept within the allowable range.

In short, the above-mentioned output buffer 4 current-amplifies (increases the current driving capability) the weak signal from the internal circuit 3 as a signal output from the semiconductor substrate 1, but the above-mentioned detection means (the ring oscillator 23 and the counter). Two
4) detects at least the current drivability (processing speed in this embodiment) of the semiconductor element in the internal circuit 3, and the correction means (see D / A converters 27 and 28 and MOS transistors 17 and 18) is detection means. The slew rate (change rate of output) of the output buffer 4 is corrected according to the current driving capability detected by.

In order to judge the current driving capability of the output buffer 4 as described above, the above-mentioned detecting means is formed in the same semiconductor substrate 1. In other words, since there is no manufacturing variation because they are on the same semiconductor substrate 1 and the same aging change and operating temperature condition, the current of the output buffer 4 is detected by detecting the current drive capability of the semiconductor element of the internal circuit 3 by the detection means. The driving ability can be estimated, and by this, it is possible to confirm how much the slew rate of the output buffer 4 should be rounded. Based on this, the correction means corrects the slew rate of the output buffer 4, so that there is a manufacturing variation. ,
This has the effect of preventing the slew rate of the output buffer 4 from changing due to aging, operating temperature conditions, etc., and thus preventing malfunctions due to simultaneous switching noise and ground bounce.

Further, the above-mentioned detecting means is constituted by the ring oscillator 23 provided in the same semiconductor substrate 1, and the current drive capability of the semiconductor element is detected by the oscillation frequency of the ring oscillator 23. That is, the delay time of the output buffer 4 can be recognized by detecting the oscillation frequency of the ring oscillator 23, and the shorter the delay time is, the larger the current driving capability is, so that the slew rate can be appropriately corrected. .

As described above, the ring oscillator 23 having the same current driving capability as that of the semiconductor element is provided in the same semiconductor substrate 1.
By detecting the oscillation frequency of the ring oscillator 23, the slew rate of the output buffer 4 is determined based on the output of the ring oscillator 23 without adding an additional device to the outside of the semiconductor substrate 1 so that noise and shoot-through current are not generated. It has the effect that it can always be corrected statically.

In the correspondence between the configuration of the present invention and the above-described embodiment, the detection means for detecting at least the current driving capability of the present invention corresponds to the ring oscillator 23 and the counter 24 for detecting the processing speed of the embodiment. Similarly, the correction means for correcting the slew rate of the output buffer is D /
A converters 27 and 28, an N channel MOS transistor 17 acting as a variable resistance, and a P channel MO
Although it corresponds to the S transistor 18, the present invention is not limited to the configuration of the above-described embodiment. Moreover, the numerical values of the voltages shown in the embodiments are merely examples.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a semiconductor substrate configuration including an output buffer compensation circuit of the present invention.

FIG. 2 is an electric circuit diagram showing an output buffer and a slew rate control circuit.

FIG. 3 is an explanatory diagram of each signal when the oscillation frequency of the ring oscillator becomes high.

FIG. 4 is an explanatory diagram of control for reducing a slew rate.

FIG. 5 is an explanatory diagram of each signal when the oscillation frequency of the ring oscillator becomes high.

FIG. 6 is an explanatory diagram of control for increasing a slew rate.

FIG. 7 is a claim correspondence diagram.

FIG. 8 is an electric circuit diagram showing a conventional output buffer.

FIG. 9 is an electric circuit diagram showing a logically inverted output state in a conventional output buffer.

FIG. 10 is an explanatory diagram of simultaneous switching noise.

FIG. 11 is an explanatory diagram showing a slew rate allowable range.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 3 ... Internal circuit 4 ... Output buffer 17 ... N channel MOS transistor 18 ... P channel MOS transistor 23 ... Ring oscillator 24 ... Counter 27, 28 ... D / A converter

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[Procedure amendment]

[Submission date] December 22, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

[Title of the Invention] output buffer compensation circuit

Claims (2)

[Claims] 1. An output buffer compensating circuit having an output buffer for current-amplifying a weak signal from an internal circuit as a signal output from a semiconductor substrate, wherein the semiconductor elements in the internal circuit have at least the same current driving capability. An output buffer compensating circuit comprising a detecting means for detecting in the substrate, and a correcting means for correcting the slew rate of the output buffer in accordance with the current driving capability detected by the detecting means. 2. The output buffer compensating circuit according to claim 1, wherein the detecting means detects the current driving capability of the semiconductor element by the oscillation frequency of a ring oscillator provided in the semiconductor substrate.