JPH0897421A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent a substrate from being damaged by anisotropic etching during sidewall formation by using an insulation film covering a gate electrode as a protective film during ion implantation by allowing it to remain partially in a thickness direction by performing under-etching for it. CONSTITUTION: A gate electrode is formed on a p-type silicon substrate 1 with a gate insulation film 2 therebetween and a source/drain region 4 of low concentration is formed using the gate electrode as a mask. Then, a silicon dioxide film (SiO2 film) 5 is formed on a substrate as an insulation film by vapor growth method. Anisotropic etching is performed for a substrate surface, an SiO2 film 5 is processed to be an implantation protective film to the substrate l and a sidewall consisting of the SiO2 film 5 is formed at a side surface of the gate electrode. Ion implantation is performed by using the SiO2 film 5 which is made to remain on the substrate as an implantation protective film and a gate electrode and a sidewall of a gate electrode side surface as an implantation mask, a deep source/drain region 6 of high concentration is formed and a thin part of the SiO2 film 5 is etched and removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a source and a drain of an LDD (Lightly Doped Drain) structure of FET.

In recent years, along with the high integration and miniaturization of semiconductor devices, it is desired in the manufacturing process thereof to simplify the process, shorten the process, prevent damage on the process, and stabilize the device.

[0003]

2. Description of the Related Art FIG. 2 is an explanatory view of a conventional example of forming a source and a drain. In this example, the FET of the cell part of the memory integrated circuit and the FET of the peripheral circuit part are shown.

Here, the source and drain of the FET in the cell portion have a single structure, and the FET in the peripheral circuit portion has an offset structure, that is, an LDD structure. In Fig. 2 (A), a gate electrode 3 is formed on a p-type silicon (p-Si) substrate 1 via a gate insulating film 2, and a low concentration shallow source / drain region 4 is formed using the gate electrode as an implantation mask. To do.

In FIG. 2B, an insulating film 5A is deposited on the substrate and anisotropic etching is performed on the substrate surface. At this time, the inside of the cell is masked to leave the insulating film 5A, and the peripheral circuit portion leaves the insulating film 5A only on the side surface of the gate electrode. afterwards,
The insulating film 5B is deposited again on the substrate, and the side wall of the insulating film 5A and the insulating film 5B is formed again on the side surface of the gate electrode in the peripheral circuit portion by anisotropic etching.

At the same time, at the same time, a side wall of the insulating film 5B is formed in the cell portion, the substrate surface is flattened, and the step coverage of the wiring formed thereon is improved. For this reason, vapor deposition (CVD) is performed twice to form the insulating film.

During the anisotropic etching, the FET in the cell portion is covered with the insulating film 5A so that the substrate is not damaged, but the FET in the peripheral circuit portion is not damaged by the etching because the substrate surface is exposed. Occurs.

Therefore, the substrate surface is oxidized by using an asher and the oxide film is removed by hydrofluoric acid to clean the substrate surface. However, the damaged part cannot be completely removed. Since the FET in the cell area refreshes the memory, there is less margin for etching damage to the substrate than the FET in the peripheral circuit area, so anisotropic etching is performed over the cell area as described above. .

Next, a thin insulating film which is a protective film at the time of ion implantation is formed, and ion implantation is performed using the gate electrode and the side wall of the FET in the peripheral circuit portion as an implantation mask. To form.

[0010]

In the conventional example, since the substrate of the peripheral circuit portion is exposed during anisotropic etching, the substrate is damaged by etching. In addition, when the surface of the gate electrode is metal-silicided, the metal scatters on the substrate and causes contamination.

Further, the deposition of the insulating film and the anisotropic etching are each repeated twice, and further, the deposition of the protective insulating film at the time of ion implantation for forming the source and drain is required, which has a drawback that the number of processes is large.

It is an object of the present invention to prevent damage to a substrate due to anisotropic etching at the time of forming a side wall, simplify a manufacturing process, and improve device reliability and manufacturing yield.

[0013]

To solve the above problems, 1) a gate electrode is formed on a one-conductivity-type semiconductor substrate via a gate insulating film, and the gate electrode is used as an implantation mask, which is opposite to the semiconductor substrate. A step of implanting conductive type ions, an insulating film is deposited on the semiconductor substrate including the gate electrode, and anisotropic etching is performed to form a side wall made of the insulating film on the side surface of the gate electrode. A step of partially leaving the insulating film in the thickness direction, and using the insulating film left on the semiconductor substrate as an implantation protection film, and using the gate electrode and the sidewall as an implantation mask, ions of a conductivity type opposite to that of the semiconductor substrate. Or a method of manufacturing a semiconductor device having a higher concentration than the above-mentioned implantation, or 2) allowing the ions to pass through the implantation protection film according to the conditions of the ion implantation, and the anisotropic etching and Ion injection The method for manufacturing the semiconductor device according to the above 1, wherein the thickness is adjusted so that the substrate is not damaged by the insertion, or 3) the method for manufacturing the semiconductor device according to the above 1, wherein the wet etching is performed using a hydrofluoric acid-based etchant. Achieved by

[0014]

In the present invention, an insulating film is deposited to cover the gate electrode,
In order to prevent the surface of the substrate from being damaged by anisotropic etching when forming the side wall made of this insulating film on the side surface of the gate electrode, underetching is used to leave a part of this insulating film in the thickness direction and leave it as it is. Ion implantation for source and drain formation is performed by using a thin insulating film as a protective film during implantation.

Therefore, the surface of the substrate is not attacked by anisotropic etching due to the remaining thin insulating film, and it is not necessary to form a protective film for implantation in a separate process.

[0016]

Embodiments FIGS. 1A to 1D are explanatory views of an embodiment of the present invention. In FIG. 1 (A), a gate electrode 3 with a thickness of 200 nm is formed on a p-type silicon substrate 1 through a gate insulating film 2, and a low concentration shallow source / drain region 4 is formed using the gate electrode as an implantation mask. .

The implantation conditions at this time are: ion species P ⁺ , energy 40 KeV, and dose 1 × 10 ¹³ cm ^-2 . Here, the gate electrode has a polycide structure, and the polysilicon layer 3A
And a tungsten silicide (WSi) laminated structure.

In FIG. 1 (B), a 200 nm thick silicon dioxide as an insulating film is formed on the substrate by the vapor phase epitaxy (CVD) method.
A (CVD SiO ₂ ) film 5 is deposited, anisotropic etching is performed on the substrate surface, and a 20 nm thick CVD Si film is formed on the substrate as an injection protection film.
Leave the O ₂ film 5. At this time, a sidewall made of CVD SiO ₂ film 5 is formed on the side surface of the gate electrode by anisotropic etching.

An example of anisotropic etching conditions at this time is shown below. Reactive gas: CF ₄ / CHF ₃ / Ar Gas flow rate: 191/60/231 SCCM Gas pressure: 166.3 Pa RF power: 165 W At this time, the CVD SiO ₂ film 5 to be an injection protection film depends on the ion injection conditions. The thickness is adjusted so that the ions are transmitted and the substrate is not damaged by the anisotropic etching and the ion implantation. In this example, the film thickness was 20 nm.

In FIG. 1 (C), the CVD Si left on the substrate
Ion implantation is performed by using the O ₂ film 5 as an implantation protection film and the gate electrode and the side wall formed on the side surface of the gate electrode as an implantation mask to form deep source / drain regions 6 of high concentration.

Implantation conditions at this time are ion species As ⁺ , energy 70 KeV, and dose amount 1 × 10 ¹⁵ cm ^-2 . Figure 1 (D)
In is removed by wet etching a thin CVD SiO ₂ film 5 remaining in the CVD SiO ₂ film 5 and the substrate on the gate electrode with hydrofluoric acid or buffered hydrofluoric acid solution.

In the embodiment, the gate electrode material has a polycide structure composed of a laminated film of tungsten silicide and polysilicon, but is not limited to this, and a polycide structure using other metal silicide or a polysilicon film only. May be.

[0023]

According to the present invention, it is possible to prevent the substrate from being damaged by anisotropic etching when forming the side wall, simplify the manufacturing process, and improve the reliability and the manufacturing yield of the device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 p-type silicon substrate 2 gate insulating film 3 gate electrode 3A polysilicon layer 3B tungsten silicide layer 4 low-concentration shallow source / drain region 5 CVD SiO ₂ film and sidewall 6 high-concentration deep source / drain region

Claims (3)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate of one conductivity type through a gate insulating film, implanting ions of a conductivity type opposite to that of the semiconductor substrate using the gate electrode as an implantation mask, and the gate. A step of depositing an insulating film on the semiconductor substrate including electrodes, performing anisotropic etching to form a side wall made of the insulating film on the side surface of the gate electrode, and leaving a part of the insulating film in the thickness direction; , Using the insulating film left on the semiconductor substrate as an implantation protection film and using the gate electrode and the sidewall as an implantation mask to implant ions of a conductivity type opposite to that of the semiconductor substrate at a higher concentration and deeper than the above implantation. A method of manufacturing a semiconductor device, comprising: 2. The implantation protection film is provided with a thickness adjusted so that ions are permeated according to the conditions of ion implantation and the substrate is not damaged by the anisotropic etching and ion implantation. The method of manufacturing a semiconductor device according to claim 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the wet etching is performed using a hydrofluoric acid-based etchant.