JPH0896582A - Semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a high speed sense-amplifier. CONSTITUTION: In this device, a sense-amplifier is constituted so that a bit line is charged to a certain precharge potential by applying a negative feedback while inputting the potential of the bit line to an inverter at the time of precharging a memory cell connected to the bit line and while impressing the output of the inverter to an N type field effect transistor M1 for precharge. The difference between achieved potentials of the bit line of the ON time and the OFF time of the memory cell is amplified by an inverter INV1 consisting of an N type field effect transistor M3 and a resistor element R1 and applying the negative feedback to be outputted to an output node SOUT1. A sense operation is finished in conjunction with the completion of the precharge by making this output the output of the sense-amplifier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device used for a sense amplifier.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram of a semiconductor device used for a conventional and generally known sense amplifier.

In FIG. 7, the semiconductor device used for the sense amplifier includes an inverter INV7, N-type field effect transistors M1 and M2, and a resistance element R2. Inverter INV7 further includes an N-type field effect transistor M3 and a resistance element R1.

One terminal of the resistance element R1, the source of the N-type field effect transistor M1 and one terminal of the resistance element R2 are connected to the power supply voltage Vcc, and the drain of the N-type field effect transistor M3 is grounded.

At node 79, the gates of N-type field effect transistors M1 and M2, the source of N-type field effect transistor M3, and resistance element R1 are connected, and node 8 is connected.
1, the drains of the N-type field effect transistors M1 and M2, the gate of the N-type field effect transistor M3, and the terminal BL are connected. Here, the terminal BL is connected to a memory cell not shown in FIG. 7 via a bit line. At the output node SOUT7, the source of the N-type field effect transistor M2 and the resistance element R2 are connected.

Next, the operation will be described. First, the power supply voltage Vc
The bit line is precharged through the N-type field effect transistors M1 and M2 by c. At this time, the inverter IN
By applying negative feedback with V7, the bit line becomes constant at a certain potential lower than the power supply voltage. If a current is flowing through the memory cell connected to the bit line after the potential becomes constant, a part of the current passes through the resistance element R2 and the voltage drop caused at that time causes the output node SO
The potential of UT7 drops. If no current flows through the memory cell, the potential of the output node SOUT7 remains high. Therefore, information can be read from the memory cell.

[0007]

However, in the semiconductor device used for the sense amplifier of FIG. 7, the sense operation precharges the bit line, and then the minute current flowing through the memory cell is further reduced. The memory cell is turned on for the first time by driving a load consisting of a resistance element R2 and an external load capacitance not shown in FIG.
Since the off state is detected, there is a problem that it takes time to sense.

The present invention has been made to solve the above problems, and an object thereof is to obtain a high-speed sense amplifier.

[0009]

A semiconductor device according to claim 1 of the present invention is a semiconductor device for detecting a potential of a memory cell connected to a bit line by a potential of the bit line, wherein a predetermined memory cell is provided on the bit line. Applying means for applying the precharge potential, output means for inputting a detection signal corresponding to the applied potential and outputting an inverted signal thereof as the output of the semiconductor, and control for controlling the potential of the memory cell by the inverted signal And means are provided.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, further comprising a supplying means for continuously supplying a precharge potential of a predetermined memory cell to the applying means. is there.

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, further comprising means for amplifying the inverted signal.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein the semiconductor devices form a pair, one of the pair is connected to the memory cell, and the other of the pair is connected to the dummy cell. Connected to each pair of semiconductor devices,
Differential amplification means for amplifying the difference between the outputs is further provided.

[0013]

In the semiconductor device according to the first aspect of the present invention, the precharge potential of a predetermined memory cell is applied to the bit line, the detection signal corresponding to the applied potential is input, and the inverted signal thereof is the above-mentioned. Since it is output as the output of the semiconductor device and the potential of the memory cell is controlled by the inversion signal, an inverter for negative feedback is configured, and the inversion signal output from the inverter is used to turn on the memory cell at the end of precharge. The difference between the reaching potential of the bit line at the time of turning off and that at turning off is amplified.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the precharge potential of the memory cell is continuously supplied and applied.
It is possible to further increase the difference in the reaching potential of the bit line when the memory cell is turned on and when it is turned off at the end of precharge.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, since the inverted signal is amplified, the reaching potential of the bit line at the time of turning on and off the memory cell at the end of precharge. The difference is further amplified.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the semiconductor devices form a pair, one of the pair is connected to the memory cell, and the other of the pair is connected to the dummy cell. Since the difference between the outputs of the semiconductor devices connected to the pair of semiconductor devices is amplified, the difference between the reaching potentials of the bit lines at the time of turning on and off the memory cells at the end of precharge is further amplified, In addition, the effect of parameter variation is offset.

[0017]

【Example】

(1) First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device used in the sense amplifier of the present invention.

In FIG. 1, the semiconductor device 1 used for the sense amplifier includes an inverter INV1 and an N-type field effect transistor M1. Inverter INV1 further includes an N-type field effect transistor M3 and a resistance element R1.

The source of the N-type field effect transistor M1 and one terminal of the resistance element R1 are connected to the power supply voltage Vcc, and the drain of the N-type field effect transistor M3 is grounded.

At the node 107, the drain of the N-type field effect transistor M1 and the gate of the N-type field effect transistor M3 are connected to the terminal BL. Here, the terminal BL is
It is connected to the memory cell via a bit line. At the output node SOUT1, the gate of the N-type field effect transistor M1 and the resistance element R1 are connected.

Next, the operation will be described. A power supply voltage is applied from the terminal 101 to the bit line as a precharge voltage for the memory cell through the N-type field effect transistor M1. Then, the difference in the reaching potential of the bit line when the memory cell is turned on and when it is turned off at the end of the precharge is amplified by the inverter INV1 for applying the negative feedback, and the inverter IV1.
It is output from the output node SOUT1 as the output of NV1.

Therefore, by using the output of the sense amplifier as the output of the sense amplifier, it is possible to obtain a high-speed sense amplifier in which the sensing operation is completed when the precharge of the memory cell is completed.

Here, a transistor load may be used for the resistance element R1. (2) Second Embodiment FIG. 2 is a circuit diagram showing a second embodiment of the semiconductor device used in the sense amplifier of the present invention.

In FIG. 2, the semiconductor device 2 includes an inverter INV2 and N-type field effect transistors M1 and M2. The inverter INV2 further includes an N-type field effect transistor M3 and resistance elements R1 and R3.

The source of the N-type field effect transistor M1, the source of the N-type field effect transistor M2, and one terminal of the resistance element R1 are connected to the power supply voltage Vcc, and the drain of the N-type field effect transistor M3 is grounded. .

At node 119, gate resistance elements R1 and R3 of N-type field effect transistor M1 are connected, and at node 121, N-type field effect transistors M1 and M2.
Of the N-type field effect transistor M3 is connected to the terminal BL. Here, the terminal BL is connected to the memory cell via a bit line. At the output node SOUT2, the gate of the N-type field effect transistor M2, the source of the N-type field effect transistor M3, and the resistance element R
3 and 3 are connected.

Next, the operation will be described. The bit lines are precharged through the N-type field effect transistors M1 and M2 in the same manner as in the first embodiment. But at this time,
Even after the N-type field effect transistor M2 is turned off, pulling up is further performed through the N-type field effect transistor M1 to increase the difference in the reaching potential of the bit line when the memory cell is on and when the memory cell is off. The difference in the reaching potential is amplified by the inverter INV2 that applies negative feedback, and is output from the output node SOUT2.

Therefore, two N-type field effect transistors for precharging the memory cell are provided like the N-type field effect transistors M1 and M2, and the threshold value is changed by the resistance elements R1 and R2 in the inverter INV2. By controlling separately, the difference in the reaching potential of the bit line, which is the output thereof, can be made larger, and if it is used as the output of the sense amplifier, the sense operation is completed with the end of the precharge of the memory cell in which the sense operation is easier. A high-speed sense amplifier can be obtained.

Here, the resistance elements R1 and R2 may be transistor loads. (3) Third Embodiment FIG. 3 is a circuit diagram showing a third embodiment of the semiconductor device used in the sense amplifier of the present invention.

In FIG. 3, the semiconductor device used for the sense amplifier includes the same two semiconductor devices as the semiconductor device 1 in the first embodiment, semiconductor devices 1 and 1 ', and a differential amplifier circuit OPA.

The inverter INV1 'of the semiconductor device 1',
And field effect transistors M11 and M31, resistance element R11, terminal DBL, and node 13
7 and the output node SOUT1 'correspond to the inverter INV1, the field effect transistors M1 and M3, the resistance element R1, the terminal BL, the node 107, and the output node SOUT1 of the semiconductor device 1 of the first embodiment, respectively. The connection relationship and operation are similar to those in the first embodiment.

A dummy cell is connected to the terminal DBL of the semiconductor device 1 ', and from the output node SOUT1',
A certain reference potential is generated.

The difference in the reaching potential of the terminal BL when the memory cell is turned on and when it is turned off at the end of the precharge is amplified by the semiconductor device 1 and output, and the output is the differential amplifier circuit OP.
A is input to the non-inverting input terminal + of A, and the output from the output node SOUT1 ′ of the semiconductor device 1 ′ is input to the inverting input terminal − of the differential amplifier circuit OPA to output node SOUT3 of the differential amplifier circuit OPA. The differential of the reaching potential of the bit line thus amplified is further differentially amplified and output.

Therefore, by using the semiconductor devices 1 and 1'of the same shape in contrast, the influence of the parameter variation is canceled out, and the parameter variation is small. Further, since the output of each inverter of the semiconductor devices 1 and 1'is used as the output of the sense amplifier and the output is simply amplified by using the differential amplifier circuit OPA, the sense operation is completed immediately after the end of the precharge. A high-speed sense amplifier can be obtained.

Here, the resistance elements R1 and R11 are
A transistor load can also be used.

A configuration is also possible in which the output of the semiconductor device 1, 1'is received by a cross-couple type sense amplifier.

FIG. 4 is a circuit diagram in which, in the semiconductor device of the third embodiment shown in FIG. 3, the semiconductor devices 1, 1'are replaced by the same two semiconductor devices 2, 2'as the semiconductor device of the second embodiment. is there.

In FIG. 4, the inverter INV2 'of the semiconductor device 2'and the field effect transistors M11, M are shown.
21 and M31, the resistance elements R11 and R31, the terminal DBL, the nodes 149 and 151, and the output node SOUT2 ′ are the inverter INV2 and the field effect transistors M1, M2, and M3 of the semiconductor device 2 of the second embodiment, respectively. , And the resistance elements R1 and R3, the terminal BL, the nodes 119 and 121, and the output node SOUT2, and the connection relation and operation of the semiconductor device 2 ′ are similar to those of the semiconductor device 2 of the second embodiment.

A dummy cell is connected to the terminal DBL of the semiconductor device 2 ', and a certain reference potential is generated from the output node SOUT2'.

The difference in the reaching potential of the terminal BL when the memory cell is turned on and when it is turned off at the end of precharge is amplified by the semiconductor device 2 and output from the output node SOUT2, and the output is non-inverted by the differential amplifier circuit OPA. The output from the output node SOUT2 ′ of the semiconductor device 2 ′ is input to the inverting input terminal − of the differential amplifier circuit OPA and amplified from the output node SOUT4 of the differential amplifier circuit OPA. The difference between the reaching potentials of the bit lines is further amplified and output. Therefore, the semiconductor devices 1, 1'of the same shape
In contrast, the effect of the parameter variation is canceled by the use of, so that the parameter variation is small. Further, since the output of the inverter of the semiconductor device 2, 2'is used as the output of the sense amplifier and the output is simply amplified by using the differential amplifier circuit OPA, the sense operation is completed at a high speed immediately after the end of the precharge. You can get a good sense amplifier. At that time, since the difference in the reaching potential of the bit line is larger when the semiconductor devices 2 and 2'are used, the sensing operation is easier than when the semiconductor devices 1 and 1'are used. .

Here, the resistance elements R1, R3, R1
A transistor load can be used for 1 and R31.

A configuration is also possible in which the output of the semiconductor device 2, 2'is received by a cross-couple type sense amplifier. (4) Fourth Embodiment FIG. 5 is a circuit diagram showing a fourth embodiment of the semiconductor device used in the sense amplifier of the present invention.

In FIG. 5, the semiconductor device includes the same two semiconductor devices as those in the first embodiment, semiconductor devices 1 and 1 ', and a circuit C using a current mirror load. Here, the circuit C using the current mirror load is used to realize a differential amplifier circuit.

The semiconductor devices 1 and 1'are the same as the semiconductor devices 1 and 1'of the third embodiment, and their connection relationship and operation are the same as those of the third embodiment.

The circuit C using the current mirror load is
Type field effect transistors M41, M43 and P type field effect transistors M45, M47.

In the circuit C using the current mirror load, the P-type field effect transistor M45 is provided at the node 167.
And the sources of M47 are connected to the power supply voltage Vcc. At node 169, the gate and drain of P-type field effect transistor M45, the gate of P-type field effect transistor M47, and N-type field effect transistor M
41 sources are connected. At the node 171, the drains of the N-type field effect transistors M41 and M43 are connected to the terminal 165 and are grounded.

The output node SOUT1 of the semiconductor device 1 is
Connected to the gate of an N-type field effect transistor M41,
The output node SOUT1 'of the semiconductor device 1'is connected to the gate of the N-type field effect transistor M43. At the output node SOUT5, the N-type field effect transistor M4
3 is connected to the drain of the P-type field effect transistor M47.

When the power supply voltage Vcc is applied, the node 1 passes through the P-type field effect transistors M45 and M47.
69 and the output node SOUT5 have the same potential as the power supply voltage Vcc. Thereby, the P-type field effect transistor M45
The same voltage as the power supply voltage Vcc is applied to the gates of the P-type field effect transistors M45 and M47.
Becomes non-conductive.

Here, the difference in the reaching potential of the terminal BL at the time of turning on and off of the memory cell at the end of the precharge is amplified by the semiconductor device 1 and output from the output node SOUT1, and a certain reference potential is also applied to the semiconductor device. It is output from the 1'output node SOUT1 '.

The output voltage from the output node SOUT1 of the semiconductor device 1 is applied to the gate of the N-type field effect transistor M41, and the output voltage from the output node SOUT1 'of the semiconductor device 1'is applied to the gate of the N-type field effect transistor M43. Since each voltage is applied, N
The conduction states of the field effect transistors M41 and M43 are changed, and the difference in the reached potential of the amplified bit line is further amplified and output from the output node SOUT5.

Therefore, by using the semiconductor devices 1 and 1 ′ having the same shape in contrast, the influence of the parameter fluctuation is canceled out, so that the parameter fluctuation is small. Further, the output of the inverter of the semiconductor device 1 or 1'is used as the output of the sense amplifier, and the output is simply amplified by using the circuit C using the current mirror load. Therefore, the sense operation is performed immediately after the end of the precharge. A high-speed sense amplifier that completes can be obtained.

Here, the resistance elements R1 and R11 are
A transistor load can also be used.

A configuration is also possible in which the output of the semiconductor device 1, 1'is received by a cross-couple type sense amplifier.

FIG. 6 is a circuit diagram in which, in the semiconductor device of the fourth embodiment of FIG. 5, the semiconductor devices 1, 1'are replaced by the same two semiconductor devices 2, 2'as the semiconductor device of the second embodiment. .

In FIG. 6, the connection relationship and operation of the semiconductor devices 2 and 2'are the same as in the third embodiment.

A dummy cell is connected to the terminal DBL of the semiconductor device 2 ', and a certain reference potential is generated from the output node SOUT2'.

The output node SOUT2 of the semiconductor device 2 is
Connected to the gate of an N-type field effect transistor M41,
The output node SOUT2 'of the semiconductor device 2'is connected to the gate of the N-type field effect transistor M43. At the output node SOUT6, the N-type field effect transistor M4
3 is connected to the drain of the P-type field effect transistor M47.

When the power supply voltage Vcc is applied from the terminal 163, as in the example of FIG.
45 and M47 through node 169 and output node S
OUT6 has the same potential as the power supply voltage Vcc. As a result, the same voltage as the power supply voltage Vcc is applied to the gates of the P-type field effect transistors M45 and M47, and the P-type field effect transistors M45 and M47 are turned off.

Here, the difference in the reaching potential of the terminal BL at the time of turning on the memory cell at the end of precharge is amplified by the semiconductor device 2 and output from the output node SOUT2, and a certain reference potential is also applied to the semiconductor device. It is output from the 2'output node SOUT2 '.

The output voltage from the output node SOUT2 of the semiconductor device 2 is applied to the gate of the N-type field effect transistor M41, and the output voltage from the output node SOUT2 'of the semiconductor device 2'is applied to the gate of the N-type field effect transistor M43. Since each is applied, the conduction state of each of the N-type field effect transistors M41 and M43 changes according to the magnitude of the potential, and the difference between the reaching potentials of the bit lines is further amplified and output from the output node SOUT6. It Since the difference between the on-state and off-state reaching potentials of the memory cells at the end of precharge is larger when the semiconductor devices 2 and 2'are used than when the semiconductor devices 1 and 1'are used. The amplification effect by the circuit C using the load is also large.

Therefore, by using the same-shaped semiconductor devices 2 and 2'in contrast, the influence of the parameter variation is canceled out, and the parameter variation is small. In addition, the output of the inverter of the semiconductor device 2, 2'is converted into
Of the circuit C using the current mirror load.
Since the output is only amplified by using, it is possible to obtain a high-speed sense amplifier in which the sensing operation is completed immediately after the end of precharge. At that time, since the difference in the reaching potential of the bit line is larger than that when the semiconductor devices 1 and 1 ′ are used, the sensing operation becomes easier.

Here, the resistance elements R1, R3, R1
A transistor load can be used for 1 and R31.

A configuration is also possible in which the output of the semiconductor device 2, 2'is received by a cross-couple type sense amplifier.

Even if the N-type and P-type field effect transistors of all of the above-mentioned embodiments are replaced with P-type and N-type field effect transistors, the same construction can be achieved.

[0065]

As described above, in the semiconductor device according to the first aspect of the present invention, the precharge potential of the predetermined memory cell is applied to the bit line, and the detection signal corresponding to the applied potential is input. , The inverted signal is output as the output of the semiconductor, and the potential of the memory cell is controlled by the inverted signal, so that an inverter for negative feedback is formed, and the inverted signal output from the inverter is output at the end of precharge. The difference in the reaching potential of the bit line when the memory cell is turned on and when it is turned off is amplified.

As a result, a high-speed sense amplifier can be obtained by using the output of the inverter which applies the negative feedback as the sense amplifier output.

According to the semiconductor device of claim 2, in the semiconductor device of claim 1, since the precharge potential is continuously supplied and applied, the reaching potential of the bit line when the memory cell is on and when it is off. The difference between can be made larger.

As a result, it is possible to obtain a high-speed sense amplifier which facilitates the sensing operation by using the output of the inverter for negative feedback as the sense amplifier output.

In the semiconductor device according to claim 3, in the semiconductor device according to claim 1, since the inverted signal is amplified,
The difference in the reaching potential of the bit line when the memory cell is turned on and when the memory cell is turned off at the end of precharge is further amplified.

As a result, it is possible to obtain a high-speed sense amplifier in which the sense operation is further facilitated by using, as the sense amplifier output, the one obtained by amplifying the output of the inverter which applies the negative feedback.

According to a fourth aspect of the present invention, in the third aspect, the semiconductor devices form a pair, one of the pair is connected to a memory cell, and the other of the pair is connected to a dummy cell.
Since the difference between the outputs of the semiconductors connected to each of the pair of semiconductors is amplified, the difference between the reaching potentials of the bit lines when the memory cell is on and when the precharge is completed is further amplified. Also, the effects of parameter variations are offset.

As a result, it is possible to obtain a high-speed sense amplifier in which the sense operation is further facilitated and the parameter variation is small, by using the amplified output of the inverter for negative feedback as the sense amplifier output.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device used for a sense amplifier of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the semiconductor device used in the sense amplifier of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the semiconductor device used in the sense amplifier of the present invention.

4 is a circuit diagram in which, in the semiconductor device used in the sense amplifier of FIG. 3 of the present invention, the semiconductor devices 1 and 1'are replaced with the same two semiconductor devices 2 and 2'as the semiconductor device of the second embodiment. .

FIG. 5 is a circuit diagram showing a fourth embodiment of the semiconductor device used in the sense amplifier of the present invention.

6 is a circuit diagram in which, in the semiconductor device used in the sense amplifier of FIG. 5 of the present invention, the semiconductor devices 1 and 1'are replaced with the same two semiconductor devices 2 and 2'as the semiconductor device of the second embodiment. .

FIG. 7 is a circuit diagram of a semiconductor device used for a conventional and generally known sense amplifier.

[Explanation of symbols]

Semiconductor devices used as 1,1 ', 2,2' sense amplifiers, M1, M2, M3, M11, M21, M3
1, M41, M43 N-type field effect transistor, M4
5, M47 P-type field effect transistor, R1, R3
R11, R31 resistance element, OPA differential amplifier circuit, C
Circuits using current mirror load, INV1, INV
1 ', INV2, INV2' inverter.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location G11C 17/00 520 A (72) Inventor Yasuhiko Toto, 4-chome, Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Company ULS Development Research Center

Claims (4)

[Claims] 1. A semiconductor device for detecting the potential of a memory cell connected to a bit line from the potential of the bit line, the applying device applying a precharge potential of a predetermined memory cell to the bit line, A semiconductor including an output unit for inputting a detection signal corresponding to the applied potential and outputting an inverted signal thereof as an output of the semiconductor device, and a control unit for controlling the precharge potential of the memory cell by the inverted signal. apparatus. 2. The semiconductor device according to claim 1, wherein the applying unit further includes a supplying unit that continuously supplies the precharge potential of the predetermined memory cell. 3. The semiconductor device according to claim 1, further comprising means for amplifying the inverted signal. 4. The semiconductor devices form a pair, one of the pair is connected to the memory cell, the other of the pair is connected to a dummy cell, and each of the semiconductor devices of the pair is connected to each of the output terminals. The semiconductor device according to claim 3, further comprising a differential amplifying unit that amplifies the difference.