JPH0895945A - Microprocessor with built-in trace memory and trace method - Google Patents

Abstract

PURPOSE: To provide a microprocessor with built-in trace memory and a trace method by which instruction trace can be realized without impairing real-time processing by reducing the memory capacity of a circuit for instruction trace inside the microprocessor. CONSTITUTION: This microprocessor 101 for performing pipeline processing is incorporated with a cache memory 803 and provided with an incorporated register 811, an execution resources 812, an interruption receiving means 809, an instruction counter 802, an instruction decode means 810, an external input/ output means 804 and a trace memory 126. The microprocessor is provided with a first securing means 128, a second securing means 808, a first selecting means 117 and an external output means 127, and the trace memory 126 stores an output 118 of the first selecting means 117. Besides, the microprocessor is provided with a second selecting means 109, and the output 822 of the second selecting means 109 is connected to the write terminal of the incorporated register 811.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a trace memory built-in microprocessor and a tracing method that include a cache memory and perform pipeline processing.

[0002]

2. Description of the Related Art As an effective debugging means when a failure occurs in a board system, there is an instruction trace for investigating the order in which a microprocessor executes a program on a board to determine the cause of the failure. .

FIG. 6 is a diagram showing a structure of a microprocessor for realizing a conventional instruction trace. A conventional microprocessor will be described with reference to FIG. A microprocessor 801 is mounted on the board system 912, and the microprocessor 801 has an address terminal 815, a data terminal 816, an instruction fetch terminal 817, and an interrupt input terminal 820 as means for connecting to the outside. Further, the address terminal 815 and the data terminal 8
16 includes an address bus 90 on the board system 912.
1 and the data bus 902 are connected.

In order to realize the instruction trace of the microprocessor 801, an in-circuit emulator (hereinafter referred to as ICE) 906 is provided in the board system 912.
An external circuit called is connected. Actually, the address bus 901 and the data bus 9 on the board system 912
02 and the instruction fetch terminal 817 to the address bus connecting means 909, the data bus connecting means 908,
And the instruction fetch signal connection means 910 is connected.

[0005] The interrupt signal input from the interrupt input terminal 820 is input to the interrupt receiving means 809,
The interrupt branch address output from the interrupt accepting unit 809 is input to the next instruction address register 818 via the interrupt branch address bus 821.

The output of the next instruction address register 818 is the address incrementer 802 and the cache memory 80.
3, and input to the instruction address register 805.
The output of the address incrementer 802 is input to the next instruction address register 818 again.

The output of the next instruction address register 818 outputs the instruction address register 805 at the same time as performing the instruction fetch.
The output of the instruction address register 805 is input to the instruction address register 806, the output of the instruction address register 806 is input to the instruction address register 807, and the output of the instruction address register 807 is input to and stored in the instruction address register 808. To be done.

The output of the next instruction address register 818 is input to the cache memory 803, and the cache memory 803 is connected to the external input / output unit 804. The external input / output unit 804 is connected to the external address terminal 815, the external data terminal 816, and the instruction fetch terminal 817. The instruction output from the cache memory 803 is input to the instruction decoder 810 via the instruction bus 819.

The output of the instruction decoder 810 is input to a built-in register 811 and an execution resource 812, and the output of the built-in register 811 is input to an execution resource 812.

The execution resource 812 includes a logical arithmetic unit, a numerical arithmetic unit, an effective address generator, etc., and the instruction decoder 8
It operates by the signal output from 10. Execution resource 8
The memory access address output from 12 is input to the result register 813 and the next instruction address register 818, and is also input to the external input / output means 804 via the memory access address bus 823. Result register 81
3 is input to the result register 814, and the memory access data bus 82
4 to the external input / output means 804. The output of the result register 814 is written back to the internal register 811 at an appropriate timing via the result write bus 822.

A procedure in which the microprocessor 801 mounted on the board system 912 executes an instruction will be described. First, the address in which the instruction to be executed is stored is output from the address terminal 815 to the address bus 901 via the external input / output unit 804, and at the same time, the instruction fetch signal is activated and output to the instruction fetch terminal 817. To do. After that, an instruction corresponding to the address output from the address terminal 815 is issued to the data bus 90.
The data is input from the data terminal 816 via 2 and stored in the instruction decoder 810 via the internal input / output unit 804 and the cache memory 803 and the internal instruction bus 819. Then, a signal output from the instruction decoder 810 is input to the built-in register 811 and the execution resource 812, and the content of the built-in register 811 is read from the read port and input to the execution resource 812. In this way, the signal read from the instruction decoder 810 is input to the execution resource 812 via the internal register 811.

After or simultaneously with the execution resource 812 operating according to the signal output from the instruction decoder 810, the next instruction address calculated by the address incrementer 802 is stored in the next instruction address register 818.
And the output of the next instruction address register 818 is stored in the external input / output unit 804 via the cache memory 803.
Entered in. The external input / output means 804 has the address terminal 8
The instruction fetch signal is activated at the same time as outputting the next instruction address from No. 15 and output to the instruction fetch terminal 817.

The operation when the branch instruction is executed will be described. When the instruction decoder 810 determines that the branch instruction is a branch instruction, the branch destination address calculated by the execution resource 812 is stored in the next instruction address register 818 via the memory access address bus 823, and external input / output via the cache memory 803. It is output from the means 804 to the address terminal 815.

The operation at the time of executing an interrupt will be described. The interrupt signal input from the external interrupt input terminal 820 is input to the interrupt receiving unit 809, and determines the type of interrupt and whether the interrupt is an acceptable interrupt.
If the interrupt can be accepted, an interrupt entry address corresponding to the type of the interrupt is stored in the interrupt branch address bus 821 and the memory access address bus 82.
3 to the next instruction address register 818,
The data is output from the external input / output unit 804 to the address terminal 815 via the next instruction address register 818 and the cache memory 803.

When instruction tracing is started, ICE 906
The ICE fetching means 903 incorporated in the CPU fetches the content of the address bus 901 when the instruction fetch signal output from the instruction fetch terminal 817 is active via the address bus connecting means 909 and stores it in the ICE trace memory 904. To do.

When referring to the trace result 907,
The contents of the ICE trace memory 904 are referred to by the supervisor microprocessor 905 incorporated in the ICE 906, and the trace result 9 is output via the output means 911.
I get 07.

Also, for example, after executing a certain instruction, 100
When searching for an instruction executed after the clock,
The supervisor microprocessor 905 executes while referring to the contents of the ICE trace memory 904.

[0018]

When an external circuit is added to the terminal of the conventional microprocessor 801, the following two methods are required.
There are two problems.

(1) Values output from the data terminal 8116, the address terminal 815, and the instruction fetch terminal 817 of the microprocessor 801 by using the data bus connecting means 908, the address bus connecting means 909, and the instruction fetch signal connecting means 910. Are taken in by the ICE 906, the electrical characteristics of those terminals deteriorate. Therefore, there is a problem that even the board system 912 that operates normally without the ICE 906 added does not operate normally by connecting the ICE 906 through these connecting means.

The problem (1) will be described. As the operating speed of the microprocessor 801 has increased in recent years, the operating frequency of the board system 912 in which the microprocessor 801 is mounted has also improved. For this reason, board systems in recent years are often designed without any margin in order to realize a high operation speed.

The ICE 906 is a microprocessor 801
Are connected to the respective output terminals using connection means. Therefore, each output terminal of the microprocessor 801 must transmit signals to the data bus connecting unit 908, the address bus connecting unit 909, and the instruction fetch signal connecting unit 910 in addition to the various resources installed on the board. . Therefore, compared to the case where the ICE 906 is not connected, there is no room for the electrical characteristics on the board when the ICE 906 is connected.

In the prior art, the difference in electrical characteristics between when the ICE 906 was connected and when it was not connected was very small compared to the operating frequency of the board system, so no problem occurred. There wasn't. However, as the operating frequency of the board system 912 itself has improved in recent years,
Due to this slight difference in the electrical characteristics, the board system 912 operates in a state where the microprocessor 801 is directly mounted, but the operation becomes unstable only when the ICE 906 intervenes between the microprocessor 801 and the board system 912. There are many cases where In addition to unstable operation, it often causes defective operation.

(2) In the case of the microprocessor 801 incorporating the cache memory 803, the branch to the address stored in the cache memory 803 does not drive the external address signal. There is a problem that it is difficult to guess.

The problem (2) will be described. The microprocessor 801 in recent years has a built-in cache memory 803 and performs pipeline processing in order to realize high-speed processing. In the normal ICE 906, the instruction fetch address output from the instruction fetch terminal 817 of the microprocessor 801 stores the instruction fetch address in the ICE trace memory 904 inside the ICE 906, and the supervisor microprocessor 905 inside the ICE 906 stores the contents of the ICE trace memory 904. The type of the instruction fetched by the microprocessor 801 is determined while referring to the instruction execution trace.

First, the problems of the microprocessor 801 which performs pipeline processing will be described. In the case of the microprocessor 801 that performs pipeline processing, the instruction request address differs from the address of the instruction that is actually being executed. Therefore, when a branch instruction or the like that changes the instruction order is requested, the instruction that has been fetched by the microprocessor 801 until the execution of the branch instruction is taken into the microprocessor 801. Not executed. In the conventional microprocessor, the progress of instruction fetch for such an unexecuted instruction is
It is stored in the trace memory 904. For this reason,
Supervisor microprocessor 9 inside ICE906
In 05, a trace is realized by performing processing such as omitting an unexecuted instruction. However, the type of branch instruction and the microprocessor 80 when executing the branch instruction
Accurate tracing has been difficult because the number of instructions to be omitted may vary depending on the state of 1.

Next, a problem in tracing an instruction executed by the microprocessor 801 incorporating the cache memory 803 will be described. The microprocessor with a cache memory operates as follows when fetching an instruction. When the output of the next instruction address register 818 is input to the cache memory 803 and there is a mishit in the cache memory 803 (the content of the required address is not inside the cache memory 803), the cache memory 803 outputs to the external input / output unit 804. On the other hand, the next instruction address is transmitted, and the external input / output unit 804 starts access to the outside. On the other hand, the cache memory 80
3 is hit (the content of the required address is stored in the cache memory 803), the instruction is fetched from the cache memory 803 and the external input / output unit 804 is not operated.

When a hit occurs in the cache memory 803, the external input / output means 804 does not output an instruction address and does not activate an instruction fetch signal. Therefore, the address of the instruction to be executed is not output to the address bus 901, and the trace data cannot be captured in the ICE trace memory 904.
There is no way to analyze how instructions are being executed. Therefore, accurate instruction tracing cannot be realized.

For these reasons, conventionally, when tracing is performed, use of the cache memory 803 is prohibited, and an interrupt is input to the microprocessor 801 each time one instruction is processed, thereby substantially preventing the pipeline operation. Had been tracing. When tracing is performed by this method, the processing speed is at least 10 times slower than the processing speed at the time of actual application operation.
Therefore, in a field requiring real-time processing such as built-in control, it has become an important issue to realize the trace while realizing the actual operation speed.

As a method for solving the above problem,
The invention of the microprocessor described in Japanese Unexamined Patent Publication No. 4-44125 (hereinafter, referred to as the invention of Japanese Patent Laid-Open No. 4-12525) and the actual invention
There is a device of a microprocessor described in Japanese Patent Publication No.-40339 (hereinafter, referred to as a device of Publication 2).

[0030] The invention of Publication 1 is to output a branch destination address and a branch source address to external terminals when a microprocessor executes an instruction such as a branch instruction. When a branch instruction or the like for changing the instruction order is requested in this way, the branch destination address is output to the outside by a method other than the instruction fetch or the like, so that the occurrence of the branch in the ICE connected to the outside of the microprocessor is detected. The address of the branch destination can be communicated. However, instruction trace cannot be realized without connecting ICE to the outside,
Due to the problem (1), instruction tracing on a high-speed board cannot be realized. Also, it is difficult to trace an instruction of a microprocessor having a built-in cache memory.

The device disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2 has a small-scale trace memory inside the microprocessor to store a sequence of instructions to be executed by the microprocessor. When a trace is executed, the contents of the trace memory are stored outside the microprocessor. Instruction tracing is realized by means such as outputting to a memory. However, this method has the following problems.

(A) Since a large-capacity trace memory cannot be built in the microprocessor, it is impossible to trace instructions for a long time.

(B) Instruction tracing of instructions for changing the execution order of the microprocessor other than branch instructions cannot be performed.

(C) Since the contents of the trace memory cannot be taken out without passing through an external data bus, the result of the instruction trace must be stored in a memory or the like on the board, and the normal operation of the board or the like is verified. Despite the instruction trace, the operation of the memory on the board needs to be guaranteed. When the memory on the board is not used, it is necessary to separately connect a memory for tracing to the data bus and the address bus on the board, and the electrical characteristics of the data bus and address bus of the microprocessor deteriorate.

In order to solve the problem (A), there is also a method of saving only the branch destination address and the branch source address in the trace memory when the branch instruction is executed. Using this method, a small amount of trace memory can achieve the same effect as many trace memories. However, since two types of addresses are stored for one branch instruction, there is a disadvantage in that a trace memory for two words is used.

In order to overcome this drawback, a method is conceivable in which only one word of trace memory is used for one branch instruction. In this method, two methods are conceivable: a method of saving only the branch destination address of the branch instruction in the trace memory and a method of saving only the branch source address of the branch instruction in the trace memory. However, if only the branch instruction is supported, an instruction trace of only the branch destination address is sufficient, but the branch is not limited to when the branch instruction is executed.
It also occurs when an interrupt or an exception during instruction execution is executed. In this case, the instruction executed until immediately before the interruption is important.

Therefore, in order to execute the instruction trace without losing information even in the case of a branch due to an interrupt or an exception during instruction execution, the address of the branch source is stored in the trace memory regardless of the branch instruction or the interrupt. Is good. However, when changing the instruction execution address of the microprocessor other than the branch instruction, for example, when executing an interrupt operation (operation of canceling the operation of the instruction at the time of interruption and transferring control to the start address of the interrupt processing) In the trace of the branch instruction, the address of the branch instruction (that is, execution completion and branching) is stored in the trace of the branch instruction. Is stored in the trace memory. As a result, the instruction at the time when the interrupt is input is stored in the trace memory although it is not actually executed. That is, it is not always the case that all the addresses stored in the trace memory have been executed. In addition, depending on the type of instruction, an instruction that performs a branch operation without completing the execution of the instruction is also required depending on the application. Also in this case, not all the addresses stored in the trace memory have been completely executed, which causes confusion.

In view of such a point, the present invention has a trace memory built-in micro-processor capable of realizing an instruction trace without deteriorating the real-time processing by reducing the memory capacity of the instruction trace circuit in the microprocessor. It is an object to provide a processor and a tracing method.

[0039]

In order to solve the above-mentioned problems, a microprocessor with a built-in trace memory according to the present invention comprises:
It has a built-in register, an execution resource, an interrupt accepting means, an instruction counter for calculating an address of a next instruction, an instruction decoding means, an external input / output means, and a trace memory. A first securing unit for securing the value of the program counter of the instruction that has just been executed, and a second securing unit for securing the value of the program counter of the currently executed instruction. A first selecting means for selecting one of the outputs of the first and second securing means, and an external output means for outputting the contents of the built-in register. The output of the first selecting means is stored.

The microprocessor with a built-in trace memory according to the present invention has a second selecting means for selecting one of a trace result output from the trace memory and an output of the execution resource. An output of the second selecting means is connected to a write terminal of the built-in register.

The tracing method of the present invention using the microprocessor with trace memory of the present invention is the first method described above.
Selecting means for selecting and outputting the value secured by the first securing means when the execution sequence of the program is changed by an interrupt request signal output from the interrupt accepting means, and changing the execution order of the program When the execution sequence of the program changes due to the instruction
The value secured by the securing means of is selected and output.

The tracing method of the present invention using the microprocessor with a trace memory of the present invention is the first method described above.
Selecting means for selecting and outputting a value secured by the second securing means when the execution sequence of the program is changed by a specific interrupt detection signal output from the interrupt receiving means, and executing the program When the execution sequence of the program is changed by the instruction for changing the order, the value secured by the first securing means is selected and output according to the specific instruction detection signal output from the instruction decoding means.

Further, in the tracing method of the present invention, when the second selecting means detects the read instruction by the trace memory read instruction detecting means, the trace result can be selected and output.

Further, in the above tracing method of the present invention, the external output means can output the contents of the internal register to the outside.

[0045]

With the above construction, the present invention has the following actions.

(1) When writing the trace result in the trace memory, the first selecting means secures the first securing means when the execution sequence of the program is changed by the interrupt request signal output from the interrupt accepting means. Since the selected value is selected and output, the address of the instruction whose execution has been completed by the time the interrupt is accepted can be stored in the trace memory. When the execution sequence of the program is changed by an instruction to change the execution order of the program, the first selection means selects and outputs the value secured by the second securing means. The address of the instruction to be changed can be stored in the trace memory.

(2) When writing the trace result in the trace memory, the first selecting means sets the second securing means when the execution sequence of the program is changed by a specific interrupt detection signal output from the interrupt receiving means. Since the reserved value is selected and output, the address of the interrupt itself can be stored in the trace memory. Further, the first selecting means selects and outputs the value secured by the first securing means when the execution sequence of the program is changed by an instruction for changing the execution sequence of the program, and therefore the execution order of the programs is changed. The address of the instruction that has been executed by the time the instruction to be changed is accepted can be stored in the trace memory.

(3) When reading the trace information stored in the trace memory, the second selecting means selects the trace information when the read instruction is detected by the trace memory read instruction detecting means. It can be stored in a built-in register.

(4) Since the external output means outputs the contents of the internal register to the outside, the trace result can be output without deteriorating the electrical characteristics of the external input / output means.

[0050]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First and second embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention. First, the configuration of the first embodiment of the present invention will be described with reference to FIG. In the configuration of FIG. 1, the same parts as those of the configuration of FIG.
Only different parts will be described.

The microprocessor 101 has an external output means 127 as an output means for outputting the trace result to the outside. The interrupt type signal and the interrupt acceptance signal output from the interrupt acceptance unit 809 are the interrupt type signal line 105 and the interrupt acceptance signal line 10.
It is input to the end determination means 112 via 6. Further, the interrupt type signal line 105 is connected to the trace address determining means 1.
11 and trace detection means 113. The branch instruction type signal and the instruction type signal output from the instruction decoder 810 are input to the trace detection unit 113 and the trace address determination unit 111 via the branch instruction type signal line 103 and the instruction type signal line 104, and the instruction execution signal is It is input to the end determination means 112 via the instruction execution signal line 107. The end instruction address write signal output from the end determination means 112 is input to the execution end instruction address register 128 via the end instruction address write signal line 110.

An interrupt type signal line 105 output from the interrupt accepting unit 809 and an instruction type signal line 104 output from the instruction decoder 810 are input to the trace address determining unit 111 and output from the trace address determining unit 111. The trace address selection signal is input to the selection signal input terminal of the trace address selection means 117 via the trace address selection signal line 116.

The output of the instruction address register 808 is input to one selected signal input terminal of the trace address selection means 117 and the execution end instruction address register 128, and the output of the execution end instruction address register 128 is output from the trace address selection means 117. It is input to the other selected signal input terminal. The output of the trace address selecting means 117 is input to the write port of the trace memory 126 via the trace address bus 118.

The output of the result register 813 is input to one of the selected signal input terminals of the trace memory address selecting means 115, and furthermore, the memory access data bus 8
24 and the external output means 127 via the connection means 125
It is connected to the.

The trace memory write signal line 120 output from the trace detecting means 113 is connected to the trace memory 1
26, the trace memory address hold selection signal and the trace memory address increment selection signal are supplied to the trace memory address selection means 115 via the trace memory address increment selection signal line 122 and the trace memory address hold selection signal line 123. Input to two of the terminals.
The output of the trace memory address selecting means 115 is input to the trace memory address register 114, and the output of the trace memory address register 114 is one of the selected signal input terminals of the trace memory address selecting means 115, the trace memory address incrementer 121 ,
And to the trace memory 126. The output of the trace memory address incrementer 121 is input to one of the selected signal input terminals of the trace memory address selecting means 115.

The instruction output from the cache memory 803 is also input to the trace memory read detection means 102 via the instruction bus 819.

The register write selection signal line 108 output from the trace memory read detection means 102 is input to the selection signal input terminal of the register write signal selection means 109, and the trace memory address set selection signal line 1
24 is input to one of the selection signal input terminals of the trace memory address selection means 115, and the trace memory read signal line 129 is input to the trace memory 126.

A trace memory write signal line 120 output from the trace detection means 113 and a trace memory read signal line 129 output from the trace memory read detection means 102 are input to the trace memory 126. The output of the read port of the trace memory 126 is input to one selected signal input terminal of the register write signal selection means 109 via the trace memory read bus 119. The output of the result register 814 is input to the other selected signal input terminal of the register write signal selection means 109. Register write signal selection means 10
The output of 9 is input to the write port of the internal register 811 via the result write bus 822 of the internal register.

Table 1 is a diagram showing the operation logic of the end determination means of FIG. The relationship between the type of instruction and the value of the end instruction address write signal line 110 in the end determination means 112 when the trace data is stored in the trace memory 126 in the microprocessor 101 of FIG. 1 will be described using Table 1.

[0061]

[Table 1] In the microprocessor 101 of FIG. 1, the instruction execution address is changed by a branch instruction, an undefined instruction, a trap instruction, a trap instruction before execution, an interrupt, an address trap, an exception during instruction execution, and an interrupt after execution.

The branch instruction branches to the address indicated by the branch instruction, and the instruction ends normally. The undefined instruction branches to the undefined instruction exception entry address, and the instruction ends normally.
The trap instruction branches to the trap instruction exception entry address, and the instruction ends normally. The pre-execution trap instruction branches to the trap instruction exception entry address, and the instruction is canceled and does not end. The interrupt branches to the interrupt branch address, and the instruction being executed when the interrupt occurs is canceled and does not end. The address trap occurs when the microprocessor 101 accesses an address preset for the address trap,
Address trap entry The instruction branching to the address and executing the memory access is canceled and does not end. The exception during instruction execution occurs when, for example, division by zero is executed. The instruction branches to the exception entry address set for each exception during instruction execution, and the instruction is canceled. The post-execution interrupt branches to the post-execution interrupt entry address, and the instruction being executed when the interrupt occurred ends normally. As for this interrupt, if an interrupt is always inserted, an interrupt is generated for each instruction and a single instruction is executed.

Table 2 is a diagram showing the operation logic of the trace address determining means of FIG. The relationship between the type of instruction and the value of the trace address selection signal line 116 in the trace address determining means 111 of FIG. 1 will be described using Table 2.

[0064]

[Table 2] In the microprocessor of FIG. 1, the instruction execution address is changed by a branch instruction, an undefined instruction, a trap instruction, a pre-execution trap instruction, an interrupt, an address trap, an instruction execution exception, and a post-execution interrupt.

In the microprocessor 101 of FIG. 1, the execution address of an instruction is changed by a branch instruction, an undefined instruction, a trap instruction, a pre-execution trap instruction, an interrupt, an address trap, an instruction execution exception, and a post-execution interrupt.

The branch instruction branches to the address indicated by the branch instruction, and the trace address is the address of the instruction currently being executed. The undefined instruction branches to the undefined instruction exception entry address, and the trace address is the instruction address currently being executed. The trap instruction branches to the trap instruction exception entry address, and the trace address is the instruction address currently being executed. The pre-execution trap instruction branches to the trap instruction exception entry address, and the trace address is the instruction address executed immediately before. The interrupt branches to the interrupt branch address, and the trace address is the instruction address executed immediately before. The address trap branches to the address trap entry address, and the trace address is the instruction address executed immediately before. The instruction executing exception branches to the exception entry address set for each instruction executing exception, and the trace address is the instruction address executed immediately before. The post-execution interrupt branches to the post-execution interrupt entry address, and the trace address is the currently executed instruction address.

Next, the operation of the first embodiment of the present invention will be described with reference to FIGS.

(1) The operation logic for executing a branch instruction will be described. In the microprocessor 101 shown in FIG. 1, when the execution of the instruction is completed, the termination determining unit 112 determines whether or not the instruction is normally terminated, and the instruction address of the instruction that is normally terminated is the execution termination instruction address register 128.
Stored in.

The end judging means 112 is the instruction decoder 81.
The instruction execution signal line 107 output from 0 and the interrupt reception signal line 106 output from the interrupt reception unit 809 are input, and it is determined whether or not the instruction that has received the instruction execution has ended normally. If the interrupt acceptance signal line 106 becomes active before the instruction receiving the instruction execution start is completed, it is determined that the interrupt acceptance signal line 106 is not normally completed, and the end instruction address write signal line 110 is not activated. If the interrupt acceptance signal line 106 has not been activated until the instruction which has received the instruction execution is completed, it is determined that the operation has been completed normally, and the end instruction address write signal line 110 is activated. The result of the judgment by the end judging means 112 is transmitted to the execution end instruction address register 128 by the end instruction address write signal line 110.
Be transmitted to.

However, the exception operation is performed only in the case of the pre-execution trap instruction. The pre-execution trap instruction is usually used to temporarily change the execution of the program. A typical usage of the pre-execution trap instruction is shown below.

The pre-execution trap instruction is set in the instruction stream instead of the original instruction, and up to the previous instruction is set in the CPU
(Microprocessor) to execute, and the execution of the CPU (microprocessor) is temporarily stopped by the pre-execution trap instruction. When the pre-execution trap instruction is executed, C
A PU (microprocessor) activates a trap handler program stored at a trap handler address to perform a trap process. In this trap handler program, after executing a predetermined process, the pre-execution trap instruction in the instruction stream is returned to the original instruction instead of the original instruction, and the execution of the program is resumed from the returned instruction. This predetermined process differs depending on the application. Table 3 shows the above operation when paying attention to the flow of the instruction stream.

[0072]

[Table 3] Here, XXXX, YYYY, and the like are instructions that can be interpreted by a CPU (microprocessor), and the number preceding each instruction is a memory address where the instruction is stored. The trap handler address is 100, which indicates that execution of the pre-execution trap instruction transfers control to address 100. Tracing the original instruction stream, the operations in Table 3 appear to execute the instruction stored at memory address 4 twice. However, since the pre-execution trap instruction executes the original instruction after rewriting the original instruction stream, the instruction stored at the memory address 4 should be executed only once on the original instruction stream, Create confusion.

Therefore, when the pre-execution trap instruction is executed, it is interpreted that the execution of the pre-execution trap instruction is not completed even if it is normally completed, the end instruction address write signal line 110 is made inactive, and the trace address is changed. The trace address selection signal line 116 is activated to return to the instruction executed immediately before. by this,
The pre-execution trap instruction in Table 3 is canceled and the original instruction stream can be traced accurately.

The branch instruction is input from the cache memory 803 to the instruction decoder 810 and the trace memory read detection means 102 via the instruction bus 819. At the same time, the output of the next instruction address register 818 becomes the next instruction address in the address incrementer 802,
It is stored in the next instruction address register 818 again. The output of the next instruction address register 818 is input to the cache memory 803 to fetch the instruction at the branch destination, and is also stored in the instruction address register 805. At this time, the contents of the instruction address register 805 are input to the instruction address
06 is input to the instruction address register 807,
The contents of the instruction address register 807 are input to and stored in the instruction address register 808. After the branch instruction is determined by the instruction decoder 810 to be a branch instruction, the execution resources 81
2 to generate a branch destination address, and the branch destination address is input to and held in the next instruction address register 818.

In the next cycle, the branch destination address stored in the next instruction address register 818 is input to the cache memory 803, and the instruction next to the branch instruction is fetched. At the same time, the type of the branch instruction detected by the instruction decoder 810 is transmitted to the trace detection unit 11 via the branch instruction type signal line 103 and the instruction type signal line 104.
3 and the trace address determining means 111. The trace detection unit 113 determines whether the microprocessor 101 is in a state in which instruction tracing can be performed, and the traceable state and the instruction transmitted by the branch instruction type signal line 103 is registered in the trace memory. If so, the trace memory address hold selection signal line 123 is made inactive and the trace memory address increment selection signal line 122 is made active at an appropriate timing.

In the next cycle, the trace detection means 113 activates the trace memory write signal line 120. When the trace memory address increment selection signal line 122 is active and the trace memory address hold selection signal line 123 is inactive, the trace memory address selection means 115 selects the output of the trace memory address incrementer 121 and The data is stored in the memory address register 114. The output of the trace memory address register 114 becomes the memory address of the trace memory 126, and when the trace memory write signal line 120 is active, the trace address bus 1 is sent to the trace memory 126.
Write the value of 18. When the address of the trace memory address incrementer 121 exceeds the capacity of the trace memory, the address is configured to return to the first address in the wraparound, and does not exceed the capacity of the trace memory.

If the instruction does not cause a branch, the trace detecting means 113 activates the trace memory address hold selection signal line 123 and inactivates the trace memory address increment selection signal line 122. At this time, the trace memory address selecting means 115 selects the output signal of the trace memory address register 114, and the trace memory address register 1
Restore in 14.

The trace address determination means 111 outputs the trace address selection signal line 116 to the trace address selection means 117 at an appropriate timing in accordance with the type of instruction transmitted from the instruction decoder 810 via the instruction type signal line 104. Trace address selection signal line 1
16 is active, the trace address selecting means 117 executes the execution end instruction address register 128
The address output from is selected and output to the trace address bus 118. Trace address selection signal line 11
When 6 is inactive, the trace address selecting means 117 selects the address output from the register 808 and outputs it to the trace address bus 118.

FIG. 2 is a timing chart showing an operation at the time of execution of a branch instruction. When the instruction address of the branch instruction is stored in the instruction address register 808, the end determination means 1
12 activates the end instruction address write signal line 110 and sends it to the execution end instruction address register 128, and the execution end instruction address register 128 stores the contents of the instruction address register 808.

In FIG. 2, the instruction (jmp0020) is an instruction for setting the instruction address to 0020, and the instruction address is changed at the stage of the instruction address register 806 (). Similarly, the instruction (jmp0040) sets the instruction address to 0040 and changes the instruction address at the stage of the instruction address register 806 (). The shaded instruction in FIG. 2 is a canceled instruction, and the output of the instruction address register 808 ()
Among them, the addresses not shaded are the flow of the instruction stream. The output of this instruction address register 808 is
Data is written in the trace memory 126 via the trace address bus 118 via the trace address selection means 117 at the timing when each trace memory embedded signal line 120 is active.

In FIG. 2, address 0002 is written to trace memory 126 for the first jump instruction, and address 0020 is written to trace memory 126 for the next jump instruction.

(2) The operation logic when instruction execution becomes discontinuous due to an interrupt will be described. The interrupt signal is input from the interrupt input terminal 820 of the microprocessor 101 and input to the interrupt accepting unit 809.
The result of the reception by the interrupt receiving unit 809 is transmitted to the end determining unit 112 via the interrupt receiving signal line 106. The end determination means 112 receives the interrupt acceptance result, inactivates the end instruction address write signal line 110 for the currently executed instruction,
Writing of an instruction address to the execution end instruction address register 128 is prohibited.

However, an exception operation is performed only at the time of an interrupt after execution. The post-execution interrupt is an interrupt used when step execution is executed for each instruction. The normal interrupt cancels the instruction that accepted the interrupt, transfers control to the interrupt handler address, performs predetermined processing at the interrupt handler address, and then returns to the canceled instruction. Table 4 shows the operation when the normal interrupt is continuously executed for the CPU (microprocessor).

[0084]

[Table 4] Here, XXXX, YYYY, and the like are instructions that can be interpreted by a CPU (microprocessor), the number preceding each instruction is a memory address where the instruction is stored, and → is an interrupt signal. As can be seen from Table 4, when the normal interrupt is executed, the instruction sequence does not proceed because the instruction at the address 101 of the interrupt handler program returns to the instruction that accepted the interrupt. Table 5 shows the operation when the interrupt signal shown in Table 4 is set as an interrupt after execution.

[0085]

[Table 5] Here, the interrupt signal → is a post-execution interrupt signal.
In the post-execution interrupt, the instruction that accepted the interrupt is interpreted as having ended normally, the write end instruction address write signal line 110 is activated, and the trace address selection signal line 116 is used to specify the current instruction address as the trace address. By making it inactive, an interrupt after execution is realized, and execution for each instruction becomes possible.

The instruction being executed when the interrupt is accepted is sent from the cache memory 803 to the instruction bus 81 as usual.
9 to the instruction decoder 810 and the trace memory read detection means 102. At the same time, the output of the next instruction address register 818 becomes the next instruction address in the address incrementer 802 and is stored again in the next instruction address register 818. The output of the next instruction address register 818 is stored in the cache memory 803 to fetch the branch destination instruction, and at the same time, is also stored in the instruction address register 805. At this time, the contents of the instruction address register 805 are
6, the contents of the instruction address register 806 are input to the instruction address register 807, and the contents of the instruction address register 807 are input to and stored in the instruction address register 808.

In the next cycle, the address stored in the next instruction address register 818 is stored in the cache memory 80.
3 and fetches the instruction following the interrupt. The interrupt type signal output by the interrupt receiving unit 809 is input to the trace detection unit 113 via the interrupt type signal line 105. In the trace detecting means 113,
The microprocessor 101 determines whether or not the instruction tracing can be performed. If the tracing is enabled and the interrupt transmitted by the branch instruction type signal line 103 is an interrupt to be registered in the trace memory,
At an appropriate timing, the trace memory address hold selection signal line 123 is made inactive, and the trace memory address increment selection signal line 122 is made active.

In the next cycle, the trace detecting means 113 activates the trace memory write signal line 120. When the trace memory address increment selection signal line 122 is active and the trace memory address hold selection signal line 123 is inactive, the trace memory address selection means 115 selects the output of the trace memory address incrementer 121 and The data is stored in the memory address register 114. The output of the trace memory address register 114 becomes the memory address of the trace memory 126, and when the trace memory write signal line 120 is active, the trace address bus 1 is sent to the trace memory 126.
Write the value of 18.

In the trace address determination means 111, the trace address selection signal line 116 is set at an appropriate timing according to the type of the interrupt transmitted by the interrupt type signal line 105 output from the interrupt reception means 809. Output to.
When the trace address selection signal line 116 is active, the trace address selection means 117 selects the address output from the execution end instruction address register 128 and outputs it to the trace address bus 118. If the trace address selection signal line 116 is inactive, the trace address selection means 117 selects the address output from the register 808 and outputs it to the trace address bus 118.

FIG. 3 is a timing chart showing an operation at the time of executing an interrupt. When the instruction address of the instruction that was being executed when the interrupt was finally accepted is stored in the instruction address register 808, the end determination unit 112 activates the end instruction address write signal line 110 and the execution end instruction address register 128. The execution end instruction address register 128 stores the contents of the instruction address register 808.

In FIG. 3, an instruction (jmp1000) is an instruction for setting the instruction address to 1000, and the instruction address is changed at the stage of the instruction address register 806 (). The instruction (normal) has an instruction address corresponding to 1000, and starts executing after the instruction sets the instruction address to 1000, but the instruction is canceled because an interrupt is input. The shaded instructions in FIG. 3 are canceled instructions, and the non-shaded addresses of the output of the instruction address register 808 are the flow of the instruction stream. Here, the instruction has been canceled by the interrupt, and the instruction address is set to 2000, which is the interrupt handler address, at the stage of the instruction address register 806 without performing the operation originally performed by the instruction ().

In FIG. 3, address 0002 of the instruction which is a jump instruction is written in trace memory 126, and address 0002 is stored in trace memory 1 by an interrupt input during execution of the instruction.
26.

(3) The operation for reading the contents of the trace memory will be described. FIG. 4 is a timing chart showing the read operation of the trace memory. In the first embodiment, the instruction can read the trace memory 126 inside the microprocessor 101. The trace memory read instruction is sent from the cache memory 803 via the instruction bus 819 to the trace memory read detection unit 1.
It is input to 02. Trace memory read detection means 1
02 detects the trace memory read command and outputs the trace memory address set selection signal line 124 to the trace memory address selection means 115 at an appropriate timing. If the trace memory address set selection signal line 124 is active, the trace memory address selection means 115 selects the output of the result register 813 holding the output of the execution resource 812, and stores the value in the trace memory address register 114. Hold.

In FIG. 4, the instruction (readTM4r
2) is an instruction to read the trace memory, which reads the content of address 4 of the trace memory and stores it in the register indicated by r2. This operation is performed when the instruction is output from the instruction address register 808, and is stored in the register indicated by r2 during this cycle. In this way, by not reading the instruction until it is output from the instruction register 808, the trace result generated by the immediately preceding instruction can be normally written in and read from the trace memory.

In the next cycle, the trace memory read detection means 102 sets the trace memory read signal line 12
At the same time when 9 is activated, the register write selection signal line 108 is activated. Trace memory 12
In response to the activation of the trace memory read signal line 129, the reference numeral 6 reads the trace memory 126 by the address output from the trace memory address register 114, and outputs the read trace result to the trace memory read bus 119. To do. The output of the trace memory read bus 119 passes through the register write signal selecting means 109, and the result write bus 82
2 is written to the built-in register 811.

Since the read result of the trace memory 126 stored in the internal register 811 can be freely processed and processed by the microprocessor 101, it is realized by the supervisor microprocessor 905 in the conventional ICE 906 as shown in FIG. The functions and the like that have been used can be realized by the microprocessor 101 alone. The result of realizing the function of the supervisor microprocessor 905 in the microprocessor 101 is obtained by the connection means 12 in the microprocessor 101.
5 to the external output means 127. By observing the output of the external output means 127, the details of the instruction trace can be known.

[Second Embodiment] FIG. 5 is a diagram showing the configuration of the second embodiment of the present invention, which is an example of a two parallel superscalar for realizing an accurate instruction trace. The second embodiment is applied to the microprocessor 701 which incorporates the cache memory 803 for pipeline processing and adopts the superscalar method.

In the conventional superscalar processor, especially in those supporting out-of-order execution of instructions, instruction tracing has been extremely difficult because the execution order of instructions dynamically changes.

In the configuration of FIG. 5, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.

The microprocessor 701 shown in FIG. 5 has two sets of pipeline configurations and can execute two instructions at the same time. Specifically, in addition to the configuration of the first embodiment shown in FIG.
02 and 703, instruction address registers 707 to 710, an execution end instruction address register 711,
Trace address selection means 712 and end determination means 71
6, a register write enable signal line 715 output from the end determination unit 716 and input to the execution end instruction address register 711, an execution resource 717, and a result register 718. It also has instruction issue means 706 and trace address selection means 713. Trace address selection signal line 714 is output from trace address determination means 111 and input to trace address selection means 713, and trace address selection means The output of 712 and the output of 128 are selected and output. Further, the instruction bus 704 and the instruction decoder 705.
Corresponds to the instruction bus 819 and the instruction decoder 810 of the first embodiment shown in FIG. 1, but has a large bus width and can handle two instructions at a time.

The address generated by the address incrementer 802 is input to the cache memory 803 via the next instruction address register 818. The instruction stored at the corresponding address in the cache memory 803 is sent to the instruction decoder 705 via the instruction bus 704.
Entered in. The instruction bus 704 has a larger bus width than the instruction bus 819 in the first embodiment, and two instructions can be input to the instruction decoder 705 at one time.
At this time, the address in the cache memory corresponding to the instruction input to the instruction decoder 705 is the next instruction address register (fetch pointer queue) 702, 703,
And 818.

The instruction decoder 705 selects two instructions that can be simultaneously executed from the input instructions, and operates the execution resources 717 and 812 independently at the same time according to the selected instructions. In this way, the microprocessor 701 can execute two instructions by one operation. Further, an address in the cache memory corresponding to the instruction processed by the execution resource 717 is stored in the instruction address register 707, and an address in the cache memory corresponding to the instruction processed by the execution resource 812 is stored in the instruction address register 805. To be stored. Further, in the addresses stored in the instruction address registers 707 and 805, the instructions corresponding to them are the microprocessor 70.
1 in the instruction register 708.
And 806, and input to instruction registers 708 and 8
06 is input to instruction registers 709 and 807, and the contents of instruction registers 709 and 807 are stored in instruction register 710 or execution end instruction address register 7.
11, and stored in the instruction register 808 or the execution end instruction address register 128.

At this time, if one of the stored two instructions satisfies the condition stored in the trace memory 126, the same processing as in the first embodiment is performed in the corresponding pipeline. . This processing result is output from the trace address selecting means 712 or 117,
The trace address selection means 713 is switched by the trace address selection signal line 714 output from the trace address determination means 111 to select a pipeline satisfying the conditions stored in the trace memory 126 and output to the trace address bus 118 I do.

If the two stored instructions both satisfy the condition stored in the trace memory 126, the same processing as in the first embodiment is performed in both pipelines. The processing results output from the trace address selecting means 712 and 117 are firstly processed by the trace address selecting means 713 by using the processing result of the pipeline for executing the instruction located earlier on the instruction stream (the instruction to be executed first). Select and store in the trace memory 126. Subsequently, the processing result of the other pipeline is selected by the trace address selecting means 713 and stored in the trace memory 126.

With such a configuration and operation, an accurate instruction trace can be realized in real time even in a superscalar processor having a configuration in which instruction tracing is extremely difficult.

The configuration of the second embodiment is not limited to the instruction trace when two instructions are simultaneously executed in a two-series pipeline, but in a plurality of three-series or more pipelines.
It can also be applied to the instruction trace at the time of simultaneously executing one or more plural instructions.

[0107]

As described above, the present invention has the following effects.

(1) Even if the trace memory built in the microprocessor has a small capacity, it is possible to realize a real-time instruction trace capable of handling an interrupt or the like for a relatively long period.

Specifically, the frequency of the branch instruction is approximately 8 to 1
Since the ratio of 0 instructions is 1 instruction, if a 32 word trace memory is built in, 256 instructions can be converted to 320 instructions.
You can trace instructions. Considering that a conventional 256 word memory must be built in, the capacity of the trace memory can be reduced to 1/8. In addition, the same effect can be obtained with a half trace memory capacity as compared with a method of storing the branch source address and the branch destination address in the trace memory when a branch occurs in the microprocessor.

The area of the trace memory occupies a relatively large area of the entire microprocessor, and the area of the entire microprocessor can be reduced by the present invention. It has the effect of reducing the price.

(2) Further, even in the case of the interrupt operation (the instruction at a certain program counter is canceled and the control is transferred to the start address of the interrupt processing), all the addresses stored in the trace memory have already been executed. Since the address is stored, it is possible to significantly reduce the processing conventionally executed by the supervisor microprocessor.

(3) By reading the contents of the trace memory into a built-in register that can be freely operated by the microprocessor, the microprocessor itself can execute what the supervisor microprocessor had to do conventionally. It has the effect of.

(4) Furthermore, by providing external output means in addition to external input / output means for mounting the board,
This has the effect that the trace result processed by the microprocessor of the present invention can be transmitted to the outside without deterioration of the electrical characteristics of the external input / output terminal for board mounting.

(5) By utilizing these functions, the trace can be realized without connecting the ICE to the external terminal connected to the resource on the board, that is, without changing the electrical characteristics on the board. Since the result can be taken out from the dedicated external terminal without using the resources on the board, there is an effect that the real-time instruction trace can be stably executed even at the board frequency of 50 MHz or more.

(6) Even in a microprocessor adopting the parallel superscaler method, an accurate instruction trace can be realized in real time because each of a plurality of pipelines has the configuration of the present invention. It has the effect of.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a timing chart showing an operation when a branch instruction is executed.

FIG. 3 is a timing chart showing an operation at the time of executing an interrupt.

FIG. 4 is a timing chart showing a read operation of a trace memory.

FIG. 5 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a microprocessor that realizes a conventional instruction trace.

[Explanation of symbols]

101, 701, 801 Microprocessor 102 Trace memory read detection means 103 Branch instruction type signal line 104 Instruction type signal line 105 Interrupt type signal line 106 Interrupt acceptance signal line 107 Instruction execution signal line 108 Register write selection signal line 109 Register write signal selection Means 110 End instruction address write signal line 111 Trace address determination means 112,716 End judgment means 113 Trace detection means 114 Trace memory address register 115 Trace memory address selection means 116,714 Trace address selection signal lines 117, 712, 713 Trace address selection Means 118 Trace address bus 119 Trace memory read bus 120 Trace memory write signal line 121 Trace memory Readdress incrementer 122 Trace memory address increment selection signal line 123 Trace memory address hold selection signal line 124 Trace memory address set selection signal line 125 Connection means 126 Trace memory 127 External output means 128,711 Execution end instruction address register 129 Trace memory read Signal lines 702, 703, 818 Next instruction address registers 704, 819 Instruction buses 705, 810 Instruction decoder 706 Instruction issue means 707, 708, 709, 710, 805, 806, 8
07,808 Instruction address register 715 Register write enable signal line 717,812 Execution resource 718,813,814 Result register 802 Address incrementer 803 Cache memory 804 External input / output means 809 Interrupt acceptance means 811 Internal register 815 Address terminal 816 Data terminal 817 Instruction fetch terminal 820 Interrupt input terminal 821 Interrupt branch address bus 822 Result write bus 823 Memory access address bus 824 Memory access data bus 901 Address bus 902 Data bus 903 ICE (in-circuit emulator) fetching means 904 ICE trace memory 905 Supervisor microprocessor 906 ICE 907 Trace result 908 Data bus connection means 9 9 Address bus connection means 910 instruction fetch signal connection means 911 output unit 912 Board System

Claims (6)

[Claims] 1. An internal register, an execution resource, an interrupt acceptance unit, an instruction counter for calculating the address of the next instruction, an instruction decoding unit, an external input / output unit, a trace memory, and a cache memory. In a microprocessor that performs pipeline processing, a first securing unit that secures a value of a program counter of an instruction that has just been executed, and a second securing unit that secures a value of the program counter of an instruction that is currently being executed. Securing means and one of the outputs of the first and second securing means
Trace memory, comprising: first selection means for selecting one; and external output means for outputting the contents of the built-in register, wherein the trace memory stores an output of the first selection means. Built-in microprocessor. 2. A second selection unit for selecting one of a trace result output from the trace memory and an output of the execution resource, wherein the output of the second selection unit is the output unit. The trace memory built-in microprocessor according to claim 1, which is connected to a write terminal of the built-in register. 3. When the execution sequence of a program changes according to an interrupt request signal output from the interrupt accepting unit, the first selecting unit selects and outputs a value secured by the first securing unit. 3. The micro-computer with a built-in trace memory according to claim 1, wherein a value secured by said second securing means is selected and output when an execution sequence of the program is changed by an instruction for changing a program execution order. Trace method using a processor. 4. The first selecting means selects a value secured by the second securing means when the execution sequence of the program is changed by a specific interrupt detection signal output from the interrupt accepting means. When the execution sequence of the program is changed by the instruction for changing the execution order of the program, the value secured by the first securing means is output according to the specific instruction detection signal output from the instruction decoding means. Select and output,
A trace method using the microprocessor with a built-in trace memory according to claim 1. 5. The tracing method according to claim 3, wherein the second selecting means selects and outputs the trace result when the read instruction is detected by the trace memory read instruction detecting means. 6. The tracing method according to claim 3, wherein the external output means outputs the contents of the internal register to the outside.