JPH0895905A - Bus interface circuit - Google Patents

Abstract

PURPOSE: To efficiently use a bus by controlling the use of the bus based on the frequency or priority of bus use among plural devices sharing the bus. CONSTITUTION: In the bus interface control circuit 103, plural pairs of respective signal lines to a bus 100 are provided and by allocating the-plural pairs of signal lines to respective devices 105 based on a using signal line control table 205, the bus possession frequency for each device can be controlled by a program. Besides, the bus use frequency of high-priority device is preferentially processed based on a bus priority control table 206. Further, by allocating plural device identification numbers to one device in the split type bus, even during data return waiting in a read operation, the other transaction can be executed inside the same device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit for a computer system, and more particularly to a bus interface circuit that enables efficient use of the bus based on the bus usage frequency and priority.

[0002]

2. Description of the Related Art Conventionally, in a computer system in which each component is connected by a bus, a device such as an adapter of an input / output device such as a disk or a communication adapter, which is a bus request source connected to the bus, is based on the bus specifications. Data bus,
Address buses, control signal lines, etc. are used as one set. Therefore, in a bus in which the priority of bus acquisition is evenly assigned to all devices connected to the bus, the bus request frequency differs depending on the size and function of the devices connected to the bus, The chances of winning are even. As a conventional technique for improving the bus acquisition frequency of a specific device with such a bus specification, for example,
There is a method disclosed in Japanese Patent Laid-Open No. 62-197851. With this technology, the priority order for bus acquisition is specified to the bus arbiter controlled by the program by the device slot number, address, etc. Therefore, it is necessary to rewrite the priority order every time the slot of the device connected to the bus is changed or the address is changed. There is.

Further, when a plurality of devices that use a common bus share a bus interface circuit, the processing order of transactions cannot be switched according to an arbitrary priority after receiving a bus usage request, so that a bus with a high priority is used. If the usage request occurs after the low priority bus usage request, the transaction for the high priority bus usage request is held until the end of the transaction for the low priority bus usage request.

Further, the read operation in the split type bus is divided into a phase in which the bus master sends an address to the slave and a phase in which the slave sends back data. Therefore, transactions of other devices connected to the bus can be executed during these phases. However, since the same device is assigned only one number for identifying the device connected to the bus by the bus controller such as slot number and physical address, the phase in which the slave sends back data Other transactions are kept waiting until they are finished.

[0005]

As described above, the control of the bus acquisition frequency of the device connected to the bus cannot be performed by the program controlling the device. In addition, when multiple devices that use a common bus share the bus interface circuit, priority control regarding bus usage between devices is insufficient, so bus usage according to the characteristics of each device such as performance and usage The priority control cannot be performed, which is a major obstacle in constructing a computer system with excellent overall performance. Further, during the read operation of the device connected to the split-type bus, other transactions are allowed to wait until the slave device completes the phase of returning data, although other transactions can be executed.

An object of the present invention is to solve the above-mentioned problems in the prior art, and to control the bus acquisition frequency by installing a program on a processor directly or indirectly connected to the bus or a bus interface control circuit. It is to be controllable by a program installed in the device. Another object of the present invention is to make it possible to control the priority of bus usage between devices even after receiving a bus usage request from a device when a plurality of devices using a common bus share a bus interface circuit. It is in. Still another object of the present invention is to provide a bus interface circuit that enables execution of another transaction even during a data return waiting time in a read operation of a device connected to a split type bus.

[0007]

In order to achieve the above object, a bus interface circuit of the present invention is connected to a bus and a plurality of devices using the bus, and the bus interface circuit from each device of the plurality of devices is connected to the bus. The acquisition of the bus for the request for use of the bus is performed based on the bus request signal and the bus grant signal, and each device can be used with a plurality of sets of bus interface circuit bus request signal lines and corresponding bus grant signal lines. A used signal line control table that holds the number of sets of signal lines,
Means for changing the contents of the use signal line control table,
In response to a bus use request from each device, the bus request signal line and the bus grant signal line are used within the range of the number of usable signal line groups of the device based on the contents of the use signal line control table. Means for acquiring the bus in response to a bus use request from the device.

In order to achieve the above second object,
A bus interface circuit of the present invention is connected to a bus and a plurality of devices that use the bus, and processes a transaction generated based on a request to use the bus from each device of the plurality of devices. Based on the contents of the bus priority control table, a bus priority control table holding the priority of the use of the bus of each device, means for changing the contents of the bus priority control table, , Means for determining the processing order of the transactions.

Further, in order to achieve the above third object,
The bus interface circuit of the present invention is connected to a split-type bus and a plurality of devices that use the bus, and processes a transaction that occurs based on a request to use the bus from each device of the plurality of devices. A bus interface circuit, wherein a device identification number control table that holds one or more numbers assigned to each device for identifying each device, and a device identification number control table that holds the device identification number control table And a means for changing the number of the device identification numbers assigned to the respective devices, and the number of the device identification numbers for the devices is maintained even while waiting for the data return in the read operation based on the bus use request from the respective devices. It is not used from the device identification number within the range. The use of numbers, perform other said transaction related to the device.

[0010]

A bus control in which the number of sets of signal lines that can be used by each device is held in a used signal line control table, and the contents are loaded with a program on a processor or a bus interface control circuit directly or indirectly connected to the bus. Since it can be changed by a program installed in the device, the bus acquisition frequency can be controlled by the program.

When a plurality of devices that use a common bus share a bus interface circuit, the priority order regarding the bus usage between devices can be held in a bus priority order control table and the contents can be changed by a program. Therefore, it is possible to flexibly control the processing order of the bus use request based on the device priority.

Further, even during the waiting time for the data return in the read operation of the device connected to the split type bus, other transactions related to the device can be performed within the range of the number of device identification numbers that can be assigned to the device. Can be executed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. First, the outline of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the principle of the present invention. In FIG. 1, a bus control device 102 is connected to a bus 100 via various signal lines and data lines. In addition to the bus control device, other components of the computer system such as a processor and a memory (not shown) are connected to the bus 100.
The bus control device 102 includes a bus interface circuit 103.
And a plurality of devices 105. Device 1
Reference numeral 05 includes an adapter of an input / output device such as a disk and a communication adapter for communication with other processors. The bus interface circuit 103 has a use signal line control table 205, a bus priority control table 206, and a device identification number control table 209 in addition to the bus control circuit 104. Bus interface circuit 10
Reference numeral 3 denotes a target part of the present invention, which will be described in detail later.

In FIG. 1, the conventional interface 101 in the interface between the bus 100 and the bus control device 102 has the same specifications as the conventional one, and the bus request signal line 203, the corresponding bus grant signal line 204, and the bus control device 102. Includes a signal line 207 indicating a number for identifying the device 105 connected to the bus 100. In the present invention, a plurality of signal line groups included in the conventional interface 101 are connected, and these are used to connect the bus 1
It is characterized in that it enables efficient use of 00.

First, the bus request signal line (201,
203) and the corresponding bus grant signal lines (202, 2)
04), a bus request signal line and a bus grant signal given by a program on a processor directly or indirectly connected to a bus 100 (not shown) or a program incorporated in a bus controller equipped with a bus interface control circuit. By referring to the used signal line control table 205 that stores the number of used lines, it is possible to make a plurality of bus requests.

Secondly, in response to a bus use request from a plurality of devices 105 using the common bus 100, a program on a processor directly or indirectly connected to the bus 100 (not shown) or a bus interface control circuit is mounted. By referring to the bus priority control table 206 that enables changing the priority regarding the use of the bus 100 between the devices 105 given by the program incorporated in the bus control device, the priority of the priority accepted later in time is confirmed. It is possible to switch the order of processing of a transaction generated based on a high bus usage request and processing of a transaction generated based on a low priority bus usage request received earlier in time.

Thirdly, the bus control device 102 is connected to the bus 100.
A plurality of signal lines (207, 208) indicating a number for identifying the device 105 connected to the bus are assigned, and a program on a processor directly or indirectly connected to the bus 100 (not shown) or a bus interface control circuit is mounted. By referring to the device identification number control table 209 that enables the number of uses of the number given by the program incorporated in the bus control device to be changed, the number is also used from the number for the waiting time for data return in the read operation. The use of unnumbered numbers allows other transactions inside the device to be performed.

FIG. 2 is a block diagram of the bus interface circuit 103 which is an embodiment of the present invention. In FIG. 2, rectangles show the components of the circuit, thick lines show the flow of data, and thin lines show the flow of control signals. The bus control circuit 104 in FIG. 1 is not shown in FIG.
It consists of each component except one control table.

The bus interface circuit 10 shown in FIG.
3 is a plurality of bus request signal lines 201 and 202,
A plurality of bus grant signal lines 203 and 204, a use signal line control table 205 that stores the number of uses of the bus request signal line and the bus grant signal line, and a bus priority control table that stores the priority order of the bus 100 use between the devices 105. 206, the bus control device 102 is the bus 100
Signal lines 207 and 208 and signal lines 207 and 20 indicating numbers for identifying the device 105 connected to the
8 includes a device identification number control table 209 that stores the number of used numbers.

As other constituent elements, a flip-flop 210 holding an address or data output from the device 105 to the bus 100, a flip-flop 211 holding an address or data input from the bus 100 to the device 105, and a bus request signal. Bus request signal transmission unit 212 that receives a bus grant signal, a bus control signal transmission unit 213 that transmits a bus control signal other than the bus request signal, and a bus control signal that receives a bus control signal other than the bus grant signal. By referring to the reception unit 214 and the bus priority control table 206, the priority control unit 215 that controls the priority regarding the use of the bus 100 between the devices 105, and manages the protocol sequence of the bus 100 for each transaction type of the bus use request. Protocol control unit 216 and 21
7. A request acceptance control unit 218 that performs arbitration for the bus usage request of the device 105, and accepts the bus usage request based on the usage status of the protocol control units 216 and 217, completion of request acceptance for the device 105, and a data strobe signal. Device control signal generation unit 219, priority control unit 2
15 based on the output signal of the
Selector 220-a for switching the address or data output to 0, and selector 22 for switching the address or data input by the device 105 from the bus 100.
0-b, a protocol control unit (216, 216, which inputs a bus grant signal based on the output signal of the priority control unit 215).
217) specifying the decoder 221 and the priority control unit 2
The protocol control unit (216, 216,
A selector 222 for switching the output of 217) is included. The values of the control tables 205, 206, 209 are the bus 100
A program on a processor directly or indirectly connected to a bus 100 (not shown) connected to the computer or a program incorporated in a bus controller (device 1
(Including a ROM implemented in 05) and the like.

The request acceptance control unit 218 determines the priority of the bus use between the devices 105 specified in the bus priority control table 206 and the bus use request signal line 2 asserted by the device 105 requesting the bus use.
The outputs of 23 are compared, and a bus use request from a device with a higher priority is selected. At the same time, the states of the protocol control units 216 and 217 are confirmed, and if the protocol control unit is not in use, the bus use request is accepted.

As a result, the request acceptance control section 218 carries out the following (1) to (3). (1) Instruct the bus request signal transmission unit 212 to assert the bus request signal. (2) Protocol control unit 216 in an unused state
Alternatively, 217 (select one if a plurality of protocol control units are not used) activates the sequence corresponding to the transaction type of the received bus use request. (3) The priority control unit 215 is notified of the received device number and the protocol control unit number activated in (2).

According to (1), the bus request signal transmitter 2
12 asserts a bus request signal to the bus request signal line 201 or 202 within the range of the number of used bus request signal lines designated in the used signal line control table 205.

According to (2), the priority control unit 215 causes the device 1 designated in the bus priority control table 206 to
05 Bus 100 use priority and device 1
By comparing the numbers 05, the selector 220 is switched and the address or data 224 to be output from the device 105 to the bus 100 is set in the flip-flop 210 at the preceding stage of the bus 100. At the same time, the decoder 221 and the selector 222 are switched to select the protocol control unit 216 or 217 that is processing the transaction corresponding to the bus use request from the device 105 having a high priority.

The protocol control unit 216 or 217, which has received the activation instruction in (3), goes into a bus grant waiting state.

When the bus request signal transmission unit 212 receives the bus grant signal from either the bus grant signal line 203 or 204, the bus request signal transmission unit 212 sends a bus use request from the device 105 having the highest priority designated by the decoder 221. Prompt the protocol control unit processing the corresponding transaction to operate as a bus master. Further, it outputs a signal for freezing the priority control to the priority control unit 215.

The protocol control unit sends the sequence signal corresponding to the transaction type to the bus control signal transmission unit 21.
3 and, if necessary, outputs to the device control signal generation unit 219. Simultaneously with the completion of the sequence as the bus master, a signal for instructing the priority control section 215 to cancel the freeze of the priority control is output.

The bus control signal transmitter 213 outputs a bus control signal according to the sequence output by the protocol controller. At this time, the numbers indicated by the signal lines 207 and 208 are
The device is selectively used within the range indicated by the device identification number control table 209. When the transaction type is a read operation, the bus control signal receiving unit 214 is notified of the correspondence between the number used and the number of the protocol control unit.

When the read data is returned from the bus, the bus control signal receiving unit 214 instructs the protocol control unit processing the corresponding transaction to fetch the data.

In the above description, one embodiment of the bus interface circuit embodying the present invention is shown. However, the present invention is not limited to the above embodiment, and various modifications are made without departing from the spirit of the invention. It goes without saying that is possible. For example, the priority control in this embodiment is
Between devices with fixed priority, which allows the priority to be changed by a program on the processor directly or indirectly connected to the bus or by a program incorporated in the bus controller equipped with the bus interface control circuit. However, it becomes possible to control the priority order after receiving the bus use request. Further, the applied device and the bus interface circuit may be configured in a one-chip LSI. Furthermore, each signal line has two,
It goes without saying that any number of three or more may be used.

[0031]

According to the present invention, when constructing a system in which a plurality of devices are connected to the same bus, not the number of devices but the scale of devices, required functions, performance,
The bus acquisition frequency can be adjusted in consideration of speed and the like.

Further, when a plurality of devices using a common bus control the bus interface circuit, priority control regarding bus use between devices can be realized by a program, and after receiving a bus use request from the device. Can also be controlled.

Further, even during the waiting time for data return in the read operation of the device connected to the split type bus, other transactions inside the device can be executed, so that the processing efficiency inside the device is improved.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of a bus interface circuit according to an embodiment of the present invention.

[Explanation of symbols]

100 ... Bus, 102 ... Bus control device, 103 ... Bus interface circuit 104 ... Bus control circuit, 105 ... Device 201, 202 ... Bus request signal line 203, 204 ... Bus grant signal line, 205 ... Use signal line control table 206 ... Bus priority control table 207, 208 ... Device identification number signal line 209 ... Device identification number signal line, 212 ... Bus request signal transmitting section 213 ... Bus control signal transmitting section, 214 ... Bus control signal receiving section 215 ... Priority control section 216, 217 ... Protocol control unit 218 ... Request reception unit, 219 ... Device control signal generation unit

Front page continuation (72) Inventor Hidenori Inouchi 1-280, Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. Department

Claims (3)

[Claims] 1. A bus request signal and a bus grant signal, which are connected to a bus and a plurality of devices that use the bus, and obtain the bus in response to a request to use the bus from each device of the plurality of devices. A bus interface circuit for transmitting the bus request signal, and a plurality of sets of bus grant signal lines for transmitting the bus request signal and corresponding to the bus request signal line for transmitting the bus grant signal. A use signal line control table that holds the number of sets of the signal lines that can be used by each device, a unit that changes the contents of the use signal line control table, and a bus use request from each device. Within the range of the number of usable signal line sets of the device based on the contents of the used signal line control table. Bus interface circuit, characterized in that it comprises using a strike signal lines and the bus grant signal line and a means for performing the acquisition of the bus for the bus use request from the device. 2. A bus interface circuit that is connected to a bus and a plurality of devices that use the bus, and that processes a transaction generated based on a request to use the bus from each device of the plurality of devices. ,
A bus priority control table that holds a priority regarding the use of the bus of each device, a unit that changes the contents of the bus priority control table, and a transaction priority based on the contents of the bus priority control table. A bus interface circuit having means for determining a processing order. 3. A bus interface circuit, which is connected to a split-type bus and a plurality of devices that use the bus, and processes a transaction generated based on a request for use of the bus from each device of the plurality of devices. A device identification number control table that holds one or a plurality of numbers assigned to each device to identify each device, and each device that is held in the device identification number control table. And a means for changing the number of the device identification numbers to be allocated, and within the range of the number of the device identification numbers for the devices even while waiting for the data return in the read operation based on the bus use request from each device. By using an unused number among the device identification numbers, A bus interface circuit and executes the other of the transactions for the device.