JPH0895904A - Bus controller - Google Patents

Abstract

PURPOSE: To speedily transmit plural bus requests generated inside an I/O device to a bus arbiter device by simultaneously asserting plural bus request signals and to guarantee the execution of a bus transaction while keeping the order of the reception of bus requests arbitrated inside the I/O device on the side of the I/O device. CONSTITUTION: A bus control circuit inside the I/O device is controlled while being divided into modules composed of a bus request queue control circuit 102 for storing the order of the reception of plural bus requests, bus request control circuit 101 for asserting the plural bus request signals in any arbitrary order, and bus request distributing circuit 107 for serializing the bus requests outputted from any arbitrary number of logic bus requesters and afterwards distributing them to any arbitrary number of logic bus requester control circuits 103 and 104, or the like. Thus, the coincidence of the reception order of bus requests outputted from the plural logic bus requesters and arbitrated inside the I/O device and the order of bus service to these logic bus requesters is guaranteed by an I/O device 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O device connected to an I / O bus of a computer system such as a personal computer, a workstation, etc., and particularly enables a plurality of bus request signals assigned to the device itself. A bus control method in which the I / O device side guarantees that the bus request order arbitrated in the I / O device and the bus acquisition order for the bus request permitted by the bus arbiter device match while issuing a bus request at high speed. Involved in.

[0002]

2. Description of the Related Art The following technique has been used as a bus control method when an I / O device acquires a right to use a bus by using a plurality of bus request signals assigned to itself.
The purpose of using a plurality of bus request signal lines is to realize a low latency and high throughput data transfer function.

FIG. 2 shows a computer system including an I / O device, a bus arbiter device, a CPU device, and an MS device using a bus control system based on the conventional technique.

Two logical bus requesters capable of simultaneously issuing bus requests are connected to the I / O device 200, and two bus request signals are used to simultaneously issue a bus acquisition request to the bus arbiter device 220. Notice. Here, the logical bus requester is a bus request of the physical bus requester 209 so that the number of logical bus requesters existing in the I / O device is equal to the number of bus request lines that can be used by the I / O device. It refers to a newly created bass requester by logically dividing the operation. The logical bus requesters operate in parallel to perform the bus request operation to be performed by the physical bus requesters, using separate bus request signal lines. For example, suppose there is only one physical bus requester in the I / O device and it is the requester requesting an MS read, as an example, the first logical bus requester issues an MS read bus request at address N. The bus requester and the second logical bus requester can be mapped to the bus requester that issues the MS read request at the address (N + 1). If the physical bus requester consists of an MS access request issued by the transmitting channel and an MS access request issued by the receiving channel, it is possible to map the logical bus requester to the physical bus requester itself. It is also possible to map the MS read request of the channel to the first logical bus requester and the MS write request of the transmission / reception channel to the second logical bus requester. As shown in FIG. 2, in the conventional bus control method, the bus request issued by the first logical bus requester 205 and the bus request issued by the second logical bus requester 206 are serviced by the bus control logic that operates independently. It was

The operation of the bus control logic from the first logical bus requester 205 issuing a bus request until the service to the logical bus requester starts will be briefly described below. The first logical bus requester 205 activates the first bus request control circuit 203 and the first logical bus requester control circuit 201 by asserting the first bus request signal 210. The assertion of the first bus request signal 210 causes the first bus request control circuit 203 to immediately assert the first bus request signal 221. on the other hand,
The first logical bus requester control circuit 201 outputs the bus request signal 2
When the bus grant is received by the assertion of 14, the address information output to the bus and the control information are stored. When the bus arbiter device 220 asserts the first bus grant signal 223 as a result of the bus request arbitration, the first bus request control circuit 203 asserts the bus grant signal 214 for the first logical bus requester control circuit 201, and the first bus grant signal 214 is asserted. The logical bus requester control circuit 201 gives a bus right to the first logical bus requestor 205 by asserting the bus right permission signal 206 to the first logical bus requestor 205. As a result, the service for the first logical bus requester that issued the bus request is started. The operation of the second logical bus requester is performed in parallel just like this.

As described above, in the I / O device using the conventional technique, the bus request of each logical bus requester is driven by the dedicated bus request control circuit to drive the dedicated bus request signal, and the dedicated logical bus requester is driven. By controlling the logical bus requester with the control circuit, a plurality of logical bus requesters are operated in parallel. In other words, in the prior art, when the bus request signal is asserted, the logical bus requester connected to the I / O bus is predetermined when the bus grant signal corresponding to the bus request signal is asserted. The method was adopted.

[0007]

SUMMARY OF THE INVENTION In the above conventional technique,
There are issues listed below.

(1) If the bus arbiter device does not have a queue for storing the assertion order of a plurality of bus request signals input from a plurality of I / O devices, a certain I / O
Since it is not possible for the bus arbiter device side to completely guarantee that the assertion order of multiple bus request signals output by the device and the assertion order of the corresponding bus grant signals match, the logical bus requester in the I / O device is A mismatch occurs between the generation order of bus requests issued and the execution order of services to the logical bus requester.

For example, when the bus arbiter device uses a round robin arbitration algorithm, when a plurality of logical bus requesters generate bus requests at exactly the same time, a plurality of bus request signal lines are simultaneously asserted. However, since the order in which the bus grant signal lines are asserted by the round robin arbitration algorithm depends on the previous arbitration result, it cannot be predicted in advance which logical bus requester will acquire the bus and in what order.

In this way, if it is not possible to guarantee the coincidence between the generation order of bus requests issued by the logical bus requester in the I / O device and the execution order of services to the logical bus requester, the following inconvenience occurs. For example, Figure 4
When mapping MS read requests for consecutive addresses (N, N + 1) on MS to bus requests of separate logical bus requesters and making bus requests in parallel, as shown in, two bus request signals are When asserted at exactly the same time, the bus request for (N + 1) address may be accepted before the bus request for N address. In this case, if the physical bus requester of the bus requestor expects read data to arrive in ascending order of addresses, it is necessary to prepare a buffer inside the I / O device to rearrange the data. As a result, the data transfer performance between the MS device and the physical bus requester is significantly reduced.

(2) By matching the number of logical bus requesters with the maximum number of bus request signal lines that can be used, the merit of using a plurality of bus request lines at the same time can be enjoyed. Depending on the form of data transfer performed by the physical bus requester, the physical bus requester may not be mapped well to the logical bus requester. In such a case, the purpose is to use multiple bus request lines at the same time to improve the data transfer speed. The significance of itself is lost.

(3) When a specific bus grant signal in which a failure has occurred in the bus arbiter device cannot be asserted, a logical bus in the I / O device expecting a failed bus grant signal. There is a problem of robustness that the bus operation of the requester hangs up.

According to the present invention, when an I / O device that uses a plurality of bus request signals is connected to a bus arbiter device having any arbitration algorithm, the bus request generation order issued by the logical bus requester in the I / O device is generated. The above problem is solved by realizing a bus control system that guarantees the execution order of services to the logical bus requester (hereinafter, the expression "fairness regarding bus acquisition is guaranteed" is used).

[0014]

In order to solve the above-mentioned problems (1) to (3), when a bus request signal is asserted, I / O is received when a bus grant signal corresponding to the bus request signal is received. Avoid determining which logical bus requester is connected to the bus. That is, the bus request signal is considered as a means for transmitting only the bus acquisition request to the bus arbiter device so that the bus request signal and the logical bus requester that has output the bus request are not correlated with each other. Furthermore, the number of logical bus requesters operating in parallel and the number of usable bus request signal lines are not correlated.

As a means for this, the bus request distribution circuit 10
After serializing the bus requests from multiple logical bus requesters that occur simultaneously in 7 in the intended order and serializing them, the bus request control circuit 101 simultaneously activates an arbitrary number of logical bus requester control circuits. Assert the bus request signals in any order. On the other hand, the correspondence relationship between the generation order of serialized bus requests and the logical bus requester that issued the bus requests is stored in the bus grant distribution circuit 102. The bus requests are stored in the bus grant distribution circuit 102 at the time when any of the bus grant signals assigned to the I / O device is asserted, and the bus requests are issued in the order of the bus requests by retrieving the bus requests with the highest priority. Provides service to the issued logical bus requester.

[0016]

As described above, since the bus request distribution circuit once serializes the bus requests that are generated simultaneously,
In the example of 4, multiple bus request signals are never asserted at the same time. Therefore, as long as it is used by connecting to a normal bus arbiter device, (N +
1) It is extremely unlikely that a bus request for address N will be accepted before a bus request for address N.
1) Even if the bus request for the address is accepted before the bus request for the address N, the bus transaction can be executed in the order of the bus request by storing the order of issuing the bus request in the bus grant distribution circuit. it can. Therefore, if it is assumed that the MS device that received the MS read request returns responses to the I / O device in the order in which the read requests were accepted, it is necessary to have a buffer inside the I / O device to sort the responses. The hardware burden on the I / O device side is reduced.

Further, the I / O device is connected to the I / O bus having the bus arbiter device having any bus arbitration algorithm by adopting the method of determining the logical bus requester to be connected to the bus for the first time by asserting the bus grant signal. In this case, it becomes possible to guarantee fairness regarding bus acquisition.

Further, in the bus arbiter device, as long as all bus grant signals assigned to the I / O device are not faulted, the service is requested by using the bus grant signal line which is operating normally. O The bus operation of all logical bus requesters in the device can be continuously executed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The bus control system of the present invention will be described below with reference to FIG. FIG. 1 shows an I / O device 100 having a bus control system according to the present invention, a bus arbiter device 120, a CPU device 132, and an M
1 shows a computer system including an S device 131. A plurality of I / O devices and a bus arbiter device 120 are connected to the I / O bus 130. Two logical bus requesters are connected to the I / O device and each asynchronously issues a bus request. The bus request distribution circuit 107 is a bus request signal of the first logical bus requester 105.
110 and the bus request signal 111 of the second logical bus requester 106
In accordance with the priority, one bus request signal is selected and multiplexed onto the bus request signal 112, and at the same time, an unused control circuit is selected from the two logical bus requester control circuits and activated. Bus request control circuit 101
Is asserted by the bus request signal 112 serialized by the bus request distribution circuit 107 to generate two bus request signals 12
Bus acquisition signal is issued to the bus arbiter device 120 by asserting 1 and 122 in any order, and the bus grant signal asserted by the two bus grant signals 123 and 124 that the bus arbiter device 120 asserts at an appropriate time. Negate the bus request signal corresponding to. Also,
A signal obtained by logically ORing the two bus grant signals 123 and 124 is output as a bus grant signal 113. The assertion algorithm of the two bus request signals in the bus request control circuit 101 is as follows, for example.

(1) When both bus request signals 121 and 122 are unused, a bus request signal with a smaller number
121 is asserted preferentially, but the bus request signal 121
When the next bus request signal 112 is asserted during assertion of, another bus request signal 122 is asserted.

(2) A round robin bus request system in which two bus request signals are alternately used.

In either of the bus request assertion methods (1) and (2), the bus request control circuit 101 determines the bus request signal to be asserted and the logical bus requester which is the factor for asserting the bus request signal. It does not correspond. This is because the bus request control circuit 101 does not store the information of the logical bus requester that issued the serialized bus request. This is in contrast to the conventional bus request control circuit shown in FIG. 2 in which the bus request signal and the logical bus requester that asserts the bus request signal are fixedly associated with each other. The bus grant distribution circuit 102 stores the order of the logical bus requester that issued the serialized bus request 112 in the bus request distribution circuit 107 and the bus request, and controls the logical bus requester by asserting the bus request signal. To select and activate the logical bus requester control circuit that asserts the service activation signal for selecting and activating the control circuit and controls the logical bus requester that uses the bus next by asserting the bus grant signal 113. Assert the bus grant signal.

In the following, the bus grant distribution circuit 102 stores the correspondence between the bus request signal and the logical bus requester that asserts the bus request signal, according to (1) a fairness guarantee bus control method for bus acquisition, and (2) priority. We show that it is possible to implement a priority-based bus control method that dynamically prioritizes services for high-bus requests.

As an example of the fairness guarantee bus control system, after first accepting the bus request of the first logical bus requester 105, before asserting the bus grant signal for the bus request of the first logical bus requester 105. The operation of each control logic when the bus request of the second logic bus requester 106 is accepted will be described. In order to realize the fairness guarantee bus control method regarding bus acquisition, the bus grant distribution circuit 102 first starts a bus transaction for the logical bus requester that has been the factor that asserts the bus request signal first.
t Serverd) method is used. First of all, the bus request distribution circuit
Similarly to the bus request control circuit 101, 107 selects and activates two logical bus requester control circuits by a selection algorithm based on priority or round robin. Here, the first logical bus requester control circuit 103 is selected and activated by the bus request of the first logical bus requester 105 and the second logical bus requester control circuit 104 is activated by the bus request of the second logical bus requester 106. Suppose. The service request signal 116 to the first logical bus requester control circuit 103 is asserted by the first bus request, and the first logical bus requester control circuit 103 receives the address necessary for the bus transaction of the first logical bus requester 105. , Transaction ID (ID attached to the logical bus requester controller), command, etc. are stored internally. Then, the second logical bus requester 106
The second logical bus requester control circuit 10
The service activation signal 119 for 4 is asserted, and the second logical bus requester control circuit 104 similarly internally stores information necessary for the bus transaction of the second logical bus requester 106. The bus arbiter device 120 outputs the first bus grant signal 112 or the second bus grant signal 1
When 24 is asserted, the bus request control circuit 101 asserts the bus grant signal 113, and the bus grant distribution circuit 1
02 asserts a bus grant signal to the logical bus requester control circuit which controls the logical bus requester connected to the bus next. In this case, the bus grant signal 114 for the first logical bus requester control circuit 103 is first asserted, and the assertion of the next bus grant signal causes the bus grant signal 115 for the second logical bus requester control circuit 104 to be asserted. . First logical bus requester control circuit 103 that first receives the bus grant signal
Asserts the bus right-of-use permission signal 118 to connect the first logical bus requestor 105 to the bus interface circuit 1
The second logical bus requester control circuit 104 connected to 08, and then receiving the bus grant signal also similarly asserts the bus right-of-use permission signal 117 to transfer the second logical bus requester 106 to the bus interface circuit 108. Connecting.

The bus request distribution circuit 10 sends a bus request asynchronously issued by two logical bus requesters through the above sequence.
Outputs to the bus in the order in which the internal arbitration was performed in 9 without any delay, and at the same time, matches the internally requested bus request order with the service start order corresponding to the bus request without depending on the bus request arbitration algorithm of the bus arbiter device. You can

Next, an embodiment of the bus control system with priorities will be described. In FIG. 3, after the I / O device 100 issues a read request request to the MS device 131, the CPU device 132
Shows a time chart in the case of issuing a read request to a register inside the I / O device. Here, it is assumed that the register read request inside the I / O device issued by the CPU device is a highly urgent request and needs to be serviced with the highest priority. Further, for convenience, the MS read request issued by the I / O device uses the first bus request signal line 121, and the bus request request issued by the I / O device for returning a response to the register read request issued by the CPU device is It is assumed that the second bus request signal line 122 is used. However, M issued by the I / O device
S read request to the second bus request signal line 122, CPU
The bus request request issued by the I / O device may be used for the first bus request signal line 121 to return a response to the register read request issued by the device. CPU device 132
In order to execute the service with respect to the read request issued by the highest priority, in the bus grant distribution circuit 102, the priority of the bus request signal for returning the response to the register read request that comes later in time is set. Set it to the top and lower the priority of the MS read request signal that came in earlier in time. After that, when either one of the bus grant signal lines is asserted, the bus request service for returning a response to the register read request which is a bus request with a high service priority is performed. Serves MS read request when asserted.
By dynamically changing the service priority of the bus request based on the priority of the bus request in the bus grant distribution circuit 102 in this way, it is possible to quickly service the bus request having a high degree of urgency. This is different from the conventional method in that in the method according to the present invention, there is a causal relationship between the logical bus requester that has issued the bus request that has driven the bus request signal line and the physical bus grant signal line. This is because the bus grant signal arriving due to factors other than the own bus request can be replaced with the bus grant signal corresponding to the own bus request. Figure 2
In the bus request control circuit using the conventional technique shown in, the logical bus requester and the logical bus grant signal line that issued the bus request that became the factor driving the bus request signal line at the time of driving the bus request signal line Since there is a causal relationship between the two, it is not possible to dynamically change the priority of the bus request service on the way.

In this embodiment, the number of bus request signal lines and the number of logical bus requester control circuits that can be used by the I / O device are the same, but according to the present invention, they must be the same. It is clear that there is no such limitation. On the other hand, in the I / O device using the conventional technology, the number of bus request signal lines and the number of logical bus requester control circuits must be the same, so the bus performance of the I / O device can be There is a limitation that it can be suppressed by the maximum number of signal lines. In general, to improve the data transfer performance of an I / O device by increasing the number of logical bus requesters and logical bus requester control circuits to the number of bus transactions that the I / O device can simultaneously execute. Will be possible. Further, according to the present invention, since there is no correlation between the bus request control circuit and the logical bus requester, it is possible to enhance the data transfer performance of the I / O device by increasing the number of the logical bus requester control circuits. It's easy.

[0028]

According to the present invention, even when a bus arbiter device having any bus request arbitration algorithm is connected to acquire a bus, the inside of the I / O device is not affected by the bus request arbitration algorithm of the bus arbiter device. I can get the bus in the order I intended, and I /
O There is an effect that the fairness regarding bus acquisition can be completely guaranteed on the device side. In addition, since multiple bus request lines are conventionally driven in parallel, the bus request issuance order and the service order reversal that occurs frequently do not occur, so the data between the MS device and the logical bus requester accompanying the service order reversal does not occur. It also has the effect of minimizing the deterioration of transfer performance. Also, since there is no restriction on the relationship between the number of bus request lines and the number of logical bus requesters that can be used, setting the number of bus request lines and the number of logical bus requesters to be used variably allows There is also an effect that it is possible to easily realize a highly flexible bus control system having a data transfer performance commensurate with the above. In addition, even if a specific bus grant signal cannot be returned due to a failure in the bus arbiter circuit, the bus operation can be continued using the bus grant signal that is operating normally, and There is a robust effect that the bus operation can be continued without initializing the I / O device even when the faulty bus grant signal is restored.

[Brief description of drawings]

FIG. 1 shows an I / O device, a bus arbiter device, and a CPU that share a plurality of bus request lines and request a bus.
Block diagram of a computer consisting of a device and MS device.

FIG. 2 is a block diagram of a computer including an I / O device, a bus arbiter device, a CPU device, and an MS device that make a bus request using a bus request line to which a plurality of devices are assigned.

FIG. 3 is a diagram showing the MS request of the I / O device and the I / O of the CPU device according to the present invention.
O Time chart when requests conflict.

FIG. 4 is a time chart when the conventional I / O device continuously issues MS read requests to consecutive MS addresses.

[Explanation of symbols]

100 ... I / O device 101 ... Bus request control circuit 102 ... Bus grant distribution circuit 103, 104 ... Logical bus requester control circuit 105, 106 ... Logical bus requester 107 ... Bus request distribution circuit 108 ... Bus interface circuit 109 ... Physical bus Requester 110, 111 ... Bus request signal 112 ... 110, 111 logical OR signal 113 ... 123, 124 logical OR signal 114, 115 ... Bus grant signal for logical bus requester control circuit 116, 117 ... Service for logical bus requester control circuit Start signal 118, 119 ... Bus right permission signal for logical bus requester 120 ... Bus arbiter device 121, 122 ... Bus request signal 123, 124 ... Bus grant signal 130 ... I / O bus 131 ... MS device 132 ... CPU device 200 ... Conventional I / O device 201, 202 ... Logical bus requester control circuit 203, 204 ... Bus request control circuit 205, 206 ... Logical bus requester 208 ... Bus interface circuit 209 ... Physical bus requester 210, 211 ... Service activation signal for logical bus requester control circuit 214, 215 ... Bus grant signal for logical bus requester control circuit 216, 217 ... Bus right permission signal for logical bus requester 220 ... Bus arbiter device 221, 222 ... Bus request signal 223, 224 ... Bus grant signal 230 ... I / O bus 231 ... MS device 232 ... CPU device.

Claims (6)

[Claims] 1. A bus request issued by an arbitrary number of physical bus requesters in an I / O device connected to a bus arbiter device that arbitrates bus requests issued by a plurality of I / O devices is assigned to the I / O device. The first means for transmitting to the bus arbiter device by asserting an arbitrary number of bus request signal lines and the bus request arbitration algorithm of the bus arbiter device do not rely on the bus transaction in the order intended by the I / O device. A bus controller having a second means for initiating. 2. A circuit for mapping an arbitrary number of physical bus requesters to an arbitrary number of logical bus requesters in the first means, and an arbitrary number of bus request signal lines allocated to the I / O device. Having only one bus request control circuit that asserts, the bus request control circuit selecting a bus request signal line not currently used as a trigger input by the bus request issued by the logical bus requester and asserting it in any order Transmits a bus request from an arbitrary number of physical bus requesters to the bus arbiter device without overlapping the start time of assertion of the bus request signal line.
Characterized by outputting a bus grant signal obtained by ORing an arbitrary number of bus grant signal lines issued to the device as a control signal for realizing the second means.
The bus control device according to claim 1. 3. The second means for controlling the arbitrary number of logical bus requesters, the same number of logical bus requester control circuits as there are logical bus requesters, a unique bus request distribution circuit, and a unique bus grant. In the bus request distribution circuit, a logical bus requester control circuit that controls the bus request by serializing the bus requests asserted simultaneously by the logical bus requester is selectively activated in the bus request distribution circuit, and in parallel with this. Then, in the bus grant distribution circuit, each time the bus request control circuit asserts a bus grant signal, the logical bus requester control circuit having the highest service priority is sequentially selected, so that a plurality of bus arbiter devices returns. The logical bus request with the highest service priority regardless of the assertion order of the bus grant line And performing bus transactions control of static, the bus control device according to claim 2, wherein. 4. In the bus grant distribution circuit, in a normal operation, the order of serialized bus requests in the bus request distribution circuit is stored so that the bus request received earliest in time is the most processed. By giving a high service priority, the order of bus request generation and the order of bus use permission are guaranteed to match, but if a bus request with a high priority arrives later in time, the service priority of the bus request will be given. 4. The bus control device according to claim 3, wherein the order of permitting the use of the bus can be dynamically changed by setting the highest degree. 5. In the bus request distribution circuit, when a bus request is accepted from a logical bus requester in a state in which the bus request can be accepted, if there is a bus requester control circuit that is currently unused, any order is possible. 4. The bus control device according to claim 3, wherein the bus control device is selected according to the above-mentioned item. 6. In the bus grant distribution circuit, a bus grant signal line that is operating normally even when an arbitrary bus grant signal line of the bus arbiter device is no longer asserted due to a failure inside the bus arbiter device. 4. The bus control device according to claim 3, wherein the bus transaction can be continued by using, and the bus transaction can be continued without initializing the I / O device when the failure of the bus arbiter device is recovered.