JPH0895805A - Task management device - Google Patents

Abstract

PURPOSE: To select a task which is low in priority level without changing the position of the task in a task ready queue by selecting the task which is low in priority each time a task schedule is generated from timer information and timing information. CONSTITUTION: When the bit of timer information in a timer communication area 9 corresponding to a bit '1' of a timing mask 10 is '1', a task is selected on the basis of a special priority level schedule instead of a priority level schedule. In the special priority level schedule, a bit map 5 indicating the position of an executable task for a priority level schedule in a ready queue is masked with one of bit patterns 4a-4d of a bit pattern 4 to find a bit map 6 indicating the position of an executable task for the special priority level schedule in the ready queue. With this bit map, special priority level scheduling is performed to select, for example, the task 8c which is low in priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a task management device for scheduling a plurality of executable tasks existing in the system.

[0002]

2. Description of the Related Art FIG. 4 is a schematic diagram showing the concept of a conventional task management apparatus for scheduling a plurality of tasks existing in a computer system in order of priority.

In FIG. 4, 1 is a bitmap showing a ready queue of executable tasks, 2 is a ready queue of executable tasks, and 3a, 3b and 3c are executable tasks consisting of a task control table.

The task schedule method shown in FIG. 4 is called a priority order schedule method. First, among the executable tasks existing in the system, the ready task management table is used to read the ready task ready. The ready queue 2 in which the executable task exists is obtained from the bitmap 1 indicating the queue.

Next, the task with the highest priority (task 3a in the case of FIG. 4) is selected from the obtained ready queues 2.

As another task scheduling method, based on the priority scheduling method shown in FIG. 4, the task management block information is used at the time of task switching to detect a task that is not selected for a long time and change the priority. Alternatively, a method of predicting the usage status of a central processing unit (CPU) and selecting a task is disclosed in, for example, the following document I
Are known as described in.

I Madonic & Donovan, Translated by Katsuo Ikeda, "Operating System," 1976, Computer Society of Japan, Chapter 4.

[0008]

However, in the task schedule method described in Document I, the task schedule becomes complicated because the task that is not selected for a long time is detected at the time of task switching and the priority is changed. However, there is a problem that the overhead of the central processing unit (CPU) increases.

Further, in order to realize flexible task selection according to the system status and job characteristics, it is necessary to grasp the system status, recognize the job characteristics, and predict the system status in the future. There was a problem that it became complicated.

The present invention has been made to solve the above-mentioned problems of the prior art. An object of the present invention is to increase the overhead of the central processing unit (CPU) when switching tasks in a task management apparatus. It is another object of the present invention to provide a technology that can improve the efficiency of the system and realize a flexible task schedule according to the usage status of the system.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) In a task management device of an information processing device that manages a plurality of tasks in priority order by a task execution queue and executes them while switching each of them, a task scheduling means for selecting the highest priority task and a timer. It is characterized by comprising means for selecting a task having a low priority order without changing the priority order when the task is scheduled at a constant timing generated from the information and the timing information.

[0014]

According to the above means, in the task management device of the information processing device, when the task is scheduled for each timing generated from the timer information and the timing information, the task with the lower priority is selected without changing the priority. It becomes possible.

As a result, it becomes possible to select a task having a low priority at a predetermined timing without changing the position of the task on the task ready queue for managing the priority.

Further, because of the simple design, the overhead of the central processing unit (CPU) is small and a high-speed task schedule can be realized.

Furthermore, by changing the timing information, it becomes possible to realize a task schedule according to the operating status of all systems, and it is possible to realize a flexible task schedule according to the usage status of the system. .

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a schematic diagram showing the concept of a task management apparatus which is an embodiment of the present invention.

In FIG. 1, 4 is a bit pattern for breaking the priority schedule, 5 is a bit map showing the position of the ready queue of the executable tasks for the priority schedule, and 6 is the executable task for the special priority schedule. Of the ready queue of the ready task, 7 is the ready queue of the executable task, 8a, 8b, 8c, 8
d is an executable task consisting of a task control table, 9 is a timer communication area, and 10 is a timing mask for breaking the priority schedule.

The task management apparatus of this embodiment, like the task management apparatus shown in FIG. 4, reads ready tasks for priority scheduling from the ready queue management table among the executable tasks existing in the system. The ready queue 7 in which the executable task exists is obtained from the bitmap 5 indicating the queue position.

Next, from the obtained ready queue 7, the task with the highest priority (in the case shown in FIG. 1,
Select task 8a).

Then, the selected task 8a is chained next to the task 8b having the same priority at the time of task switching.

Next, the task schedule in the task management system of this embodiment will be described.

In this embodiment, when the task is scheduled, the timer information of the timer communication area 9 communicated from the hardware is judged by the timing mask 10, and the bit "1" of the timing mask 10 and the corresponding timer communication are determined. When the bit of the timer information in the area 9 is “1”, the task is selected based on the special priority schedule instead of the priority schedule.

Here, the timer information in the timer communication area 9 is a bit pattern that is counted up or down by communication from the hardware.

In addition, when the maximum value or the minimum value is reached by counting up or counting down,
It is updated to the initial value.

In the special priority schedule, the bitmap 5 indicating the position of the ready queue of the executable task for the priority schedule is masked by one bit pattern (4a, 4b, 4c, 4d) of the bit pattern 4. , That is, the bitmap 5 and the bit pattern (4a, 4
b, 4c, 4d) and the corresponding bit is ANDed to obtain the bitmap 6 indicating the ready queue position of the executable task for the special priority schedule.

By carrying out a special priority schedule using this bitmap 6, for example, a task with a low priority (task 8c in the case shown in FIG. 1) is selected.

A plurality of bit patterns 4 are prepared. By changing the bit pattern 4a, the bit pattern 4b, the bit pattern 4c, and the bit patterns 4a and 4 at each opportunity of the task schedule, the tasks of the same priority order are assigned. Prevent selection.

The bit pattern 4 is set at the time of system startup so that the interactive low priority and the batch job priority class can be easily selected.

FIG. 2 is a flowchart showing a task selection processing procedure at the time of task scheduling in the task management system of this embodiment.

Next, with reference to FIG. 2, a task selection processing procedure at the time of task scheduling in the task management apparatus of this embodiment will be described.

First, in step 11, at the time of task scheduling, the bit "1" of the timing mask 10
It is determined whether or not the corresponding bit of the timer information in the timer communication area 9 is "1".

If NO in step 11, the process branches to step 18.

If YES at step 11,
After step 12, task selection processing based on the special priority schedule is executed instead of the priority schedule.

In step 12, the bit map 5 is converted into one bit pattern (4a, 4b, 4) of the bit pattern 4.
The bitmap 6 showing the position of the ready queue of the executable task for the special priority schedule is obtained, which is masked in c).

Next, in step 13, the pointer is updated to utilize another bit pattern in the next special priority schedule.

Next, in step 14, it is judged whether or not the pointer is the end of the bit pattern 4, and if the pointer is the end of the bit pattern 6, the pointer is updated to the beginning of the bit pattern 6 in step 15. .

Here, in step 13, step 14, and step 15, the bit pattern 4a, the bit pattern 4b, and the bit pattern 4 are set for each task scheduling opportunity.
c, and a process for changing the bit pattern 4a and the bit pattern 4.

In the special priority schedule in the task management system of this embodiment, the bit map 5 indicating the position of the ready queue of the executable task for the priority schedule is set to one bit pattern (4).
a, 4b, 4c) and the bitmap 6 is obtained.

Then, the bit patterns (4a, 4b, 4
Depending on c), it is assumed that all the bits of the required bit pattern 6 are 0.

Therefore, in step 16, all the bits of the bitmap 6 obtained in step 12 are 0.
Or not.

If YES in step 16, in step 17, the bitmap 5 showing the position of the ready queue of the executable task for priority scheduling is switched.

Here, step 16 and step 17 are
This is a process for switching to the bitmap 5 indicating the position of the ready queue of the executable task for the original priority schedule when all the bits of the obtained bitmap 6 are 0.

In step 18, the priority schedule is executed by the bitmap 5 indicating the position of the ready queue of the executable task for the priority schedule or the obtained bitmap 6.

That is, by executing the priority schedule by the bitmap 5, the task 8a is selected as described above in the case of FIG.

By executing the priority schedule by the bitmap 6, the task 8c is selected as described above in the case of FIG.

Here, when it is necessary to keep the priority order as in a subsystem such as system control, it can be dealt with by setting the bit of the bit pattern 4 to 1.

The timing of switching from the above-mentioned priority schedule to the special priority schedule is determined by the pattern of the timing mask 10.

That is, in FIG. 1, the timing mask 1
0 bit is the 0th bit in the direction of arrow A,
If it is expressed as the 1st bit ... 7th bit, and the timer information in the timer communication area 9 is changed in the direction of arrow A, the 0th bit of the timing mask 10 is set to "1". As a result, the number of times that the “1” bit of the timing mask 10 and the corresponding bit of the timer information in the timer communication area 9 becomes “1” increases, and the probability of performing the special priority schedule process at the time of task scheduling increases. Get higher

On the contrary, if the bit near the 7th bit is set to "1", the number of times that the bit of "1" of the timing mask 10 and the bit of the timer information corresponding to it in the timer communication area 9 becomes "1" is determined. As a result, the probability of performing special priority schedule processing at the time of task scheduling becomes low.

Then, the bit pattern of the timing mask 10 is set to, for example, "0,0,0,0,1," shown in FIG.
1 ”, the probability that the low-priority task is selected can be arbitrarily set.

Therefore, by using the bit pattern of the timing mask 10 as a tuning element and changing it at the time of system startup from the outside and at the time of switching from the online business center to the batch business center, the probability that the low priority task is selected Can be changed.

FIG. 3 is a graph showing the change in the central processing unit (CPU) usage rate when the bit pattern of the timing mask 10 is changed in the task management system of this embodiment.

In the graph of FIG. 3, 19 is the CPU usage rate of the high priority task, and 20 is the CP of the medium priority task.
U usage rate, 21 indicates the CPU usage rate of the low priority task.

As shown in FIG. 3, the timing mask 10
It is possible to change the CPU usage rate of the high priority task and the low priority task by changing the bit pattern of.

When a high priority work such as an online work is executed, a certain degree of batch performance is required, or in the opposite case, the operating status of the system changes.

In this embodiment, by changing the bit patterns of the bit pattern 4 and the timing mask 10 in such a case, the timing for selecting the task with the lower priority is increased or the absolute priority schedule is set. It is possible to realize a flexible task schedule according to the usage status of the system.

Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention.

[0062]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the task management system of the present invention,
It is possible to select low-priority tasks, and because of the simple design, it is possible to realize a high-speed task schedule with a small overhead of the central processing unit (CPU).

(2) According to the task management system of the present invention,
As shown in FIG. 3, by changing the bit pattern of the timing mask that takes the timing of changing from the priority schedule to the special priority schedule, the central processing unit (C
(PU) It is possible to change the usage rate, it is possible to realize a flexible task schedule according to the usage status of the system, and it is possible to support all types of systems.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing the concept of a task management device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a task selection processing procedure at the time of task scheduling in the task management device of the present exemplary embodiment.

FIG. 3 is a diagram showing a case where the bit pattern of the timing mask 10 is changed in the task management device of the present embodiment,
It is a graph which shows the change of a central processing unit (CPU) usage rate.

FIG. 4 is a schematic diagram showing the concept of a conventional task management device that schedules a plurality of tasks existing in a computer system in order of priority.

[Explanation of symbols]

1 ... Bitmap indicating position of ready queue of executable task, 2, 7 ... Ready queue of executable task, 3
a, 3b, 3c, 8a, 8b, 8c, 8d ... Executable tasks, 4 ... Bit pattern for breaking priority schedule, 5 ... Bit map indicating position of ready queue of executable tasks for priority schedule, 6 ... Bitmap indicating ready queue position of executable task for special priority schedule, 9 ... Timer communication area, 10
... Timing mask for breaking priority schedule, 19 ... CPU usage rate of high priority task, 20 ... CPU usage rate of medium priority task, 21 ... CPU usage rate of low priority task.

Claims (1)

[Claims] 1. A task scheduling means for selecting a task with the highest priority in a task management device of an information processing device, which manages a plurality of tasks for each priority by a task execution queue and executes them while switching each of them.
A task management device comprising: means for selecting a task having a low priority level without changing the priority level when a task is scheduled at constant timings generated from timer information and timing information.