JPH0895711A - Cd-rom disk reproducing device - Google Patents

Abstract

PURPOSE: To obtain the device which can access a CD-ROM disk, controlled and rotated at a speed higher than the linear speed of recording, at the high speed as it is without switching its rotation control mode. CONSTITUTION: This device is provided with a sector clock generating circuit 100 which generates a clock having cycles equal to the CD-ROM sector cycles at the time of the (k)-fold linear speed. Further, a system control part 51 can be informed of the clock timing of the sector clock generating circuit 100 each time the clock is generated, and the sector clock generating circuit 100 is so constituted by the system control part 51 as to control the start and stop of the clock generation and the setting of the generated frequency. Consequently, data which are written in a buffer memory 4 at a high speed are transferred at a specific rate to a host computer through the buffer memory 50 and a host interface controller 55.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD-ROM disc reproducing apparatus for recording digital data, and particularly to n (n
> 1) It has a constant double linear velocity or constant angular velocity read function, and can respond to a k double linear velocity mode read request from a host computer without sacrificing access time.
(K <n) The present invention relates to a CD-ROM disc reproducing apparatus for reading at double linear velocity.

[0002]

2. Description of the Related Art A compact disc for music (hereinafter referred to as a CD
CD-ROM, which is used in conjunction with a data memory of a computer or the like, has rapidly spread in recent years. The CD-ROM disc reproducing apparatus for reproducing the disc is required to have high-speed access and high-speed data transfer rate as well as improvement of the data processing capability of the computer as an external device. The CD is recorded at a constant linear velocity (hereinafter referred to as CLV) in order to increase the recording density, and the disc rotation differs by about 2.5 times between the inner circumference and the outer circumference.
Therefore, when reading the data recorded on the outer peripheral side of the disc, a rotation waiting time for stabilizing the rotation of the disc is required, and this time lengthens the access time. Therefore, in the CD-ROM disc reproducing apparatus, the default disc reproducing linear velocity is set to n times the recording linear velocity (n ≧ 2), or the disc rotation is controlled at a constant angular velocity (hereinafter referred to as CAV). This shortens the rotation waiting time and eliminates the spindle motor control time for keeping the linear velocity constant during movement of the optical pickup, thereby achieving high-speed access and high-speed data transfer rate.

FIG. 24 is a block diagram of a CD-ROM disc reproducing apparatus in which the maximum linear velocity is the quadruple linear velocity mode.

In the figure, 1 is a CD-ROM disc, 2 is a spindle motor for rotating the CD-ROM disc 1 at a quadruple linear velocity, 3 is an optical pickup for reading a recording signal from the CD-ROM disc 1, 4 Is a pickup feed motor for moving the optical pickup 3 in the radial direction of the CD-ROM disc 1, and 5 is a high-frequency amplifier for amplifying a detection signal from the optical pickup 3 and performing waveform equalization.

Reference numeral 6 denotes a characteristic switching circuit of the high frequency amplifier 5, which includes an analog switch, a fixed resistor, and a fixed capacitor. Reference numeral 15 is a rectangular wave shaped EFM (Eight) for converting the analog data signal S _RFA output from the high frequency amplifier 5.
A waveform shaping circuit for converting into a t to Fourteen Modulation signal S _EFM, and a reference numeral 16 is a bit synchronous clock generation PLL circuit for generating a bit clock signal for strobing a data bit from the self-clockable EFM signal S _EFM . Reference numeral 17 is a frequency response characteristic switching circuit of a PLL circuit including an analog switch, a fixed resistor, and a fixed capacitor. Two
Reference numeral 4 performs a predetermined process on the input EFM signal S _EFM , demodulates a data signal of a CD audio or CD-ROM format, performs error correction and a linear velocity control signal S.
_A digital signal processing circuit for generating a _CLV , a tracking error amplifier 25 for generating a tracking control signal S _TE from the detection signal S _RF of the optical pickup 3, and a focus error amplifier 26 for generating a focus control signal S _FE from S _RF. , 27 is a digital servo processor for processing the focus error signal S _FE , the tracking error signal S _TE , and the linear velocity control signal S _CLV , and 30 is a signal required for driving the pickup feed motor by processing the output signal from the feed servo amplifier 28. Is a feed motor drive amplifier, 31 is a focus coil drive amplifier for driving the focus actuator incorporated in the optical pickup 3, 32 is a tracking coil drive amplifier for driving the tracking actuator, and 33 is a spindle motor drive amplifier. .

Reference numeral 35 is an oscillation circuit using a crystal oscillator for generating a first master clock, 36 is an oscillation circuit using a crystal oscillator for generating a second master clock, and 39 is a first master clock. And a second master clock for selecting and supplying the selected master clock to the digital signal processing circuit 24.

Reference numeral 47 is an eject switch for instructing to eject a disc, and 48 is a busy indicator for instructing that data is being read from the disc and a predetermined process is being performed.

Further, 49 is a buffer memory, 50 is a buffer memory controller for managing a data flow including writing of the error-corrected CD-ROM sector data to the buffer memory 49, 51 is a system controller, 52 is a CPU, 53 Is a ROM storing the program of the CPU 50, and 54 is an R for temporary storage of the CPU 50
AM and 55 are CD-Rs stored in the buffer memory 49
It is a host interface controller that is controlled by the system controller 51 when transferring OM data to the host computer and acts as an intermediary between the host computer and the CD-ROM data processor. The host interface controller 55 includes a data register, a control register, and a status register that can be accessed by the host computer by direct addressing.

FIG. 25 is a diagram showing details of the high frequency amplifier 5 and the bit synchronous clock generation PLL circuit 16.

In the high frequency amplifier 5, 60 is a pickup preamplifier for amplifying an analog data signal of a minute amplitude output from the optical pickup 3, 61 is a high frequency amplification element, 62 to 64 are fixed resistors, and 65 is a fixed capacitance capacitor. , 66 to 69 are switch transistors, and 70 to
73 is a fixed base resistor.

In the bit synchronous clock generation PLL circuit 16, 74 is a phase comparator, 75 is a 1/2 frequency divider, and 76.
Is a quarter frequency divider, 77 is a clock switching circuit, 78 is a voltage controlled oscillator (hereinafter referred to as VCO), 79 is an operational amplifier, 80 to 82 are fixed resistors, 83 is a T _max detection circuit,
Reference numerals 84 to 87 are switch transistors, and reference numerals 88 to 91 are fixed resistors as base resistors.

The high frequency amplifier 5 has a high frequency characteristic compensation function. The T _max detection circuit 83 is a circuit for detecting the maximum inversion interval T _max of the EFM signal by using the VCO output clock S _VCO , and the bit synchronous clock generation PLL circuit 16 is unstable when the power is turned on or the disk is searched. When the sync signal cannot be detected normally, it operates to generate a signal for preventing mislock and for quick sync pull-in.

FIG. 26 shows a register configuration accessible from the host computer among the registers provided in the host interface controller 55.

The write registers are a "Command" register, a "Data" register, and a "Byte Count".
(H / L) ”register,“ Drive Contro ”
l "register and" Drive Select "register, and the read register is" Error Sta ".
"tus" register, "Data" register, "Byte"
"Count (H / L)" register, "Drive St"
It is composed of an "atus" register and a "Bus Phase" register.

FIG. 27A shows the details of the write register described above, and FIG. 27B shows the details of the read register described above.

First, the write register group will be described. Various commands from the host computer to the drive are written in the "Command" register as operation codes and accompanying parameters.

Data associated with the command or data for testing the buffer memory is written in the "Data" register. "Byte Count (H / L)"
The number of transfer bytes required by the host computer is set in the register, and the designation of the transfer method, the interrupt instruction, and the software reset are instructed by the "DriveControl" register. In addition, "Drive Sele
The drive unit for which the command is issued is designated by the ct "register. Up to two units can be connected by one interface port of this CD-ROM disc reading device. Further, in FIG. It also shows the bit role in the register.

The read register in FIG. 27B is the system controller 51 or the system controller 51.
Is a register group to which the buffer memory controller under the control of writes.

The "Error Status" register is a register for reporting to the host computer the details of the error that occurred in the drive due to the execution of the command. The "Data" register is loaded with the CD-ROM data in the buffer memory to be transferred to the host computer or the data generated by the system controller. The “Byte Count (H / L)” register is used by the system controller 51 to set the number of bytes to be transferred to the host computer in one processing and report it to the host computer. "Drive St
The status of the drive (busy, data transfer request, error occurrence, seek completion, error correction execution, command response possible) is loaded in the "atus" register.

The "Bus Phase" register is used for IO
Bit and C / D bit and "Drive Stat"
Used by the combination of the DRDY bits of the "us" register to indicate the transfer phase of the interface bus.

Here, the function (role) of each bit of each register will be described.

"Error Status" Register Bit7: MCR (Mmedia Change Re)
If this bit is set, it indicates that the disc has been modified.

Bit6: ABRT (Aborted C
command) When this bit is set, the CD-ROM disc player indicates that execution of the command has been interrupted.

Bit 5: EOM (End of Med
ia Detected) When this bit is set, it indicates that the lead-out area has been reached during reading of data.

Bit4: ILI (Illegal Le
Indication) If this bit is set, "Tr
"transfer Le-ngth" or "Alloc
"Application Length" is illegal.

Bits 3 to 0: Sense Key A predetermined "Sense Key" code indicating the cause of the error is set.

"Drive Status" register Bit7: BUSY CD-ROM disc player indicates that the command is being executed (busy).

Bit6: DRDY (Drive Re
ady) The system controller 51 sets this bit if it can respond to the command from the host computer.

Bit4: DSC (Drive Seek)
Completed) This bit is set when the seek is completed in the data track in which the sector of the designated block address is arranged.

Bit3: DRQ (Data Request)
st) The system controller 51 sets this bit when data transfer with the host computer becomes possible.

Bit2: CORR (Corrected
Data) This bit is set when the CD-ROM data transferred immediately before is corrected.

Bit 0: ERR (Error) The system controller 51 sets this bit when an error is detected as a result of execution of the last command or failure diagnosis.

Bit 5 and 1: Unused "Bus Phase" register The IO bus and the interface bus phase are instructed to the host computer by the combination of the C / D bit and the DRQ bit.

When the DRQ IO C / D is "101", it is in the command phase and the command can be accepted. When DRQ IO C / D is “111”, it is the message phase and message data can be transferred to the host. When the DRQ IO C / D is "110", it is in the data in phase and the command parameter is transferred from the CD-ROM disc reproducing device to the host computer. DR
When Q IO C / D is “100”, it is in the data out phase, and the command parameters are transferred from the host computer to the CD-ROM disc reproducing device. DRQ I
When OC / D is "011", it is in the status phase, and the status register holds valid status data.

Returning to FIG. 24, description will be made.

The quadruple linear velocity CD-ROM disc reproducing apparatus shown in FIG. 24 has four kinds of reproducing linear velocity modes. The initial state after the power is turned on is set to the quadruple linear velocity mode and the disc is a spindle. When the optical pickup 3 is mounted on the motor 2, if the optical pickup 3 is located at the innermost circumference, it continues to rotate at about 2000 rpm and waits for a command from the host computer. Also, in each linear velocity mode,
Securing a predetermined reading error rate, optimum servo system frequency response characteristic setting, master clock frequency setting of the digital signal processing circuit 24, and bit synchronous clock generation P
The circuit constant or the clock frequency division number is switched for the LL circuit 16 to generate a predetermined frequency clock. These switching operations are executed via an I / O (Input / Output) port controlled by the system controller 51. Servo system frequency response characteristics are
Focus servo processor, tracking servo processor, C built in the digital servo processor 27
Digitally set by the LV Servo Processor.

Table 2 shows the setting of the switching unit in each linear velocity mode.

FIG. 28 shows the relationship between the state of the switch for switching the characteristics of each circuit shown in FIG. 25, the output clock, and the double speed.

By the way, depending on the CD-ROM application software, the reproducing linear velocity of the CD-ROM disc is a linear velocity lower than the default quadruple linear velocity, that is, the same linear velocity as that at the time of recording. Some of them are produced on the assumption that they will be played at any of the triple linear velocities.

Here, the sustain (Sus
FIG. 29 (A), in which the (Tained) mode reading is necessary.
The CD-ROM disc having the data structure shown in FIG.
A case of reproducing by the host computer 200 having the configuration shown in (B) will be described.

The coding mode shown in FIG. 30 is defined for the CD-ROM XA ADPCM audio, and data compression and recording are performed on the assumption that the recording linear velocity and the reproducing linear velocity are the same. .

In FIG. 29B, the CD-ROM disc reproducing device 201 is connected to the storage device interface 203 of the host computer 200 by the interface bus 202. A CD-ROM XA ADPCM audio demodulation circuit 204 is connected to the storage device interface 203, and the demodulated audio signal is amplified by an audio amplifier 205 and output as a reproduced sound from a speaker 206. The video data is processed by the computer unit 207 and displayed on the display 208. User request is keyboard 2
09 to the computer unit 207.

Each part of the interface bus 202 will be described. DD7-DD0 are 8-bit data bus, DMAR
EQ is a DMA request signal, DMACK * is a DMA acknowledge signal, CS1FX * is a CD-ROM disc playback device register selection signal, and DIOR * is a CD-RO.
M disc playback device register read signal, DIOW *
Is a CD-ROM disc register write signal, DIA
2-DA0 is a register address signal. IORDY is a wait request signal, HRESET * is a reset signal from the host computer, and an interrupt signal to the HINT host computer.

The CD-R having the data structure shown in FIG.
In the OM disc, track 01 has a sector of CD-ROM mode 1 format, and track 02 has a CD-R.
OM mode 2 form 1 and form 2 sectors are recorded. In the track 02, CD-ROM XA ADPCM audio sectors are periodically interleaved and arranged between video data sectors.

FIG. 31 shows the sector format of the CD-ROM mode 2 form 2 and the structure of the video sector and audio sector in which data is stored according to this format.

The data of the track 01 is the CD-RO.
A volume descriptor, a directory, a path table, etc. relating to the M disc are recorded, and since these data are data that do not depend on the reproduction linear velocity, the quadruple linear velocity can be read. Track 02 has ADPCM audio sector, video / text data and ADP
CM audio data has a sector interleave ratio of 3:
It is located at 1. Normally, the ADPCM audio demodulation circuit 204 on the host computer 200 side presupposes that sector data is transferred at a cycle of 1/75 sec by 1 × linear velocity reproduction. Must be set to.
The host computer 200, which controls the CD-ROM disc reproducing device 201, sets the CD-ROM disc reproducing device 201 to the linear velocity mode designated by the application program for reproducing the CD-ROM disc.
In contrast, the “Set CD in the format shown in FIG.
Issue a "ROM Speed" command.

In the command shown in FIG. 32, the linear velocity is the data transfer rate KB / se as shown in FIG.
Specify in 2-byte binary format with c as the unit.
The system controller 51 of the CD-ROM disc reproducing apparatus 201 that has received the “Set CD-ROM Speed” command analyzes the code stored in the second and third bytes of the parameter, and determines the linear velocity specified by the host computer 200. judge. If the specified linear velocity can be determined, each part in the reproducing apparatus is set to the constant or clock frequency corresponding to the 1 × speed shown in FIG. 30 through the I / O port. When the setting is completed and the next command can be accepted, the execution status is returned to the host computer 200 via the status register. The host computer 200, which has confirmed the completion of command execution on the CD-ROM disc reproducing device 201 side, continues to the “Test Unit Read” shown in FIG.
y ”command is issued to test whether or not the linear velocity converges to 1 × linear velocity and is ready for data reading and data transfer. The system controller 51 receiving the“ Test Unit Ready ”command causes the TOC ( Table of Contents)
The sub-code data of the area is read and compared with the data read in the quadruple speed mode. If the two data match, the host computer 2
00, the "Ready" status is reported as a sense key, and the "Not Ready" status is reported as a sense key.

The host computer 200 is a CD-RO.
The "Test Unit Ready" command is periodically issued until the M disc reproducing apparatus 201 reports the ready status. When the ready status is reported from the CD-ROM disc reproducing apparatus 201, the status shown in FIG.
The "Read XA" command shown in FIG. 5 is issued to read image data, sound data, or text data of a required size designated by "Transfer Length" from the desired "Logical Block Address".

FIG. 36 shows "Set CD-ROM Spe".
By executing the "ed" command, the spindle motor speed is reduced from 2000 rpm at the quadruple linear velocity to the target 50
It shows the change until convergence to 0 rpm and data can be read correctly. In the figure, the deceleration time from point B to point C needs to be about 1.2 seconds or more.

The CD-ROM disc reproducing device 201 is
Mode 2 Form 2 by "Read XA" command
The CD-ROM sectors are transferred from the buffer one by one to the host computer 200. At this time, 1
Before the transfer of sector = 2340 bytes, an interrupt signal _SHINT is generated for the purpose of instructing transfer data ready and supplying a reproduction timing reference on the host computer 200 side. This _SHINT signal is periodically generated during data transfer, and its average period is 1/75 second, which is equal to the CD-ROM sector period at the time of 1x speed reproduction. Host computer 2
Each time 00 receives an interrupt, one sector of data is read from the "Data" register by any method of DMA or program transfer (hereinafter referred to as PIO transfer) instructed to the CD-ROM disc reproducing device 201.

As described above, the host computer 200 cannot read the target data until it converges to the 1 × linear velocity, and as a result, the access speed is very slow.
It has a drawback that it becomes a D-ROM disc reading device. In addition, when the CD-ROM disc for exclusive use of the 1 × linear velocity is replaced with a CD-ROM disc which does not depend on the reproducing linear velocity to access at the 4 × linear velocity, “Set CD
As in the case of the deceleration, the acceleration accompanying the linear velocity change to the quadruple linear velocity by the "ROM Speed" command speed also requires a long convergence time, and therefore has a drawback that the initial access time becomes long. 4 such drawbacks
The same applies to the transition between the double linear velocity mode and another linear velocity mode (double linear velocity or triple linear velocity). Further, by having a plurality of linear velocity modes, it is necessary to switch various constants in order to maintain the data reading performance at each linear velocity, and there is a drawback that the number of parts increases and the cost increases.

[0052]

Therefore, the problem to be solved by the present invention is to solve the problems of the above-mentioned prior art, and to control the rotation of a CD-ROM disc in which the rotation is controlled at a higher speed than the linear velocity during recording. It is an object of the present invention to provide an inexpensive CD-ROM disc reproducing apparatus capable of accessing a CD-ROM disc to be reproduced at the same linear velocity as that at the time of recording at high speed without switching.

[0053]

[Means for Solving the Problems] CD-RO according to the present invention
In order to achieve the above-mentioned object, the M disc reproducing apparatus has k
Sector clock generation means for generating a clock having a cycle equal to the CD-ROM sector cycle at the time of double linear velocity is provided. Further, the system control means can be notified each time a clock is generated from the sector clock generation means, and the sector clock generation means can start and stop the clock generation by the system control means.
Also, it is configured to control the generation frequency setting.

[0054]

That is, the CD-ROM disc reproducing apparatus according to the present invention generates, by the sector clock generating means, a sector clock having a frequency which is k times the frequency of the sector synchronization signal corresponding to the k linear velocity instructed by the host computer. , CD-RO driven at a higher linear velocity than the recording linear velocity
The CD-ROM data read from the M disk and temporarily stored in the buffer memory is controlled to read one sector data from the buffer memory based on the sector clock, and to control the data transfer to the host computer. CD-ROM read from a CD-ROM disk to monitor the number of sectors waiting to be transferred and prevent data overflow or data zero
The writing of data to the buffer memory is controlled.

[0055]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a CD-ROM according to an embodiment of the present invention.
It is a block diagram of a ROM disk reproducing apparatus. The same parts as those of the conventional embodiment are designated by the same reference numerals, and the description thereof will be omitted. Different parts will be described. In this device, the characteristic switching circuit is omitted in the high frequency amplifier 5. The characteristic switching circuit is also omitted in the bit synchronous clock generation PLL circuit 16. Further, only the oscillation circuit 36 using the crystal oscillator is provided, and the oscillation circuit 35 and the master clock selection circuit 39, which are further provided in the conventional device, are omitted.

In the figure, 100 is newly provided, which is a sector clock generation circuit for generating a pulse signal having a repetition period equal to the sector period at a specified linear velocity.

FIG. 2 shows the detailed circuit configuration of the sector clock generation circuit 100.

The clock generation circuit 100 has a frequency of 176.4 kHz supplied from the digital signal processing circuit 24.
Pre-counter 10 with S _LRCX of z as master clock
1/392 is generated to generate a clock signal S _EN having a frequency of 450 Hz, and the S _EN signal is used as a clock enable signal for the 3-bit programmable frequency divider 101. The master clock of the 3-bit programmable frequency divider 102 is the S _LRCX signal like the pre-counter 101, and the content is incremented at the rising _edge of the S _LRCK signal every time the S _EN signal becomes “H”.

When the content reaches 111b and the S _EN signal becomes "H", the I / O port signals S _PA , S _PB and S
_The 3-bit preset value set by the _PC is reloaded and incremented each time the S _EN signal becomes “H”.
Carry output S of 3-bit programmable frequency divider 102
_CO becomes one input signal of the 2-input AND gate 104. The other input of the 2-input AND gate 104 becomes the S _EN signal, and the NAND operation output is supplied to the load terminal of the 3-bit programmable frequency divider 102. Normally, the S _CL signal is at “L” level, and this signal causes the pre-counter 1
The content of 01 is all zeros, and the content of the 3-bit program counter 102 is 111b.
An initial value 010b set by S _PA , S _PB and S _PC is given to the preload terminals A, B and C of the 3-bit programmable frequency divider 102.

Reference numeral 105 is a D flip-flop, and Q
The terminal output signals S _INT and S _CO signals are 2-input OR circuits 10
The OR operation is performed by 6 and the result becomes the D terminal input, and the S _INT signal line is connected to the CPU 52. The output of the 2-input AND gate 107 is connected to the CL terminal of the D flip-flop 105, and the 2-input AND gate 1
The contents are cleared by either the I / O port signal S _CLR or S _INTAK signal which is the input signal of 07.

FIG. 3 is a diagram showing the operation timing of the sector clock generation circuit 100 shown in FIGS. 1 and 2. In this diagram, the 3-bit programmable frequency divider 102 has 6
The frequency is set to divide and the frequency is 75 in 1x linear velocity mode.
A sector clock of Hz can be obtained.

The master clock S _LRCL of the sector clock generation circuit 100 is a signal having a frequency of 176.4 kHz obtained by dividing the system clock 33.4 _MHz from the oscillation circuit 36 by 192 in the digital signal processing circuit 24. .

FIG. 4 shows the operation timing of the sector clock generation corresponding to the double linear velocity, and FIG. 5 shows the operation timing of the sector clock generation corresponding to the triple linear velocity.

FIG. 6 shows the relationship between the setting values for the programmable frequency divider 102, the frequency division numbers, and the sector clock frequency, which are determined by S _PA , S _PB , and S _PC .

Quadruple linear velocity CD- according to the embodiment shown in FIG.
The operation when the ROM disc reproducing apparatus reproduces the CD-ROM disc having the data structure shown in FIG. 29A and accesses it by the computer system having the configuration shown in FIG. 29B will be described.

Immediately after the CD-ROM disc is mounted in the CD-ROM disc reproducing apparatus, the optical pickup 3 is positioned at the innermost periphery after a predetermined initial process is completed, and waits for a command from the host computer. . At this point, the rotation speed of the spindle motor controlled to have a constant 4 × linear velocity is about 2000 rpm. The host computer confirms that the CD-ROM disc player can accept commands.
It is determined by the "Status" register in 5 and the data of the track 01 is read by the "Read" command.

Next, the "Set CD-ROM Spe" shown in FIG. 32 is set in order to set the disc rotation to the designated linear velocity.
Issue the "ed" command.

When the system controller 51 receives this command, it transfers the transfer rate parameter "Dri".
"ve Speed" is converted to an instruction for determining the corresponding linear velocity and setting the sector cycle of the sector clock generation circuit 100. The relationship between the "Drive Speed" parameter and the data transfer rate and linear velocity is shown in FIG.

[0070] The preset value for 3-bit programmable frequency divider 102 by the instruction _{(S PA, S PB, S} PC) is set. After that, the normal termination of the command without any error is notified to the host computer via the "Drive Status" register and the "Error Status" register. The contents of this content are Drive Status = 40h by the system controller 51.
Error Status = 00h (no error) is set.

Next, the host computer 200 uses the CD
-"Test Unit Ready" shown in FIG. 34 for confirming the ready state of the ROM disc reproducing apparatus.
Issue the command. Upon receiving this command, the system controller 51 immediately sends "Drive Status".
The execution result of the command is notified to the host computer via the s "register and the" Error Status "register.

In the ready state, "Drive Sta"
tus = 40h, Error Status = 00h are reported.

Further, the host computer 200 uses "Mode Selec" to indicate the file number and the channel number of the CD-ROM XA sector to be transferred for each of the audio sector and the video sector.
The "t" command (shown in FIG. 7) is issued. The XA page data following the command is transferred according to the format of FIG. 8. The XA page data indicates the file number and the channel number.

Channels 0 to 15 can be designated for audio data and channels 0 to 31 can be designated for video data, and "Channel Sele" in FIG. 8 can be designated.
The channel number of audio data or video data can be designated by setting the corresponding bit number in the "action Mask" field.
Finally, the host computer 200 displays the “Re” shown in FIG.
The "ad XA" command is issued to the CD-ROM disc reproducing apparatus, and the predetermined sector length (Trans) of the CD-ROM XA sector stored in the track number = 02 is stored.
Instruct reading of “fer Length ≧ 2)”.

Upon receipt of this command, the system controller 51 in the CD-ROM disc reproducing apparatus is
Control of data reading from a specified sector on the ROM disk, digital processing of read data, buffering of processed data by the buffer memory 49, and control of data transfer from the buffer memory 49 to the host computer 200 are started.

The digitally processed sector data is temporarily stored sequentially from the lower address, with 2340 bytes excluding the sync pattern data as one block. The buffer memory 49 is managed in units of this memory block. Data writing after digital processing to the buffer memory 49 and data reading for transferring to the host computer 200 are performed by the system controller 5
It is controlled via the buffer memory controller 50 operated by 1.

FIG. 10 shows registers used by the system controller 51 for managing the buffer memory 49.

The TRCOUNT register is a register for holding the number of untransferred sectors, and when the "Read XA" command is received, the command "Transfer Length" is sent.
The data of the th "field is stored, and the content is decremented by -1 each time the sector data transfer to the host computer 200 is completed.

The TRPEND register is a register for holding the number of sectors waiting to be transferred in the buffer memory 49,
Every time 2340 bytes of sector data processed by the digital signal processing circuit 24 is written in the buffer memory 49, +
The host computer 200 is incremented by one.
The content is decremented by -1 each time the transfer to the.

The WSTADR register is a register for storing the address of the buffer memory 49 at which writing is started for buffering the sector data for which digital signal processing has been completed. Prior to the execution of the "Read XA" command, it is initialized to 000000h, and the next write start address obtained by adding 2340 is set every time data of one sector is written.

The RDSTADR register is updated each time sector data transfer to the host computer 200 is completed, and an address to start reading for the next transfer is set. Like the WSTADR register, "Read X
Prior to execution of the "A" command, it is initialized to 000000h, and its content is incremented by 2340 units.

FIG. 11 is a diagram showing the relationship between the WSTADR register and the RSTADR register and the sector data storage area of the buffer memory 49. Must be WSTAD
The address specified by the R register precedes the address specified by the RSTADR register. These registers can be written and read by the system controller 51, and are provided in the buffer memory controller 50 in this embodiment. The system controller 51 monitors the amount of data waiting for transfer in the buffer memory 49 based on the information in these registers, and controls so that the data will not overflow or become zero.

FIG. 12 shows the data structure and format of the tag area created in the SRAM 54. The tag area is subdivided into 4-byte fields, and the fields correspond to the data blocks in the buffer memory 49.
The system controller 51 is a digital signal processing circuit 24.
The header and sub-header of each sector are checked every time the sector data processed in step 1 is written in the buffer memory. It is determined whether or not the sector matches both the file number and the channel number requested by the host computer 200, and attribute information is in byte 0 of the field of the tag area, and the CD-ROM header address of the sector is in bytes 1 to 3. Store. The attribute information REQ of byte 0 is R if the data requested by the host computer 200 to be transferred.
EQ = 1, otherwise REQ = 0.

The TAGPNTR is placed at a fixed address in the SRAM 54 and indicates to the host computer 200 the start address of the corresponding tag field in the tag area in which the information regarding the sector data to be transferred is stored.

FIG. 13 is a diagram for explaining a series of processing operations of data read from a CD-ROM disc and processed by the digital signal processing circuit 24 and a disc access mode.

The host computer 200 has a CD-ROM X with the number of sectors exceeding the storage capacity of the buffer memory 49.
To read A data, use T of the "Read XA" command.
This is the operation when instructed by the "transfer Length" field.
The processing sequence of No. 1 will be described.

(1) The sector data processed by the digital signal processing circuit 24 is sequentially written into the buffer memory 49 from the head sector designated by the host computer 200. Each time the sector data is written, the TRPEND register is incremented by +1. NUM WSEC
The contents of the T register are decremented by -1. Also,
With reference to the header and sub-header of the sector, predetermined information is written in the tag field.

(2) Data transfer to the host computer 200 is started at the time when the writing of the first sector is completed. The contents of the TRPEND register and the TRCONT register are decremented by -1 each time the host transfer ends. After that, the data transfer to the host computer 200 is repeated at a cycle of about 1/75 second.

(3) The sector of the TRPEND register indicating the number of sectors waiting to be transferred in the buffer memory 49 has reached the maximum number of sectors (S _max ) that can be buffered, and has the sector data number specified by "Transfer Length". If data buffering is not completed, read data from the next sector address,
Suspend digital data processing and buffering.

(4) Continue seeking the sector of the next read target address by one track kick. Meanwhile, W
The STADR register holds a buffer memory address at which writing is started when buffering is resumed. During this period, the position of the optical pickup 3 is calculated based on the header address, and the rotation waiting time T _w is calculated.

(5) It is detected that the minimum number of transfer waiting sectors has been reached. Before the disk access for restarting the buffering suspended in the full state of the buffer memory 49 is started, the minimum transfer waiting sector number held in the buffer memory 49 is calculated. This is the number of retries (N)
The one-track kick time t of the optical pickup 3, the maximum time τ from the end of the one-track kick of the optical pickup 3 to the time when the header address to the sector arranged before the read start sector can be read, and the reading restart The maximum rotation waiting time T _{w at the} optical pickup position,
It is calculated in advance from the sector cycle T _k at the k times linear velocity. The minimum number of sectors waiting for transfer is S _min = [Nx (t + τ + T _w ) / T _k ] +1. Normally N = 5, t = 2 msec, τ = 7 ms
ec is set. T _w is a function of the optical pickup position 3, and S _min is also a function of the optical pickup 3 position. S _min is small on the inner circumference and increases as it moves to the outer circumference.

(6) Next, in order to search for a sector to be written in the buffer memory, one-track kick, waiting for rotation, or retry is executed when the target address cannot be searched. 14 and 15 show a flow at the start of buffering including a retry.

(7) When the target sector is detected, the read operation is restarted.

(8) New sector data is sequentially written in the buffer memory 49.

(9) Detecting that the number of transfer waiting sectors in the buffer memory 49 has reached S _max , the data writing is interrupted.

(10) The seek of the sector of the next read target address by the one-track kick is continued. The same operation as (4) is performed.

(11) It is detected that the minimum transfer waiting sector number S _min has been reached.

(12) The sector of the next read target address is searched by the one-track kick.

(13) As a result of the sector search of the read target address, if the number of retries increases, it takes time until the read is restarted, and the number of transfer waiting sectors decreases.

(14) New sector data is sequentially written in the buffer memory 49.

In (15) to (20), the same processing as before is repeated.

(21) When it is detected that the content of the NUM WSECT register becomes zero, the writing is stopped.

(22) The seek of the last sector is continued by the one-track kick, and the idling state is entered.

(23) Host data transfer continues, TR
When it is detected that the contents of the COUNT register have become zero, the execution of the "Read XA" command is terminated,
The execution status is reported to the host computer 200.

FIG. 16 shows (1) in FIGS. 14 and 15.
It is a figure explaining the detail of the operation timing of- (3).
The audio sector in which the compressed audio data of the CD-ROM XA ADPCM level B stereo in the track 02 is stored is arranged at an interleave ratio of 3: 1, and is convenient for the sector read from the CD-ROM disc. , Sector numbers are 0, 1, 2, ..., i-
1, i, i + 1, ... Where sectors 0, 4,
4, 12, ..., 4 * (s-1), ... are ADPCM audio sectors, sectors 7, 10 are text data sectors,
The other is the video data sector. The host computer does not specify only the text data sector as the data to be transferred. The data is written in the buffer memory 49 as shown in FIG. The figure also shows the data of the tag area holding the information about the sector data written in the buffer memory 49 () is shown in FIG.
It corresponds to the sector number in No. 6.

FIG. 18 is a diagram for explaining the flow of data transfer processing for the host computer 200.

Hereinafter, the host computer 200 will be described with reference to FIGS. 14, 15, 16, 17, and 18.
The transfer processing of the system controller 51 at the time of data transfer to will be sequentially described.

(1) Initialize the buffer memory controller 50 and the host interface controller 55 for host transfer.

(2) If the first sector data is written in the buffer memory 49, S is generated to start the generation of the sector clock by the sector clock generation circuit 100.
Change _CLR from "L" to "H". This produces the first S _INT signal approximately 1/450 seconds later.

[0110] (3) immediately S _INT signal if it detects an interruption by S _INT signal = "H" to clear the S _INTAK signal.

(4) The tag field address is obtained by referring to the TAGPNTR register.

(5) Information regarding the sector data in the buffer memory 49 is acquired by referring to the tag field.

(6) Byte Count (H / L) as follows according to the value of the REQ bit of the attribute field
Set the transfer length in the register.

If REQ = 1, Byte Count
(H / L) = 2340 If REQ = 0, Byte Count (H / L) = 1
2 For the sector data corresponding to sector numbers 6 and 10, REQ = 0 is specified so that the buffer write processing routine transfers a total of 12 bytes of "Header" and "Subheader".

(7) Referring to the contents of the RSTADR register, the buffer memory controller 50 sets the buffer memory read start address and the read stop address, and sets the read enable state.

If REQ = 0, a transfer start address and a transfer stop address = transfer start address + 11 are set in the buffer memory 49. Further, the transfer start address and the transfer stop address = transfer start address + 2339 are set in order to execute the transfer of 2340 bytes to the sectors other than the text data sector.

(8) In order to permit the data transfer to the host computer 200, "Drive Status
A predetermined value is set in the "s" register and the "Bus Phase" register.

(9) Host interrupt signal _SHINT is "H"
Assert to.

The host computer 200 displays "Stat
The interrupt factor is determined by referring to the "us" register and the "Bus Phase" register.
_SHINT is negated by reading the register.

The host computer 200 displays "Dat
The sector data in the buffer memory 49 is read out by PIO (programmable IO transfer) for the number of bytes designated according to the contents of the Byte (Count (H / L) register via the a "register.

When the specified number of bytes have been read, the read access is temporarily stopped and the next transfer interrupt process is set up.

(10): While the host computer 200 is reading data, other processing such as writing sector data to the buffer memory 49 is performed until the buffer memory controller 50 reports the detection of the read end address. Run.

(11) When the end of transfer of 1 sector worth of data or 12 bytes of header / subheader is detected, the TRCOUNT register is decremented by -1.

(12) RSTAD is set as the buffer memory address for starting data reading for the next host transfer.
Write to R register.

(13) Update the contents of the TAGPNTR register holding the address of the tag field to be referred to in the next host transfer.

(14) Whenever an interrupt is generated from the sector clock generation circuit 100, the processing of (3) to (13) is repeated and TRCOUNT = 0, and when the transfer processing of the last sector to the host computer 200 is completed, S
_{CLR is set} to "L" to stop the sector clock generation by the sector clock generation circuit 100.

(15) Report the command execution star to the host computer 200.

As described above, with the rotation control mode of the spindle motor 2 fixed at the 4 × linear velocity, the CD-ROM XA ADPCM audio sector for interleaved recording of the CD-ROM XA ADPCM audio sector, which is assumed to be the 1 × linear velocity reproduction, 1 Data can be transferred to the host computer at a data rate equivalent to that at the time of double speed reproduction.

By managing the minimum number of sectors waiting for transfer in the buffer memory 49 according to the number of retries and the position of the optical pickup 3, the probability of abnormal termination of the application program due to a CD-ROM disc defect is significantly reduced. At the same time, the buffer memory data bus can be effectively used. That is, by assigning the data bus access right of the buffer memory 49 for data transfer to the host computer 200 to read data for host data transfer as long as possible, the host interface controller 55 causes the host computer 200 to transfer data during data transfer.
To the host computer 2 as a whole, the frequency of issuing a wait request by the IORDY signal is reduced.
00 can reduce the CPU time spent for CD-ROM data transfer.

In the above embodiment, the CD-ROM disc reproducing apparatus in which the spindle motor 2 is CLV controlled at the quadruple linear velocity is explained, but the rotation of the spindle motor 2 is CAV.
The present invention can be effectively applied to a CD-ROM disc reproducing device which is controlled and has a built-in ADPCM audio data demodulating means.

FIG. 19 shows an embodiment of a CD-ROM disc reproducing apparatus having a built-in ADPCM audio data demodulating means. CAV control system CD- of this embodiment
In the ROM disc reproducing apparatus, the digital signal processing circuit 2
4 is configured to include a CD-ROM XA type ADPCM audio demodulation circuit. In the figure, the spindle motor 2 is equipped with a frequency generator 108 on its rotating shaft as a rotation sensor.
CAV control is performed by the control unit 8. The angular velocity in the present embodiment is the innermost rotation speed 2000 in the quadruple linear velocity mode.
It is controlled to be equal to rpm.

Reference numeral 109 is a data rate detecting circuit for detecting the data rate of the read EFM data signal. The output of this detecting circuit 109 produces a bit synchronous clock P.
The center oscillation frequency of the VCO 78 in the LL 16 is controlled so as to follow the data rate. 110 is ADPC
M audio demodulation circuit, 130 is a D / A converter, 1
31 is a low pass filter, 132 is an audio amplifier,
133L and 133R are audio signal output terminals.

FIG. 20 is a diagram for explaining the configuration of the ADPCM audio demodulation circuit 110. 111 is a memory address generation circuit, 112 is a memory control signal generation circuit, 11
3 is a 3-state address output buffer, 114 is a 3-state memory control signal output buffer, 115 is an audio data processor, 116 is a D / A converter interface, 117 is a sequencer / system timing generation circuit, 118 is a system controller interface, and 119 is a control / It is a status register. The data bus of the buffer memory 49 is connected to the audio data processor 115. The operation of the ADPCM audio demodulation circuit 110 is controlled by the system controller 51 via the system controller bus.
It is controlled by accessing the status register.

The buffer memory 49 is shared by the ADPCM audio demodulator 110 and the buffer memory controller 50, and the 3-state output buffers 113 and 11 are used.
The buffer address line and the memory control lines S _OE / S _CE output from 4 are connected to the address terminal and the control signal terminal of the buffer memory 49.

The buffer memory controller 50 is ADP
When the CM audio demodulation circuit 110 is permitted to access the ADPCM audio data storage area in the buffer memory 49, the ADPCM audio demodulation circuit 110
The address signal and the memory read control signal generated by are output to the buffer memory 49. In other cases, the address signal and the memory read control signal are in a high impedance state and are separated from the buffer memory 49.

For the ADPCM audio data request from the ADPCM audio demodulation circuit 110, the buffer memory controller 50 performs access arbitration together with the buffer memory access request from another data access channel, but the handshake between them is performed by the ADPCM audio demodulation. The S _REQ signal output by the circuit 110 and the buffer memory controller 50 responding to the S _REQ signal by the instruction signal S _ACK for permitting the buffer memory access.

When the access right is given to the ADPCM audio demodulation circuit 110, the memory bus from the buffer memory controller 50 to the buffer memory 49 becomes the 3-state state, and the audio data processor 115
Is the ADP in the buffer memory 49 indicated by hatching in FIG.
First, the coding information byte in the subheader is read from the CM sector data storage area to determine the demodulation mode.
Next, the 2304 bytes of compressed data stored in the offset addresses 12 to 2315 are sequentially read and demodulated, and digital audio data of a predetermined sample rate is output to the D / A converter 130 via the DA converter interface 116. I have to. A
The address offset corresponding to the DPCM data read start address and the interleave ratio of the audio sector is set in the memory address generation circuit 111 by the system controller 51 via the control / status register 119. The content of the address counter 111 is incremented by +1 each time one handshake ends, and when the data reading of the 2304th byte ends, the read start address and the offset data
The start address of the next area in which the audio data is stored is calculated and loaded into the address counter 111.

FIG. 22 shows an operation timing chart during data processing.

The figure shows the processing operation in the case where the compressed audio data of ADPCM level B stereo is stored and the sectors are arranged on the track with an interleave ratio of 3: 1. For the sake of convenience, sector numbers 0, 1, 2, ..., I-1, i, i + 1, ... Are assigned to the target sectors read from the CD-ROM disc. Here, sectors 0, 4, 8, ..., 4 (s-
1), ... Are ADPCM audio sectors, sector 7 is a text data sector, and others are video data sectors.
The host computer does not specify only the text data sector as the data to be transferred.

In this embodiment, the tag field is shown in FIG.
The extension shown in is performed.

In the figure, the AUD bit (bit 6) is an extension bit and indicates whether the sector data is data to be demodulated by the ADPCM audio demodulation circuit 110. That is, every time the sector data read from the disk is buffered in the buffer memory 49, the XA page data transferred from the host computer is referred to, and if the data is demodulated by the ADPCM audio demodulation circuit 110, AUD = 1 is set. Other data is AUD = 0. The sector data with AUD = 1 has REQ = 0, and only a total of 12 bytes of the header and the subheader are transferred to the host computer. Buffering, reading from the buffer memory 49 for host transfer, and host transfer processing are executed as in the first embodiment. Since the spindle motor 2 is under CAV control, the rotation waiting time T _w is constant regardless of the position of the optical pickup 3. Also, the maximum time τ from the end of one track kick until the header address of the sector located before the read start sector becomes readable is
Since the linear velocity increases as the position of the optical pickup 3 moves to the outer circumference, the outer circumference has a shorter time. Even when the spindle motor 2 is controlled to have a constant angular velocity, the minimum transfer waiting sector number can be treated as a function of the position of the optical pickup 3.

The present invention is not limited to the above embodiments, but can be modified in various ways without departing from the scope of the invention.

[0143]

As described above, according to the CD-ROM disc reproducing apparatus of the present invention, the data transfer rate is equivalent to that obtained by reading at the same linear velocity as the recording linear velocity with the disc rotation control mode fixed. Since it is possible to execute data transfer to the host computer by switching the disc rotation control mode, it becomes unnecessary for the host computer to issue a series of commands for instructing the 1x linear velocity reproduction, and then the target first CD- The time required to obtain the ROM data can be significantly shortened. Furthermore, it is not necessary to switch constants corresponding to the respective reproduction linear velocities, which makes the CD-CD less expensive.
A ROM disk reproducing device can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a sector clock generation circuit of FIG.

FIG. 3 is a timing diagram showing an operation example of the apparatus of FIG.

4 is a timing diagram showing another operation example of the apparatus of FIG.

5 is a timing chart showing still another operation example of the apparatus of FIG.

FIG. 6 is an explanatory diagram of setting data and clock frequency for the circuit of FIG.

FIG. 7 is a "Mode" for indicating the file number and the channel number of the CD-ROM XA sector to be transferred for each of the audio sector and the video sector.
The figure which shows the Select command.

FIG. 8 is a diagram showing a format of XA page data.

FIG. 9 is a diagram showing a Read XA command.

FIG. 10 shows a system controller having a buffer memory 49.
FIG. 6 is a diagram showing an example of a register used for management of the.

FIG. 11: WSTADR register and RSTADR
FIG. 3 is a diagram showing a relationship between a register and a sector data storage area of a buffer memory.

FIG. 12 is a diagram showing a data structure and format of a tag area in SRAM.

FIG. 13 is a diagram illustrating a series of data processing operations in the digital signal processing circuit and a disk access mode.

FIG. 14 is a flowchart at the start of buffering.

FIG. 15 is a view showing a continuation of the flow of FIG.

FIG. 16 is a diagram showing the timing of the operation of the device of the present invention.

FIG. 17 is a diagram showing a relationship between a data storage example in a buffer memory and a tag area.

FIG. 18 is a diagram showing a flow of data transfer processing to a host computer.

FIG. 19 is a diagram showing another embodiment of the present invention.

20 is a diagram showing the audio demodulation circuit of FIG. 19;

FIG. 21 is a diagram showing an example of an ADPCM sector data storage area in a buffer memory.

22 is an operation timing chart of the device of FIG. 19 during data processing.

FIG. 23 is a diagram showing another example of a tag field format.

FIG. 24 is a diagram showing a configuration of a conventional CD-ROM disc reproducing device.

FIG. 25 is a diagram showing in detail a part of the apparatus shown in FIG. 1;

FIG. 26 is a diagram showing a configuration of a host interface register.

FIG. 27 is a diagram showing details of a write register and a write register of a host interface register.

28 is a diagram showing the relationship between the state of a switch for switching the characteristics of each circuit shown in FIG. 25, the output clock, and the linear velocity mode.

FIG. 29 is a diagram showing a structural example of a CD-ROM disc and a structural example of the host computer.

FIG. 30 is an explanatory diagram showing a coding mode of ADPCM audio of a CD-ROM XA system.

FIG. 31 is a diagram showing a sector format of a CD-ROM mode 2 form 2 and a structure of a video sector and an audio sector in which data is stored according to this format.

FIG. 32 is a diagram showing a “Set CD-ROM Speed command”.

FIG. 33 is a diagram showing an example of specifying a data transfer rate.

FIG. 34 is a diagram showing a Test Unit Ready command.

FIG. 35 is a diagram showing a Read XA command.

FIG. 36 is a view showing a time during which the rotation speed of the spindle motor changes.

[Explanation of symbols]

1 ... Optical disc, 2 ... Spindle motor, 3 ... Optical pickup, 4 ... Pickup feed motor, 5 ... High frequency amplifier, 6 ... Characteristic switching circuit, 15 ... Waveform shaping circuit, 16
Bit synchronization clock generation PLL circuit, 24 Digital signal processing circuit, 25 Tracking error amplifier, 26
Focus error amplifier, 27 ... Digital servo processor, 28 ... CAV servo processor, 29 ... Feed servo amplifier, 30 ... Feed servo amplifier, 31 ... Focus coil drive amplifier, 32 ... Tracking coil drive amplifier, 33 ... Spindle motor drive amplifier, 36 …
Oscillation circuit, 49 ... Buffer memory, 50 ... Buffer memory controller, 52 ... CPU, 53 ... ROM, 54 ...
RAM, 55 ... Host interface controller,
100 ... Sector clock generation circuit.

Claims (7)

[Claims] 1. A spindle motor rotation control means for rotating and driving a CD-ROM disk at a speed higher than a recording linear velocity, a pickup means for reading digital data from the CD-ROM disk, and data read by the pickup means. Digital signal processing means for performing a predetermined signal processing on the buffer, buffer memory means for temporarily storing the digital data processed by the digital signal processing means, and buffer memory management means for controlling the data flow to the buffer memory means. , Host interface means for mediating data or command transfer with the host computer, and controlling the pickup means and the digital signal processing means after decoding a data read request from the host computer to read the read data. The system control means for controlling the buffer memory management means and the host interface means to store the data in the buffer memory means and to sequentially transfer the designated sectors to the host computer, and the program is set by the system control means. Sector clock signal generation means for generating a clock having a frequency k times the sector synchronization frequency at the recording linear velocity, and means for notifying the system control means as timing information every time the sector clock signal generation means generates clock. A CD-ROM disc reproducing device characterized by having. 2. The system control means, when executing a k times linear velocity read command smaller than the current linear velocity n, rotationally drives the CD-ROM disk at the current linear velocity to read data and generate the sector clock signal. 2. The CD-ROM disk according to claim 1, wherein when the data is temporarily stored in the buffer memory means in synchronization with a clock signal generated by the means, the transfer to the host computer is controlled. Playback device. 3. The spindle motor rotation control means is a linear velocity constant control means of at least m times the recording linear velocity (m> 1) or an angular velocity greater than the angular velocity at the time of innermost recording of a CD-ROM disc. C according to claim 1, characterized in that it includes any one of the means for controlling the constant angular velocity according to C.
D-ROM disc reproducing device. 4. The system control means monitors the number of sectors waiting to be transferred and temporarily stored in the buffer memory means, and controls buffering so that the data stored in the buffer memory means does not overflow or become zero. And the minimum number of transfer waiting sectors temporarily stored in the buffer memory means before restarting the disk access to restart the buffering which is temporarily stopped by the buffer full, and allows a plurality of retry and rotation waiting at the time of the access. 2. The CD-ROM disc reproducing apparatus according to claim 1, wherein the number of sectors to be set is set. 5. The system control means converts the k-times linear velocity setting instruction from the host computer into a clock generation instruction having the same cycle as the sector cycle at the k-times linear velocity by the sector clock signal generation means. 2. The CD-ROM disc reproducing apparatus according to claim 1, further comprising a step for normally ending the k-times linear velocity setting command. 6. The spindle motor rotation control means comprises a linear velocity constant control means of m times the recording linear velocity (m> 1), and means for calculating a rotation waiting time at the position of the pickup means. 5. The CD-ROM according to claim 1, wherein the rotation waiting time calculated by the means is used for setting the minimum transfer waiting sector number.
Disc player. 7. The CD-ROM disc reproducing apparatus according to claim 1, wherein the digital signal processing means includes audio data processing means.