JPH0894673A - Waveform recorder with waveform level display device - Google Patents

Abstract

PURPOSE: To confirm the level of a waveform during writing of data of the input waveform into a storing memory. CONSTITUTION: The apparatus is equipped with a maximum/minimum detection part 62 which detects maximum value data and minimum value data in an indicated number of sampled waveform data, and a register 64 for storing the maximum value data and minimum value data. Moreover, the apparatus has a waveform level display device 56 consisting of a controller 52 which reads the maximum and minimum value data from the register 64 and controls the display, a maximum/minimum control part 66 which controls the maximum/ minimum detection part 62 and register 64 and informs a detecting state to the controller 52, and a display part 54 which displays the maximum and minimum value data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform recorder for displaying waveforms of measured voltage, current, power, etc. on a screen and recording them on paper, and more particularly to a waveform level display device thereof.

[0002]

2. Description of the Related Art Conventionally, for example, when measuring and monitoring a commercial power supply voltage or a physical quantity converted into a voltage, a waveform recorder is used, and an input voltage waveform is triggered at a predetermined level.
The input waveforms captured after the trigger or before and after the trigger are displayed on the screen for a certain period of time and recorded on paper for observation. The circuit relating to the waveform display of this waveform recorder is an AMP 10, an A / D converter 12, a storage RAM (readable / writable memory) 14, a data addressing unit 16, a data writing unit 1 as shown in FIG.
8, controller 20, bus buffer 22, data storage control unit 24, display unit 26 and the like. Therefore, input an input waveform such as a commercial power supply voltage from the terminal 28 to the AMP 10,
When the voltage level of the input waveform is adjusted and then input to the AD converter 12, the level-adjusted waveform can be converted from an analog value to a digital value.

Therefore, the data storage control unit 24 causes the AM
While controlling the operations of the P10, the A / D converter 12, the data address designating unit 16, the data writing unit 18, and the bus buffer 22, the data address designating unit 16 designates the data storage address of the storage RAM 14 to write the data. The waveform data sampled at the data storage address can be written in the input section 18. When a trigger is applied due to a drop in the input waveform voltage or the like, the controller 20 reads the waveform data from the storage RAM 14 and controls the display, and the display unit 26 keeps the input waveform and the like captured after the trigger or before and after the trigger constant. It can be displayed on the screen over time. The controller 20 is CP
U (Central Processing Unit), ROM (Read Only Memory), R
It consists of AM, input / output port, bus line and so on.

In order to avoid such a data collision on the bus line during writing and reading of the waveform data, a bus buffer 22 controlled by the data storage control unit 24 is connected to the storage RAM 14 and the data writing unit 18. The bus line 32 from the controller 20 connected to the line 30 is interposed to control the opening / closing of the bus line 32. Therefore, the controller 20 can read the waveform data stored in the storage RAM 14 only when the writing to the storage RAM 14 by the data writing unit 24 is completed and the bus buffer 22 is released to the controller 20 and becomes accessible. is there. Therefore, the state of the input waveform to be measured cannot be displayed during the operation of loading the waveform data waiting for the trigger into the storage RAM 14.

[0005]

However, if the state of the input waveform cannot be displayed while waiting for the trigger, it is determined whether the trigger level or the like can be set or whether the input waveform is included. There is a problem because it can not be done. Incidentally, if the waveform data is read from the storage RAM 14 and displayed while waiting for the trigger, the waveform data cannot be written to the storage RAM 14 even if a trigger is applied during the display.

The present invention has been made by paying attention to such a conventional problem, and a waveform recording with a waveform level display device capable of confirming a waveform level even during an operation of writing input waveform data into a storage memory. The purpose is to provide a total.

[0007]

In order to achieve the above object, the waveform level recorder according to the present invention includes a waveform level adjuster 38 for adjusting the waveform level of an input waveform and an analog value of the level adjusted input waveform. To a digital value, a data storage memory 46 for storing the sampled waveform data, a data address designating unit 42 for designating a data storage address of the memory 46, and a waveform for the data storage address. A data writing section 44 for writing data, a waveform level adjuster 38 for these, an AD converter 40, a data addressing section 4
2. A data storage control unit 50 that controls each operation of the data writing unit 44.

Further, a maximum / minimum detecting section 62 for detecting maximum value data and minimum value data in a designated number of the sampled waveform data, a register 64 for storing these maximum value data and minimum value data, and its Read the maximum value data and the minimum value data from the register 64,
The controller 52 for controlling the display, the maximum / minimum detectors 62 and the registers 64 for controlling them, and the controller 5
2 is provided with a waveform level display device 56 including a maximum / minimum control unit 66 for notifying the detection state, and a display unit 54 for displaying maximum value data and minimum value data of them.

Further, a bus line 58 with a bus open / close control buffer 48 from the controller 52 is connected to a bus line 58 connecting the data writing unit 44 and the data storage memory 46, and the bus buffer 48 is connected to the data storage control unit. Controlling at 50 is preferable.

[0010]

The waveform level display device 56 constructed as described above
, The conventional waveform level adjuster 38, AD
Converter 40, data storage memory 46, data address designation unit 42, data writing unit 44, data storage control unit 5
The A-D converter 40 has a circuit configuration of 0 or the like.
The waveform data sampled by can be sequentially written in the storage memory 46.

In addition, the sampled waveform data also enters the maximum / minimum detection section 62 of the waveform level display device 56. Therefore, the maximum / minimum detection unit 62 detects the maximum value data and the minimum value data in the designated number of the sampled waveform data, stores the maximum value data and the minimum value data in the register 64, and the maximum / minimum control unit 66. The maximum / minimum detection unit 62 and the register 64 are controlled to notify the detection state to the controller 52, and when the detection end signal is received from the maximum / minimum control unit 66, the controller 52 registers the register 6
4, the maximum value data and the minimum value data are read out, the display is controlled, and the input waveform data storage memory 4
Even during the writing operation for 6, the waveform level can be displayed on the screen of the display unit 54 by the maximum value data and the minimum value data of the input waveform data.

Further, a bus line 58 having a bus opening / closing control buffer 48 from the controller 52 is connected to a bus line 58 connecting the data writing unit 44 and the data storage memory 46, and the bus buffer 48 is connected to the data storage control unit. When controlled by 50, the controller 52 and the display unit 54 can read and display the waveform data from the storage memory 46 while avoiding collision of the waveform data on the bus line 58 when writing and reading the input waveform data to and from the storage memory 46. , Maximum value data of waveform data from register 64,
It can also be used for reading and displaying the minimum value data.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration of a waveform display circuit section of a waveform recorder with a waveform level display device to which the present invention is applied. In the figure, 34 is the waveform display circuit section of the waveform recorder with a waveform level display device, 36 is its input terminal, and 38 is AMP.
(Amplifier), 40 A-D converter, 42 data addressing unit, 44 data writing unit, 46 storage RAM, 48 bus buffer, 50 data storage control unit, 52 controller, 54 display unit , 56 are waveform level display devices. The AMP 38 is a waveform level adjuster for amplifying or attenuating the voltage level of the input waveform such as the commercial power supply voltage which is input to the terminal 36. Therefore, A
The level-adjusted input waveform is input to the AD converter 40 connected to the MP38. Then, the AD converter 40 converts the level-adjusted input waveform from an analog value to a digital value.

The sampled waveform data (digital conversion data) enters the data writing section 44 and the waveform level display device 56. Therefore, the waveform data is stored in the storage RAM.
In order to store the data in 46, the data address designating section 42 designates the data storage address of the storage RAM 46, and the data writing section 44 writes the waveform data to the data storage address. At that time, the data storage control unit 50 causes the AMP3
8, A-D converter 40, data addressing unit 4
2. Control each operation of the data writing unit 44 and the bus buffer 48. The bus buffer 48 is the bus line 5 that connects the data writing unit 44 and the storage RAM 46 in the conventional manner.
8 is connected to the bus line 60 from the controller 52 and is connected to the controller 52 and the data writing unit 44.
The bus line 60 is controlled to open and close in order to prevent the data from (1) from colliding with the bus line.

Storage RAM for such waveform data
The same waveform data always enters the waveform level display device 56 during the writing operation to the 46. The display unit 54 and the like are included. Then, the number specified by the maximum / minimum detection unit 62 (for example, the number of waveform data captured in 10 seconds)
The maximum value data and the minimum value data of each waveform data are detected. At that time, compare the waveform data that was previously captured with the waveform data that was captured this time, and if the maximum value, leave the larger data and compare the remaining waveform data with the waveform data that is captured next time However, if the minimum value is left, the smaller data is left, the remaining waveform data is compared with the waveform data that was captured next time, and the smaller data is left in sequence. To do. The data address specifying unit 42, the data writing unit 44, the data storage control unit 50, and the maximum / minimum detecting unit 6
2. The maximum / minimum control unit 66 and the like use ICs (integrated circuits) made exclusively, or are made by combining general-purpose ICs.

These maximum value data and minimum value data are transferred to and stored in the register 64. Then, the maximum / minimum control unit 66 controls the maximum / minimum detection unit 62 and the register 64,
Further, it notifies the controller 52, which also controls the reading and the display of the maximum value data and the minimum value data from the register 64, of the detection of the maximum value data and the minimum value data and the end of the detection of the designated number. At this time, if the designated number of waveform data is set to a large number, the stored contents (maximum value data, minimum value data) of the register 64 remain the same as the previously stored contents until the specified number of waveform data are fetched.
When the CPU included in 2 performs a read operation, the stored content of the register 64 changes very slowly. Therefore, A
-The CPU is sufficient for the register 64 regardless of the conversion speed of the D converter 40 (waveform data storage speed).
Maximum value data and minimum value data can be read from. In addition,
The controller 52 is an arithmetic and control unit such as a microcomputer, and includes a CPU, ROM, RAM, input / output ports, bus lines, etc., and performs not only display but all controls such as a data storage control unit 50 and a maximum / minimum control unit. 6
It also controls 6th grade.

Therefore, the maximum value data and the minimum value data of the waveform data are displayed on the screen of the CRT display or the like provided in the display section 54 as shown in FIG. 2, and the width between the maximum value data (MAX) and the minimum value data (MIN) is set. , Or the waveform of the maximum value data and the minimum value data as shown in FIG. 3, or the value itself of the maximum value data and the minimum value data is displayed in characters, and the waveform level is displayed. Therefore, the observer can perform observation while confirming the level of the measured input waveform even while the waveform data waiting for the trigger is being written in the storage RAM 46. When a trigger is applied, the A / D converter 40 is set after a set time, for example, 5 minutes.
After the waveform data has been captured, the signal is input from the data storage control unit 50 to the bus buffer 48. For this reason,
The CPU included in the controller 52 can read the waveform data from the storage RAM 46 via the bus buffer 48, and the waveform data captured after the trigger or before and after the trigger can be displayed on the screen of the display unit 54.

[0018]

According to the present invention described above, claim 1
Then, during the writing operation of the sampled waveform data to the data storage memory, the maximum value data and the minimum value data in the specified number of the same waveform data are displayed on the screen, and the observation can be performed while confirming the level of the input waveform.
Therefore, it is possible to continue the observation without having to worry about whether the setting is made while waiting for the trigger, whether the waveform is included, or the like.

According to a second aspect of the present invention, by controlling the bus buffer by the data storage control unit, the controller and the display unit are separated while avoiding collision of the waveform data on the bus line when writing and reading the input waveform data to and from the storage memory. Reading display of waveform data from storage memory,
This is convenient because the maximum value data and the minimum value data of the waveform data from the register can also be read and displayed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a waveform display circuit section of a waveform recorder with a waveform level display device to which the present invention is applied.

FIG. 2 is a diagram showing the width of maximum value data and minimum value data displayed on the screen of the display unit of the waveform recorder.

FIG. 3 is a diagram showing waveforms of maximum value data and minimum value data displayed on the screen of the display unit of the waveform recorder.

FIG. 4 is a diagram showing a configuration of a waveform display circuit section of a conventional waveform recorder.

[Explanation of symbols]

34 ... Waveform display circuit unit of waveform recorder with waveform level display device 36 ... Input terminal 38 ... AMP 40 ... A / D converter 42 ... Data addressing unit 44 ... Data writing unit 46 ... Storage RAM 48 ... Bus buffer
50 ... Data storage control unit 52 ... Controller 54 ...
Display unit 56 ... Waveform level display device 58, 60 ... Bus line 62 ... Maximum / minimum detection unit 64 ... Register 66
… Maximum control unit

Claims (2)

[Claims] 1. A waveform level adjuster for adjusting the waveform level of an input waveform, an A / D converter for converting the level-adjusted input waveform from an analog value to a digital value, and data storage for storing the sampled waveform data. A memory, a data addressing section for designating a data storage address of the memory, a data writing section for writing waveform data to the data storage address, a waveform level adjuster, an AD converter, and a data addressing section for these In a waveform recorder including a data storage control unit that controls each operation of the data writing unit, a maximum / minimum detection unit that detects maximum value data and minimum value data in a specified number of the sampled waveform data, and The maximum value data and the minimum value data such as The controller that reads the data and controls the display, the maximum / minimum control unit that controls these maximum / minimum detection units and registers, and notifies the controller of the detection state, and displays the maximum value data and minimum value data A waveform recorder with a waveform level display device, comprising: a waveform level display device comprising: 2. A bus line connecting a data writing unit and a data storage memory to a bus line with a buffer for controlling bus opening / closing from a controller, and the bus buffer is controlled by the data storage control unit. A waveform recorder with a waveform level display device according to claim 1.