JPH08152867A - Device and method for controlling display - Google Patents

Abstract

PURPOSE: To provide a device and a method for controlling display capable of detecting failure of a displaying memory and a display control circuit in hardware. CONSTITUTION: A test pattern automatic generation circuit 1 automatically generating plural kinds of fixed test patterns (a) by hardware, a display memory control circuit 2 writing the fixed test pattern (a) generated by the circuit 1 in a display memory 3 and a comparison circuit 4 reading out the data before displayed and controlled (parallel-serial conversion, etc.) from the displaying memory 3 written by the circuit 2 and comparing them with the generated fixed test pattern (a) are provided, and the failure of the displaying memory 3 is detected, and an easy display memory test is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and a display control method for improving a defect detection method for display data.

[0002]

2. Description of the Related Art Conventionally, a display control device using a multiport DRAM has been provided. Further, in this device, the operation test of the display memory was performed by the CPU through the RAM port for write / read compare.

[0003]

In the above-mentioned conventional display control device, when the display data is read from the SAM port and displayed, the SAM port defect and the display data system defect are actually caused by the display device. There is only a method of displaying and visually confirming, and there is a risk of oversight.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a display control device and a display control method capable of detecting defects in a display memory and a display control circuit by hardware. To aim.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a circuit means for automatically generating several kinds of fixed test patterns by hardware and a fixed pattern generated by this circuit means. The display control device is provided with means for writing to the display memory and means for reading data from the display memory written by this means before display control (Parasili conversion, etc.) and comparing it with a fixed test pattern generated.

Further, in order to achieve the above object, the present invention provides the above-mentioned display control device, wherein by setting parameters and the like,
There is provided means for generating an arbitrary test pattern, means for writing the set test pattern in the display memory, and means for reading display data from the display memory and comparing it with the set test pattern.

Further, in order to achieve the above object, the present invention provides:
In the above display control device, there is provided a means for fetching data (Pararisiri conversion, inverted data, etc.) output to the display device, and a means for comparing the data with a test pattern.

[0008]

With the above arrangement, a defect in the display memory can be detected and a simple display memory test can be realized. or,
It is possible to realize a simple display memory test by detecting a defect in the display memory or the display control circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a test pattern automatic generation circuit, which automatically generates a fixed test pattern and transfers it to the display memory control circuit 2.

Reference numeral 2 denotes a display memory control circuit, which controls writing of test patterns to the display memory 3 and creates comparison data. A display memory 3 is a storage device for storing display data, and is a multiport RAM R.
It consists of AM and SAM.

Reference numeral 4 is a comparison circuit, which is a circuit for comparing the data output to the display control system with the comparison data to detect a defect. A P / S conversion circuit 5 performs parallel / serial conversion on display data from the display memory 3 and transfers the display data to the display device 6.

The display device 6 displays the display control data from the P / S conversion circuit 5. In the above configuration, a in the figure is fixed test data, which is data output from the test pattern automatic generation circuit 1.

Reference numeral b is memory data, which is data output from the display memory control circuit 2 to the display memory 3. c
Is comparison data, which is data output from the display memory control circuit 2.

D is display data, which is data output from the display memory 3. e is display control data,
The data is output to the display device 6. The above-mentioned configuration operates as follows.

That is, in FIG. 1, the test pattern automatic generation circuit 1 automatically generates several fixed test patterns a.
(For example, all, 0, all 1 etc.) is generated and transferred to the display memory control circuit 2. Then, the display memory control circuit 2 receives the fixed test pattern a, writes it in the display memory 3, and transfers the comparison data c (expected value) to the comparison circuit 4.

The display memory 3 transfers the memory data written from the internal RAM port to the SAM port,
The display data d is read out from the AM port and transferred to the P / S conversion circuit 5. Then, the P / S conversion circuit 5 converts the display data d transferred from the display memory 3 into the display device 6
Parallel / serial conversion so that
Transfer to the display device 6.

The comparison circuit 4 compares the display data d output from the display memory 3 with the comparison data c output from the display memory control circuit 2, detects a defect, and notifies the CPU or the like to the outside. .

FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. In FIG. 2, the same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

A CPU (central control unit) 7 controls parameters such as parameter settings. Reference numeral 11 denotes a test pattern automatic generation circuit, which generates an arbitrary test pattern aa by an internal parameter register and transfers it to the display memory control circuit 2.

In the figure, 2 to 6 are the same as in FIG. In the above configuration, f is CPU data, which is data output from the CPU 7 and including parameter data and the like.

Reference numeral aa is an arbitrary test pattern, which is data output from the test pattern automatic generation circuit 1. In the figure, b to e are the same as in FIG. The above-mentioned configuration operates as follows.

That is, in FIG. 2, the CPU 7 sets parameters for the test pattern automatic generation circuit 11. Then, in the test pattern automatic generation circuit 11, C
Based on the parameters set by the PU 7, an arbitrary test pattern aa is generated and output to the display memory control circuit 2.

The operation after the display memory control circuit 2 is the same as the operation shown in FIG. 1 described above, and the comparison circuit 4 compares the comparison data d with the display data c, detects a defect, and sends it to the outside of the CPU 7 or the like. Notice.

FIG. 3 is a block diagram showing the configuration of the third embodiment of the present invention. In FIG. 3, the same components as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted.

Reference numeral 8 denotes an S / P conversion circuit, which reads data output to the display device 6, performs serial / parallel conversion, and transfers the data to the comparison circuit 4. Reference numeral 4 is a comparison circuit, which compares the data transferred from the S / P conversion circuit 8 with the comparison data to detect a defect.

In the above structure, f is conversion data, and the S / P conversion circuit 7 serial / parallel converts the data output to the display device 8 to restore the input state of the P / S conversion circuit 5. The data.

In the figure, reference characters a to f have the same meanings as in FIG. The above-mentioned configuration operates as follows. That is, in FIG. 3, the display memory control circuit 2 outputs the comparison data c and the P / S conversion circuit 5 outputs the display control data e in the same manner as the operation of FIG.
Is output. Then, the S / P conversion circuit 8 restores the display control data e output from the P / S conversion circuit 5 to the state before being processed by the P / S conversion circuit 5, and outputs it as conversion data g to the comparison circuit 4. To do. Then, the comparison circuit 4 compares the comparison data c and the conversion data g, detects a defect, and outputs CP
This is a notification to the outside such as U.

[0028]

As described in detail above, according to the present invention, it is possible to obtain excellent effects such as preventing the defects of the display memory and the defects of the display data system from being overlooked.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a functional block diagram showing the configuration of a second embodiment of the present invention.

FIG. 3 is a functional block diagram showing the configuration of a third embodiment of the present invention.

[Explanation of symbols]

1 ... Test pattern automatic generation circuit, 2 ... Display memory control circuit, 3 ... Display memory, 4 ... Comparison circuit, 5 ... P / S conversion circuit, 6 ... Display device, 7 ... CPU, 8 ... S / P conversion circuit, 11 ... Test pattern automatic generation circuit.

Claims (6)

[Claims] 1. A fixed test pattern generating means for generating several kinds of fixed test patterns, a means for writing the fixed test pattern generated by the fixed test pattern generating means into a display memory, and a display memory written by this means. A display control device comprising: means for reading out data before display control and comparing with a generated test pattern. 2. The display control device according to claim 1, wherein an arbitrary test pattern can be generated by setting parameters and the like. 3. A means for fetching display-output data,
3. A means for comparing the data captured by this means with a test pattern is provided.
The display control device as described above. 4. A test pattern generated by generating several types of fixed test patterns, writing the generated fixed test patterns in a display memory, and reading the data before display control from the written display memory. A display control method characterized in that 5. The display control method according to claim 4, wherein an arbitrary test pattern can be generated by setting parameters and the like. 6. The display control method according to claim 4, wherein the display-outputted data is fetched, and the fetched data is compared with the test pattern.