JPH0888977A - Inverter device - Google Patents

Abstract

PURPOSE: To provide a deepened inverter device which is arranged so as to suppress the voltage fluctuation at the neutral point without detecting the terminal voltage at the neutral point of a three-level inverter. CONSTITUTION: In a three-level inverter, the required output voltage command values (Vu*, Vv*, and Vw*) of each phase are operated in every very short sampling time (Ts), and the maximum value (Vmax) and the minimum value (Vmin) and the residual middle value (Vmid) are judged, and those are operated by each formula for finding voltage vector output time (T0, T1, and T2) from the voltage value (E) half DC voltage power and the very short sampling time (Ts). And, this is provided with each such means as to get a signal which puts the switching commands (Smax1, Smid1, Smin1, Smax2, Smid2, and Smin2) to OFF, OFF, OFF, ON, ON, ON in the period T0 out of the period of the next very short sampling time, and to ON, ON, OFF, ON, ON, OFF in the period T1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-level inverter, and more particularly to an inverter device which suppresses fluctuation of the neutral point voltage of its capacitor.

[0002]

2. Description of the Related Art As a known example of a three-level inverter, Japanese Patent Publication No. 51-47848, "Inverter device", JP-A-3-
For example, Japanese Laid-Open Patent Publication No. 293971 "three-phase three-level inverter" is known. FIG. 3 shows the configuration of a three-level inverter. 1 is a DC voltage power supply, 2 is a DC reactor, 3a, 3
b is a capacitor, 4a-4d, 5a-5d, 6a-6d
Are transistors of switching elements, 7a to 7d, 8
a-8d, 9a-9d, 10a, 10b, 11a, 11b, 12
a and 12b are diodes.

In FIG. 3, two capacitors 3a and 3b having the same rating are connected in series, and their terminals P and N are connected to a DC voltage power source 1 via a DC reactor 2, and the connection points of both capacitors are connected to the middle. The sex point terminal O is derived.
In the transistors 4a to 4d, 5a to 5d, 6a to 6d, the diodes 7a to 7d, 8a to 8d, 9a to 9d are connected in anti-parallel and are connected between the terminals P and N for each phase. Between the connection point and the neutral terminal O,
As shown, the diodes 10a, 10b, 11a, 11b, 12
a and 12b are arranged. U, V, and W are output terminals of each phase derived from the intermediate connection point of each phase transistor.

Further, the operation of the three-level inverter will be described by taking the U phase as an example. Transistors 4a-4b
Table 1 shows the relationship between the switching pattern and the U-phase voltage.
Shown in However, the output voltage of the DC voltage power supply 1 is 2E, the neutral point voltage is 0 (V) with reference to the neutral point voltage, the terminal P voltage is E (V), and the terminal N voltage is -E (V). ). In this way, depending on the switching state of the transistor, the output voltage of each phase is 3 for each terminal P, N, O.
It is the value of the type.

[0005]

[Table 1]

Next, the on / off of the transistor is sequentially switched to perform control to obtain a three-phase output. In this on / off mode, there are 27 combinations of total (3 to the third power). However, some instantaneous space vectors (hereinafter simply referred to as voltage vectors) are the same, and in this sense there are a total of 19 independent voltage vectors. This is shown in Table 2. That is, Table 2 shows the relationship among the on / off modes M1 to M27, the voltage vectors V0 to V18, and the output voltages Vu, Vv, Vw of the output terminals U, V, W.

[0007]

[Table 2]

In the conventional control system of this type of three-level inverter, the voltage at the neutral terminal fluctuates according to the current supplied to the load. As a result, there is a high risk of causing an error in the output voltage and of destroying the switching element due to overvoltage. Further, in order to suppress such a defect, the capacities of the capacitors 3a and 3b have to be increased, so that the device itself of the three-level inverter becomes large.

Here, in order to solve the above-mentioned problems, the present applicant makes the neutral point voltage output time of each phase the same within a minute sample time only by selecting and switching an appropriate on / off mode, Japanese Patent Application No. 5-341925 "Inverter device" (hereinafter referred to as the previous application) in which the fluctuation of the neutral point voltage is suppressed without detecting the voltage at the neutral point terminal of the three-level inverter. ) Is proposed. This will be described with reference to FIGS. 4 and 5.

FIG. 4 is shown for explaining the control operation of the previous application, 13 is a maximum and minimum voltage command calculator, 14 to 17,
23 to 25 are adders, 18 to 20 and 26 to 28 are comparators, and 21 is a triangular wave carrier. In FIG. 4, the maximum / minimum voltage command calculator 13 receives the required output voltage command values Vu *, Vv *, Vw * for each phase for each minute sample time Ts, and outputs the output voltage finger pressure command values for each phase. It outputs the maximum value Vmax and the minimum value Vmin.

The adder 14 calculates (-E-Vmin = G1) and supplies the output G1 to the adders 15, 16 and 17. Adder 15
Calculates the voltage command value (Vu * + G1 = Vu1 *), the adder 16 calculates the voltage command value (Vv * + G1 = Vv1 *), and the adder 17 calculates the voltage command value (Vw * + G1 = Vw1 *). Are calculated and output to the comparators 18, 19 and 20, respectively. The triangular wave carrier 21 is a carrier signal Ca that changes linearly (from −E to E) or (from E to −E) during the minute sample time Ts.
Are output to the comparators 18 to 20 and the comparators 26 to 28, respectively. The comparator 18 outputs (Su1 = 1) if (Vu1 *> Ca) and outputs (Su1 = 0) if (Vu1 * ≤Ca). Similarly, the comparator 19 compares Vv1 * and Ca and outputs Sv1, and the comparator 20 compares Vw1 * and Ca and outputs Sw1.

The adder 22 calculates (E-Vmax = G2) and supplies the output G2 to the adders 23, 24 and 25. The adder 23 calculates the voltage command value (Vu * + G2 = Vu2 *), the adder 24 calculates the voltage command value (Vv * + G2 = Vv2 *), and the adder 25 calculates the voltage command value (Vw * + G2 = Vw2 *)
Are calculated and output to the comparators 26, 27 and 28, respectively. If (Vu2 ≧ Ca), the comparator 26 outputs (Su
2 = 1) is output, and if (Vu2 << Ca), then (Su2
= 0) is output. Similarly, the comparator 27
2 * and Ca are compared to obtain Sv2, and the comparator 28 has Vw
2 * and Ca are compared and Sw2 is output.

The switching commands Su1, Sv1 and Sw1 thus obtained and the switching command Su2 are obtained.
, Sv2, Sw2, the transistors of each phase are controlled as follows. That is, regarding the U phase, when (Su1 = 1), the transistor 4a is ON and the transistor 4c is OFF in FIG.
When (Su1 = 0), the transistor 4a is OFF and the transistor 4c is ON. In addition, (Su2 =
In the case of 1), the transistor 4b is ON and the transistor 4d is OFF. When (Su2 = 0), the transistor 4b is OFF and the transistor 4d is ON.
Becomes The V phase and the W phase are similar to the U phase.

FIG. 5 is shown to further explain the operating principle of FIG. 4, and (Vmax = Vu *), (Vmin
= Vv *), the change in the carrier signal and the voltage command value during control described above with respect to the time axis and the change in the actual output voltage of each phase of the inverter with respect to the time axis are respectively shown. Further, the output time of 0 (V) of the neutral point voltage of each phase and the E (V) of the voltage of the terminal P of each phase
And the output time of the voltage −E (V) of the terminal N of each phase. As shown in FIG. 5, the output voltage Vu, Vv, Vw of each phase of the inverter is the output voltage command value Vu1.
When *, Vv1 *, Vw1 * is larger than the carrier signal Ca, the voltage of E (V) is output and the output voltage command value Vu1 is output.
When *, Vv1 *, Vw1 * is smaller than the carrier signal Ca and larger than the output voltage command values Vu2 *, Vv2 *, Vw2 *, a voltage of 0 (V) is output and the voltage command value Vu2 *,
When Vv2 * and Vw2 * are smaller than the carrier signal Ca, a voltage of -E (V) is output.

The output time T of 0 (V) of the neutral point voltage of each phase within the minute time Ts of the output voltages Vu, Vv, Vw.
0 u, T0 v, and T0 w are represented by equation (1). In addition, the output time T1 u, T1 v, of the voltage E (V) at the terminal P of each phase,
T1 w is shown by the equation (2), and the voltage of the terminal N of each phase −E
The output times T2 u, T2 v, and T2 w of (V) are expressed by equation (3).

T0 u = Ts * {1- (Vu * -Vv *)} / (2E) ... (1) T0 v = Ts * {1- (Vu * -Vv *)} / (2E) T0 w = Ts.multidot. {1- (Vu * -Vv *)} / (2E)

T1 u = Ts · (Vu * −Vv *) / (2E) ··· (2) T1 v = 0 T1 w = Ts · (Vw * −Vv *) / (2E)

T2 u = 0 ... (3) T2 v = Ts. (Vu * -Vv *) / (2E) T2 w = Ts. (Vu * -Vw *) / (2E)

Therefore, the minute time Ts is calculated by the equation (1).
Output time T0 u, T0 v, T0 of the neutral point voltage of each phase in
It is shown that w is the same. Here, the average output voltage Vum, Vvm, V of each phase within the minute sampling time Ts
wm is expressed as follows.

Vum = (E · T1 u−E · T2 u) / Ts = Vu * − {(Vu * + Vv *) / 2} = Vu * − {(Vmax + Vmin) / 2} ... (4 ) Vvm = (E · T1 v−E · T2 v) / Ts = Vv * − {(Vu * + Vv *) / 2} = Vv * − {(Vmax + Vmin) / 2} Vwm = (E · T2 w−) E · T2 w) / Ts = Vw *-{(Vu * + Vv *) / 2} = Vw *-{(Vmax + Vmin) / 2}

Thus, the minute sample time Ts of each phase is
The average output voltages Vum, Vvm, Vwm in each of the output voltage command values Vu *, Vv *, Vw * of each phase are Vmax (=
Since it is a value obtained by subtracting the average value of Vu *) and Vmin (= Vv *), the line voltage of the load of the three-phase three-wire system is not affected at all, and an output equivalent to the command value can be obtained. it can.

Further, since the output times T0 u, T0 v and T0 w of the neutral point voltage of each phase within the micro sampling time Ts are the same, the currents Iu and I of each phase within the micro sampling time Ts are the same.
Ignoring ΔIu, ΔIv, and ΔIw, which are changes in v and Iw, the electric charge ΔQ accumulated at the neutral point terminal within the minute sample time Ts is given by equation (5). Where (Iu + I
Since v + Iw = 0), (ΔQ = 0). Therefore, the change ΔV of the neutral point voltage within the minute sampling time Ts
Becomes zero.

ΔQ = (Iu + Iv + Iw) · T0 u (5)

[0024]

The control of the neutral point voltage of the three-level inverter is required in view of the output characteristics, protection of the inverter itself, and especially in reducing the capacitance of the capacitor. It becomes an unavoidable task. Here, according to the control method of the previous application, the amount of change ΔIu, ΔIv, ΔI of the current of each phase within the minute sample time Ts is used.
w is not considered. In reality, however, there is a small amount of change in the current, and the neutral point voltage fluctuates due to the integration of the small current. Then, it is feared that the neutral point voltage like a direct current fluctuates with the passage of time. When the neutral point voltage fluctuates in this way, it causes an error in the output voltage or causes breakdown of the switching element due to overvoltage.

[0025]

The present invention has been made in view of the above points, and means for solving the problems are as follows. (1) A DC power supply circuit having a voltage across the DC voltage power supply and a neutral point voltage of a connection point of two capacitors connected in series to the DC voltage power supply, and a bridge type inverter circuit including three sets of unit inverters And a three-level inverter in which the first and third switching elements and the second and fourth switching elements in the unit inverter operate in a conjugate manner, respectively, (2) Necessary for each phase for every minute sampling time. Means for calculating various output voltage command values, and (3) output voltage command values Vu *, Vv for each phase
Means for discriminating the maximum value Vmax, the minimum value Vmin and the remaining intermediate value Vmid of *, Vw *,

(4) From the maximum value Vmax, the minimum value Vmin, the intermediate value Vmid, the half voltage value E of the DC voltage power source, and the minute sampling time, the voltage vector output times T0, T1
, T2 are calculated by the following equation: T0 = Ts. {2E- (Vmax-Vmin)} / (2E) T1 = Ts. (Vmid-Vmin) / (2E) T2 = Ts. (Vmax-Vmid) / (2E) Means to do

(5) Within the next minute sample time,
During the period of {0 to (T0 / 3)}, the switching command (Sma
x1, Smid1, Smin1, Smax2, Smid2, Smin2) is (O
FF, OFF, OFF, ON, ON, ON) signals, and (ON, ON, OFF, ON, ON, OFF) signals during the period of [(T0 / 3) to {(T0 / 3) + T1}] And [{(T0 / 3) + T1} to {(T0 / 3) +
T1 + (T0 / 3)}] is (OFF, OFF, O
FF, ON, ON, ON) signal, [{(T0 /
3) + T1 + (T0 / 3)} to {(T0 / 3) + T1 +
(T0 / 3) + T2}] period (ON, OFF, OF
It becomes a signal of F, ON, OFF, OFF), and [{(T0
/ 3) + T1 + (T0 / 3) + T2} to Ts] during the period of (OFF, OFF, OFF, ON, ON, ON).

(6) The output voltage command value Vu * is the maximum value V
When it is max, the switching command values Su1 and Su2 become switching commands Smax1 and Smax2, and the intermediate value Vmid
If the intermediate value is Vmid, the switching commands Smid1 and S
Mid2, when the minimum value is Vmin, the switching commands Smin1 and Smin2 become, and the V phase switching command value S
v1, Sv2 and W phase switching command value Sw1,
Sw2 also has means for obtaining the same as the switching command values Su1 and Su2, and (7) the switching command value Su of each phase.
1, Sv1 and Sw1 become the switching command of the first switching element of each phase, and the switching command values Su2,
Sv2 and Sw2 are provided with means for providing a switching command for the third switching element of each phase.

[0029]

Now, it is assumed that the output voltage command value for each phase is obtained by the means for calculating the required output voltage command values Vu *, Vv *, Vw * for each phase for each minute sampling time Ts. Further, the means for discriminating the maximum value Vmax, the minimum value Vmin and the intermediate value Vmid among the output voltage command values of the respective phases is
It is assumed that the following determination is made. When Vmax = Vu *, Vmin = Vv *, Vmid = Vw *, the maximum value Vmax, the minimum value Vmin and the intermediate value Vmi
The voltage vector output times T0, T1 and T2 are calculated from the equation (6) from the d, the half voltage value E of the DC voltage power source, and the minute sampling time Ts, by the equation (7).

T0 = Ts.multidot. {2E- (Vmax-Vmin)} / (2E) ... (6) T1 = Ts. (Vmid-Vmin) / (2E) T2 = Ts. (Vmax-Vmid) / (2E) T0 = Ts * {2E- (Vu * -Vv *)} / (2E) ... (7) T1 = Ts * (Vw * -Vv *) / (2E) T2 = Ts * (Vu * -Vw *) / (2E)

Then, within the next minute sampling time, the switching command Sma is generated in the first to fifth periods described later.
x1, Smid1, Smin1, Smax2, Smid2, Smin2 are the first
During the period, the signal (OFF, OFF, OFF, ON, ON,
ON), and signals (ON, ON, OF) during the second period.
F, ON, ON, OFF), signals (OFF, OFF, OFF, ON, ON, ON) in the third period, and signals (ON, OFF, OFF, ON, 4) in the fourth period.
OFF, OFF), and the signal (OFF, OFF,
OFF, OFF, ON, ON, ON) means,

When the output voltage command value Vu * is the maximum value Vmax, the switching command values Su1 and Su2 are the switching commands Smax1 and Smax2, and when it is the intermediate value Vmid, the switching commands Smid1 and Smid2 are the minimum value Vmax.
When it is min, the switching commands Smin1 and Smin2 are generated, and the V phase switching command values Sv1 and Sv2 and W
By means of obtaining the switching command values Sw1 and Sw2 of the phases similarly to the switching command values Su1 and Su2, the switching commands of the respective phases in the first to fifth periods are as follows.

First period 0- (T0 / 3) (Su1, Su2) = (Sv1, Sv2) = (Sw1, Sw2) = (OFF, ON) Second period (T0 / 3)-{(T0 / 3) + T1} (Su1, Su2) = (Sw1, Sw2) = (ON, ON) (Sv1, Sv2) = (OFF, OFF) Third period {(T0 / 3) + T1} to {(T0 / 3) + T1 + (T0 / 3)} (Su1, Su2) = (Sv1, Sv2) = (Sw1, Sw2) = (OFF, ON)

Fourth Period {(T0 / 3) + T1 + (T0 / 3)} to {(T0 / 3) + T1 + (T0 / 3) + T2} (Su1, Su2) = (ON, ON) (Sv1 , Sv2) = (Sw1, Sw2) = (OFF, OFF) Fifth period {(T0 / 3) + T1 + (T0 / 3) + T2} to Ts (Su1, Su2) = (Sv1, Sv2) = (Sw1) , Sw2) = (OFF, ON)

Then, the switching command values Su1, Sv
1 and Sw1 become the switching command of the first switching element of each phase, and the switching command values Su2 and Sv2
, Sw2 is a period {0 to (T0 /
3)}, the output voltage Vu, Vv, Vw of each phase is 0 (V) for the voltage at the neutral point and + E for the voltage on the + side of the DC voltage power supply.
If the voltage on the (V) -side is -E (V), the following is obtained. Vu = Vv = Vw = 0 (V) At this time, the neutral point voltage is output in all three phases, and if the load is a three-phase three-wire system, the sum of the currents in each phase is zero, and the neutral point is The current flowing through is zero.

Period [(T0 / 3) to {(T0 / 3) + T
1}], and the output voltages Vu, Vv, Vw of each phase are as follows. Vu = Vw = E (V), Vv = -E (V) At this time, since no neutral point voltage is output in all three phases, no current flows in the neutral point.

Period [{(T0 / 3) + T1} to {(T0
/ 3) + T1 + (T0 / 3)}], output voltage V of each phase
u, Vv, and Vw are as follows. Vu = Vv = Vw = 0 (V) Also at this time, no current flows to the neutral point.

Period [{(T0 / 3) + T1 + (T0 /
3)} to {(T0 / 3) + T1 + (T0 / 3) + T2
}], And the output voltages Vu, Vv, Vw of each phase are as follows. Vu = E (V), Vv = Vw = -E (V) At this time also, no current flows to the neutral point.

Period [{(T0 / 3) + T1 + (T0 /
3) + T2} to Ts], output voltage Vu, Vv, V of each phase
w is as follows. Vu = Vv = Vw = 0 (V) Also at this time, no current flows to the neutral point. Thus, it can be seen that no current flows to the neutral point in any period. That is, no current flows through the neutral point, and the voltage at the neutral point does not change.

The average output voltages Vum, Vvm, Vwm within the minute sampling time Ts of each phase are expressed by the following equation (8). That is, the average output voltages Vum, Vvm, Vwm are calculated from the output voltage command values Vu *, Vv *, Vw * by (V
It is a value obtained by subtracting the average value of (max = Vu *) and (Vmin = Vv *), and in a three-phase three-wire type load, an output equivalent to the command value can be obtained without affecting the interphase voltage. .

Vum = {E · (T1 + T2)} / Ts = (Vu * −Vv *) / 2 = Vu * − {(Vu * + Vv *) / 2} (8) Vvm = {− E * (T1 + T2)} / Ts = (Vv * -Vu *) / 2 = Vv *-{(Vu * + Vv *) / 2} Vwm = {(E * T1)-(E * T2)} / Ts = Vw *-{(Vu * + Vv * / 2}

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1 shows a main configuration of an embodiment of the present invention, in which 29 is a voltage command calculator, 30 is a voltage vector output time calculator, and 31, 32, 33 and 34 are switching command selectors. That is, the voltage command calculator 29 for discriminating between the maximum voltage command, the minimum voltage command and the intermediate voltage command has the necessary output voltage command values Vu *, V for each phase for each minute sample time Ts.
v * and Vw * are input, and the maximum value Vmax, the minimum value Vmin, and the remaining intermediate value Vmid of the output voltage command values for each phase are input.
Is output.

The voltage vector output time calculator 30 receives the maximum value Vmax, the minimum value Vmin, the intermediate value Vmid, the half voltage value E of the DC voltage source and the minute sampling time Ts, and outputs the voltage vector output time T0, T1 and T2 are obtained from equation (6) and output. The switching command selector 31 that generates a pulse output has a voltage vector output time T0,
Input T1 and T2 to input switching commands Smax1 and Smid
1, Smin1, Smax2, Smid2, and Smin2 are output as follows within the period (0 to Ts) of the next minute sample time.

Period {0 to (T0 / 3)} Smax1 = OFF, Smid1 = OFF, Smin1 = OFF Smax2 = ON, Smid2 = ON, Smin2 = ON Period [(T0 / 3) to {(T0 / 3) + T1 }] Smax1 = ON, Smid1 = ON, Smin1 = OFF Smax2 = ON, Smid2 = ON, Smin2 = OFF period [{(T0 / 3) + T1}-{(T0 / 3) + T1 + (T0 / 3)}] Smax1 = OFF, Smid1 = OFF, Smin1 = OFF Smax2 = ON, Smid2 = ON, Smin2 = ON

Period [{(T0 / 3) + T1 + (T0 / 3)} to {(T0 / 3) + T1 + (T0 / 3) + T2}] Smax1 = ON, Smid1 = OFF, Smin1 = OFF Smax2 = ON , Smid2 = OFF, Smin2 = OFF period [{(T0 / 3) + T1 + (T0 / 3) + T2} -Ts] Smax1 = OFF, Smid1 = OFF, Smin1 = OFF Smax2 = ON, Smid2 = ON, Smin2 = ON

The switching command selector 32 has a maximum value Vmax, a minimum value Vmin and an intermediate value Vmid of the U-phase output voltage command value Vu * and the above-mentioned output voltage command values of the respective phases, and switching commands Smax1, Smid1, Smin1, Smax2, Smid
2 and Smin2 are input, and the U-phase switching command values Su1 and Su2 are selected and output under the following conditions. When (Vu * = Vmax) (Su1, Su2) = (Smax1, Smax2) (Vu * = Vmid) (Su1, Su2) = (Smid1, Smid2) (Vu * = Vmin) (Su1, Su2) ) = (Smin1, Smin2)

The switching command selector 33 and the switching command selector 34 are provided for the V-phase and W-phase output voltage command values Vv.
*, Vw * and the maximum value Vmax, the minimum value Vmin and the intermediate value Vmid of the output voltage command values of each phase described above and the switching commands Smax1, Smid1, Smin1, Smax2, Smid2, Smi.
n2 and the switching command selector 32, respectively, to input V2 switching command values Sv1, Sv2 and W.
The phase switching command values Sw1 and Sw2 are determined and output.

The switching command values Su1, Su2, Sv1, Sv2, Sw1, S for each phase thus obtained are
The transistor of each phase is controlled by w2. This will be described with an example of the U phase. When (Su1 = 1), the transistor 4a is ON and the transistor 4c is OFF.
Becomes When (Su1 = 0), the transistor 4a is OFF and the transistor 4c is ON. Also,
When (Su2 = 1), the transistor 4b is ON and the transistor 4d is OFF. When (Su2 = 0), the transistor 4b is OFF and the transistor 4d is ON. The V phase and the W phase are similar to the U phase.

Further, FIG. 2 shows the operating principle of FIG. 1, in which (Vmax = Vu *), (Vmin = Vv *).
When the above-mentioned control is performed in the case of
Shows the changes of the output voltages Vu, Vv, Vw of the respective phases that are actually output during the minute sample time Ts with respect to the time axis. That is, the voltage vector output times shown in FIG. 2 are given by the following equation (9).

T0 = Ts · {2E− (Vmax−Vmin)} / (2E) = Ts · {2E− (Vu * −Vv *)} / (2E) ... (9) T1 = Ts · ( Vmid-Vmin) / (2E) = Ts. (Vw * -Vv *) / (2E) T2 = Ts. (Vmax-Vmid) / (2E) Ts. (Vu * -Vw *) / (2E)

As can be seen from FIG. 2, the output voltage Vu, Vv, V of each phase for the period {0 to (T0 / 3)}.
w is as follows, where the voltage at the neutral point is 0 (V), the voltage on the + side of the DC voltage power supply is E (V), and the voltage on the − side is −E (V). Vu = Vv = Vw = 0 (V) At this time, the neutral point voltage is output in all three phases, and the three phases are 3
In the case of a linear load, the sum of the currents of the respective phases is 0, and the current flowing at the neutral point is 0. Period [(T0 / 3) ~
{(T0 / 3) + T1}], output voltages Vu, Vv, Vw
Is as follows. Vu = Vw = E (V), Vv = -E (V) At this time, since no neutral point voltage is output in all three phases, no current flows in the neutral point.

Period [{(T0 / 3) + T1} to {(T0
/ 3) + T1 + (T0 / 3)}], output voltage Vu, V
v and Vw are as follows. Vu = Vv = Vw = 0 (V) Also at this time, no current flows to the neutral point. Period [{(T0 /
3) + T1 + (T0 / 3)} to {(T0 / 3) + T1 +
(T0 / 3) + T2}], output voltages Vu, Vv, Vw
Is as follows. Vu = E (V), Vv = Vw = -E (V) At this time also, no current flows to the neutral point. Period [{(T0 /
3) + T1 + (T0 / 3) + T2} to Ts] and the output voltages Vu, Vv, Vw are as follows. Vu = Vv = Vw = 0 (V) Also at this time, no current flows to the neutral point. Therefore, it is understood that the current does not flow to the neutral point in any period. Therefore, since the current does not flow to the neutral point, the voltage at the neutral point does not change.

Further, the average output voltages Vum, Vvm, Vwm within the minute sampling time Ts are expressed by the equation (8).
Therefore, in a three-phase three-wire type load, it is possible to obtain an output equivalent to the command value without affecting the line voltage.

[0054]

As described above, according to the present invention, there is provided a deepened inverter device in which the fluctuation of the neutral point voltage is significantly suppressed without detecting the voltage of the neutral point terminal. it can.

[Brief description of drawings]

FIG. 1 is a system diagram showing a main part configuration of an embodiment of the present invention.

FIG. 2 is a waveform diagram shown for explaining the operation principle of FIG.

FIG. 3 is a circuit diagram showing a configuration of a 3-level inverter.

FIG. 4 is a system diagram shown for explaining a control example of the previous application by the applicant.

5 is a waveform diagram shown for explaining the operation principle of FIG. 4;

[Explanation of symbols]

 1 DC voltage power supply 2 DC reactor 3a capacitor 3b capacitor 4a transistor 4b transistor 4c transistor 4d transistor 7a diode 7b diode 7c diode 7d diode 10a diode 10b diode 13 maximum / minimum voltage command calculator 14 adder 18 comparator 21 triangular wave carrier 29 voltage command calculation Unit 30 Voltage vector output time calculator 31 Switching command calculator 32 Switching command calculator 33 Switching command calculator 34 Switching command calculator

Claims (1)

[Claims] 1. A DC power supply circuit having a voltage across a DC voltage power supply and a neutral point voltage of a connection point of two capacitors connected in series to the DC voltage power supply, and a U-phase, V-phase and W-phase Three
A bridge-type inverter circuit including a set of unit inverters, and a first inverter in the unit inverters.
In the inverter device in which the third and third switching elements and the second and fourth switching elements operate in a conjugate manner, means for calculating a necessary output voltage command value for each phase for each minute sample time (Ts), and The maximum value (Vma) of the output voltage command values (Vu *, Vv *, Vw *) of each phase
x), the minimum value (Vmin) and the remaining intermediate value (Vmid), and the voltage vector output time (T0) from the judgment value, the half voltage value (E) of the DC voltage power supply and the minute sampling time. , T1 and T2) respectively, T0 = Ts. {2E- (Vmax-Vmin)} / (2E) T1 = Ts. (Vmid-Vmin) / (2E) T2 = Ts. (Vmax-Vmid) / 2 (2E) ) And a switching command (Smax1, Smid1,) during the next minute sample time period (0 to Ts).
Smin1, Smax2, Smid2, Smin2,) are means for changing from the first signal to the fifth signal in the first to fifth periods, and the output voltage command value (Vu *) of each phase is the maximum value. The switching command value (Su1, Su2) becomes the switching command (Smax1, Smax2), and the switching command value (Smid1, Smid2) when the intermediate value.
And the switching command (Smi
n1, Smin2) and the switching command value (S
u1) is a command for the first switching element of the U phase and the switching command value (Su2) is a command for the third switching element, and an inverter device is provided.