JPH0888657A - Digital orthogonal modulation circuit - Google Patents

Abstract

PURPOSE: To reduce the circuit scale by eliminating the need for two multipliers for I, Q phases requiring a large circuit scale having been needed for a conventional circuit so as to suppress the increase in the capacity of a waveform generating memory. CONSTITUTION: The polarity of I phase data stored tentatively in a shift register 1 are inverted by a polarity inverter 3 based on an I phase rectangular carrier clock and a band limit waveform stored in advance in a waveform generating memory 4 is read by using the output of the inverter 3 as an address. The polarity of Q phase data stored tentatively in a shift register 5 are inverted by a polarity inverter 7 based on a Q phase rectangular carrier clock whose phase differs from the I phase rectangular carrier clock by 90 deg. and a band limit waveform stored in advance in a waveform generating memory 8 is read by using the output of the inverter 7 as an address. The generated waveform (i) for I phase and the generated waveform (q) for Q phase read from the two waveform generating memories 4, 8 are added by an adder 9, from which an output is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature modulation circuit used in a digital communication device, for example, BS.
PK (Binary Phase Shift Keying) and QPSK (Quad
rature PhaseShift Keying) and other improvements to the digital quadrature modulation circuit applied to multi-level modulation.

[0002]

2. Description of the Related Art FIG. 1 shows, for example, BPSK or QPSK.
FIG. 3 is a configuration example diagram of a conventional technique often used as a digital quadrature modulation circuit of FIG. In the figure, binary (0, 1) digital data I and Q of an in-phase component and a quadrature component are input to shift registers 11 and 14, respectively, and band-limited waveform data is output from waveform generation memories 12 and 15 using the outputs thereof as addresses. Read out, carrier wave cos ω in multipliers 13 and 16
After multiplying t and sin ωt respectively, both are added by the adder 17 and output. FIG. 2 is a conceptual diagram of each of the conventional techniques of the waveform generation memories 12 and 15 of FIG. Quadrature modulation is the in-phase component of the transmitted signal,
This is a method of modulating the orthogonal components by multiplying them by cos ωt and sin ωt, respectively, and the transmitted modulated wave s (t) is represented by the following equation.

S (t) = Ai (t) cos ωt + Aq (t) sin ωt where Ai (t) is the in-phase component of the band-limited transmission information and Aq (t) is the band-limited transmission information. It is an orthogonal component.

In FIG. 2, 20 is a K-bit shift register, 21 is a waveform generation memory, and 22 is an address switching scanner. In the conventional configuration, the input binary value (0, 1)
The digital data (I, Q) of 1 is stored in the K-bit shift register 20 as the length of the K symbol length, and this is input as the address of the waveform generation memory 21 in which the band-limited waveform is stored. Each time the K-bit shift register shifts by 1 bit, an output having N data per symbol output from the waveform generation memory 21 is scanned by the address switching scanner 22 to obtain a band-limited generated waveform. The output (Ai (t), A
After multiplying q (t)) by the carrier waves in the multipliers 13 and 16, respectively, the quadrature modulated wave is obtained by adding the in-phase component and the quadrature component in the adder 17.

[0004]

However, in the above-mentioned conventional configuration, two multipliers are required to put the I and Q signals on the carrier wave, and the scale of the multiplication circuit is generally larger than that of the adder. Is disadvantageous when considering.
There is also a method of storing the quadrature modulation waveform in the waveform generation memory in advance for the purpose of not using the multiplier, but it has a drawback that the memory capacity is significantly increased.

An object of the present invention is to eliminate the use of two multipliers required in the conventional circuit, and
An object of the present invention is to provide a digital quadrature modulation circuit in which the circuit scale is reduced without increasing the memory capacity of the waveform generation memory.

[0006]

A digital quadrature modulation circuit according to the present invention includes a first shift register for holding a value of an input signal of an in-phase component for a certain period of time, and a rectangular carrier clock sgn having a carrier frequency for the in-phase component. [cos ωt] (however, sgn x
= 1 (x≥0), -1 (x <0), and a rectangular carrier clock output from the first carrier clock generator at the output of the first shift register. A first polarity reversing device for reversing the polarity of
A first waveform generation memory that outputs a band-limited waveform in which the output of the polarity inverter is stored in advance as an address, a second shift register that holds the value of the input signal of the quadrature component for a certain time, and a carrier frequency And a second carrier clock generator that outputs a rectangular carrier clock sgn [sin ωt] for the quadrature component, and the polarity of the carrier clock that is output from the second carrier clock generator at the output of the second shift register. A second polarity inverter for inverting, a second waveform generation memory for outputting a band-limited waveform in which the output of the second polarity inverter is stored in advance as an address, and the first and second waveform generators. And an adder that adds the outputs of the memories and outputs a quadrature modulated wave.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 3 is a diagram showing a configuration example of a digital quadrature modulation circuit according to the present invention. In the figure, 1 is a shift register that stores the in-phase component (I) of the transmission data for a certain period of time, 2 is a carrier frequency clock generator that sends out a rectangular carrier clock for the in-phase component (I), and 3 is the in-phase component (I-phase side). The polarity inverter 4 for inverting the polarity of the signal from the shift register 1 according to the rectangular carrier clock from the carrier clock generator 2 outputs a band-limited waveform in which the output from the polarity inverter 3 is stored in advance as an address. Waveform generation memory
Is a shift register that stores the quadrature component (Q) of the transmission data for a certain period of time, 6 is a carrier frequency clock generator that sends out a rectangular carrier clock for the quadrature component (Q), and 7 is a shift register on the quadrature component side (Q phase side) A polarity inverter that performs polarity inversion according to the carrier clock from the rectangular carrier clock generator 6 with 5 signals, and 8 reads and outputs a band-limited waveform in which the output from the polarity inverter 7 is stored in advance as an address. The waveform generation memory 9 is an adder for adding the signals from the two waveform generation memories 4 and 8.

The operation of the present invention shown in FIG. 3 will be described below. The circuit according to the invention of FIG. 3 must operate equivalently at its output as the conventional digital quadrature modulator circuit of FIG. Carrier frequency clocks output from carrier frequency clock generators 2 and 6 sgn [cosωt], sgn [sinω
t] is a rectangular wave clock signal that repeats 1, 0 at the frequency ω. Here, sgn x is a function for rectangularly shaping the fluctuation of x, and is +1 when x ≧ 0 and −1 when x <0. These carrier clocks sgn [cosωt], sgn [sinω
t] can be generated by a circuit as shown in FIG. 4A, and their phases are deviated from each other by 90 ° as shown in FIG. 4C. The input signals A0 and A1 of the decoder 41 shown in FIG.
A clock signal having a frequency of 2ω and a clock signal having a frequency of ω, respectively. The output from the decoder 41 of FIG. 4 is input to the active low OR circuits 42 and 43, and the rectangular carrier wave clock signals sgn [cosωt] and sgn [sin] are input.
ωt] is obtained.

The waveform generation memories 4 and 8 are an I-axis waveform generation memory and a Q-axis waveform generation memory, respectively, and their internal operations are the same, so the I-axis waveform generation memory 4 will be described. FIG. 5 is an explanatory diagram of the internal waveform of the one waveform generation memory 4. In the waveform generating memory 4 in the middle stage, the filter shaping waveform (shaded part b) of the bit section (shaded part a) uniquely determined by the bit sequence given by the shift register 1 (the solid line in the upper part of FIG. 5) is timed. It is stored in order. Since the waveforms corresponding to all combinations of the bit sequences are stored, the shaped waveform (horizontal line portion d) of the bit (horizontal line portion c) in the sequence (the lower broken line in FIG. 5) obtained by inverting the bit sequence. Will be similarly stored. The same applies to the Q-axis waveform generation memory 8 by the bit sequence given from the shift register 2.

The in-phase component (I) of the transmission data of FIG. 3 is temporarily stored in the shift register 1, and the waveform designation address output from the shift register 1 is the carrier clock generator 2.
Are alternately inverted by the polarity inverter 3 in accordance with the rectangular carrier clock from In the waveform generation memory 4, the corresponding output waveform is designated by the input waveform designation address,
Since the scan address only counts up constantly, the negative waveform and the positive waveform in the memory are partially alternately output, and the I-phase output waveform i is as shown in FIG. In the quadrature component (Q) of the transmission data in FIG. 3, the rectangular carrier clock output from the carrier clock generator 6 is 90 °.
Since there is a phase shift, the waveform of the output q from the waveform generation memory 8 is transmitted 90 ° later than the waveform of the output i. The in-phase component output i and the quadrature component output q read from the waveform generation memories 4 and 8 are added by the adder 9. FIG. 6 shows an adder 9
The waveforms of the I-phase and the Q-phase input to are shown. The solid line in FIG. 6 represents the actual output waveform, and the broken line represents the waveform in the waveform generation memory. In the present invention, since the carrier wave is a rectangular wave, the output of the quadrature modulated wave contains a harmonic component. Therefore, although not shown, the output of the adder 9 may be passed through the D / A converter and then the harmonic component may be removed by a bandpass filter or the like.

In the above embodiments, the case of BPSK and QPSK has been described. However, it is obvious that the present invention can be applied to the case of multilevel modulation which handles multilevel sequences.

[0012]

As described above, according to the present invention,
Since a multiplier having a large circuit scale is not included, the circuit configuration is simplified and miniaturization can be realized. Further, a desired output can be obtained without increasing the memory capacity of the waveform generation memory.

[Brief description of drawings]

FIG. 1 is a diagram of a conventional digital quadrature modulation circuit.

FIG. 2 is a conceptual diagram of a waveform generation memory.

FIG. 3 is a digital quadrature modulation circuit diagram according to the present invention.

FIG. 4 is a diagram illustrating an example of a clock signal generation circuit.

FIG. 5 is a correspondence diagram between an internal waveform of a waveform generation memory and a transmission bit sequence.

FIG. 6 is an output waveform diagram of a digital quadrature modulation circuit.

[Explanation of symbols]

 1,5 Shift register 2,6 Carrier clock generator 3,7 Polarity inverter 4,8 Waveform generation memory 9 Adder 11,14 Shift register 12,15 Waveform generation memory 13,16 Multiplier 17 Adder 20 K bit shift Register 21 Waveform generation memory 22 Address switching scanner 41 Decoder 42, 43 OR circuit

Front page continued (72) Inventor Tsutomu Suda 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Kokusai Electric Inc.

Claims (1)

[Claims] 1. A first shift register for holding a value of an input signal of an in-phase component for a fixed time, and a rectangular carrier clock sg having a carrier frequency for the in-phase component.
n [cos ωt] (however, sgn x = + 1 (x ≧ 0), -1 (x
<0)), and a first polarity inverter for inverting the polarity of the rectangular carrier clock output from the first carrier clock generator at the output of the first shift register. A first waveform generation memory that outputs a band-limited waveform in which the output of the polarity inverter is stored in advance as an address; a second shift register that holds the value of the input signal of the quadrature component for a certain period of time; Rectangular carrier clock for orthogonal components sg
a second carrier clock generator that outputs n [sin ωt]; and a second polarity inversion that inverts the polarity of the carrier clock output from the second carrier clock generator at the output of the second shift register. And a second waveform generating memory for outputting a band-limited waveform in which the output of the second polarity inverter is stored in advance as an address, and the outputs of the first and second waveform generating memories are summed and orthogonalized. A digital quadrature modulation circuit including an adder that outputs a modulated wave.