JP3437282B2 - Digital quadrature modulation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature modulation circuit used in a digital communication system.
BPSK (Binary Phase Shift Keying), QPSK
The present invention relates to improvement of a digital quadrature modulation circuit applied to multi-level sequence modulation such as (QudraturePhse Shift Keying). 2. Description of the Related Art FIG. 1 shows, for example, BPSK or QPSK.
1 is a configuration example diagram of a conventional technique often used as a digital quadrature modulation circuit. In FIG. 1, binary (0, 1) digital data I and Q of an in-phase component and a quadrature component are input to shift registers 11 and 14, respectively. , And the carrier cos is
After multiplying by ωt and sin ωt, both are added by the adder 17 and output. FIG. 2 is a conceptual diagram of the related art of each of the waveform generation memories 12 and 15 of FIG. The quadrature modulation is a method of modulating the in-phase component and the quadrature component of a transmission signal by multiplying them by cos ωt and sin ωt, respectively, as represented by the following equation. It is expressed by an equation. S (t) = Ai (t) cos ωt + Aq (t) sin ωt where Ai (t) is the in-phase component of the band-limited transmission information and Aq (t) is the band-limited transmission information. It is an orthogonal component. In FIG. 2, reference numeral 20 denotes a K-bit shift register, reference numeral 21 denotes a waveform generation memory, and reference numeral 22 denotes an address switching scanner. In the conventional configuration, input binary (0, 1)
Is stored in a K-bit shift register 20 as a K symbol length, and this is input as an address of a waveform generation memory 21 storing a band-limited waveform. Each time the K-bit shift register shifts one bit, an output having N data per symbol output from the waveform generation memory 21 is scanned by the address switching scanner 22 to obtain a band-limited generated waveform. Thereby, the obtained output (Ai (t), A
q (t)) is multiplied by the carrier at multipliers 13 and 16, respectively, and then an in-phase component and a quadrature component are added at adder 17 to obtain a quadrature modulated wave. [0004] However, in the above-described conventional configuration, two multipliers are required to put each of the I and Q signals on a carrier, and the scale of the multiplication circuit is generally smaller than that of the adder. It is disadvantageous in consideration of the increase.
There is also a method in which a quadrature modulation waveform is stored in a waveform generation memory in advance for the purpose of not using a multiplier, but there is a disadvantage that the memory capacity is significantly increased. An object of the present invention is to eliminate the need for two multipliers in the conventional circuit,
It is an object of the present invention to provide a digital quadrature modulation circuit having only one waveform generation memory and having a reduced circuit scale without increasing the memory capacity. A digital quadrature modulation circuit according to the present invention comprises a first shift register for holding a value of an input signal of an in-phase component for a predetermined time, a second shift register having a carrier frequency and a second shift register for an in-phase component . a first carrier wave clock generator for outputting a rectangular carrier clock, and a second shift register that holds a certain time the value of the input signal of the quadrature component, second rectangular for the quadrature component has the carrier frequency a second carrier wave clock generator for outputting a carrier wave clock, the data and clock phase component output from said first shift register and said first carrier wave clock generator, said second shift register and said A first switch for switching and outputting quadrature component data and a clock output from a second carrier clock generator, and the in-phase output from the first switch Input data and clock of component or quadrature component
A polarity inverter for inverting the polarity of the data, and the waveform generation memory for outputting a bandlimited waveform stored in advance as the address output of the polar inverter, the waveform generating memory output
The place switching the second to sorting output to in-phase and quadrature components
A first register for storing the in-phase component output output from the second switch for a certain period of time, and a second register for storing the quadrature component output output from the second switch for a certain period of time. And an adder for adding the outputs of the first and second registers to output a quadrature modulated wave. FIG. 3 is a structural example of a digital quadrature modulation circuit according to the present invention. In the figure, reference numeral 301 denotes a shift register for storing an in-phase component (I) of transmission data for a predetermined time;
Reference numeral 2 denotes a carrier frequency clock generator for transmitting a rectangular carrier clock for the in-phase component (I); 303, a shift register for storing a quadrature component (Q) of transmission data for a predetermined time;
305 is a carrier frequency clock generator for transmitting a rectangular carrier clock for the quadrature component (Q), 305 is the output of the shift register 301 and the carrier clock generator 302 for the in-phase component (I-phase side) and the quadrature component side (Q-phase side). ) Of the shift register 303 and the output of the carrier wave clock generator 303 are 1
A switching circuit for switching every sampling time; 306, a polarity inverter for inverting the polarity of data A from the shift register output from the switching circuit 305 by the carrier clock B;
Reference numeral 307 denotes a waveform generation memory that reads and outputs a band-limited waveform stored in advance using the output from the polarity inverter 306 as an address, 308 denotes a switching circuit that switches the output read from the waveform generation memory 307, and 309 denotes a switching circuit that outputs the A register for storing the I-phase output (i) for a certain time, a register 310 for storing the Q-phase output (q) from the switching circuit 308 for a certain time, and 311 for two registers 30
9 and 310. The operation of the present invention shown in FIG. 3 will be described below. The circuit according to the invention of FIG. 3 must operate equivalently at the output of the conventional digital quadrature modulation circuit of FIG. Carrier frequency clock generator 302,3
04 sgn [cosωt], sgn
[sinωt] is a rectangular clock signal that repeats 1, 0 at the frequency ω. Here, sgn x is a function for rectangularly shaping the variation of x, and is +1 when x ≧ 0 and − when x <0.
It becomes 1. These carrier clocks sgn [cosωt], sgn
[sinωt] can be generated by a circuit as shown in FIG. 4 (a), and as shown in FIG.
° is off. The input signals A0, A of the decoder 41 of FIG.
1 is a clock signal having a frequency of 2ω and a clock signal having a frequency of ω, respectively. The output from the decoder 41 in FIG. 4 is input to the active-low OR circuits 42 and 43, and the clock signals sgn [cosωt] and sgn [sinωt] are respectively provided.
Get. As shown in FIG. 5, a waveform generation memory 307 stores a bit section (shaded area a) uniquely determined by a bit sequence (solid line in the upper part of FIG. 5) given by shift registers 301 and 302. Filter-shaped waveforms (hatched portions b) are stored in chronological order. Since the waveforms corresponding to all the combinations of the bits are stored, the shaped waveform (horizontal line portion d) of the bit (horizontal line portion c) of the sequence obtained by inverting the bit sequence (the lower dashed line in FIG. 5) is also obtained. It will be stored similarly. In the present invention,
The waveform designation address output from the shift register 301 in FIG. 3 is input to the switching circuit 305 together with the rectangular carrier clock from the carrier clock generator 302. In the polarity inverter 306, the signal from the shift register 301 alternates with the rectangular carrier clock. Is inverted. In the waveform generation memory 307, the corresponding output waveform is specified by the input waveform specification address, and the scan address only counts up constantly, so that the negative waveform and the positive waveform in the memory are partially alternated. Is output. The switching circuit 308 switches the signal read from the waveform generation memory 307 every sample time similarly to the switching circuit 305, distributes and outputs the in-phase component i and the quadrature component q, and supplies the same to the registers 309 and 310. The data temporarily stored in the register 309 and the register 310 are simultaneously output and added by the adder 311. FIG. 6 shows the I phase and Q input to the adder 311.
3 shows a phase waveform. The solid line in FIG. 6 is the actual output waveform,
The broken line represents the waveform in the waveform generation memory. In the present invention, the quadrature modulated wave output contains a harmonic component because the carrier wave is a rectangular wave. Accordingly, although not shown, the adder 311
The high-frequency component may be removed by a band-pass filter or the like after passing the output of D / A converter. In the above embodiment, the case of BPSK and QPSK has been described. However, it is apparent that the configuration of the present invention can be applied to the case of multi-level modulation that handles a multi-level sequence. As described above, according to the present invention,
Since there is no multiplier having a large circuit scale, the circuit configuration is simplified, and downsizing can be realized. Further, the number of memories can be reduced without increasing the memory capacity of the waveform generation memory.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of a conventional digital quadrature modulation circuit. FIG. 2 is a conceptual diagram of a waveform generation memory. FIG. 3 is a diagram of a digital quadrature modulation circuit according to the present invention. FIG. 4 is a method for generating a clock signal. FIG. 5 is an explanatory diagram of reading an internal waveform from a waveform generation memory. FIG. 6 is an output waveform diagram of the digital quadrature modulation circuit. [Description of Signs] 11, 14 Shift register 12, 15 Waveform generation memory 13, 16 Multiplier 17 Adder 20 K-bit shift register 21 Waveform generation memory 22 Address switching scanner 41 Decoder 42, 43 OR circuit 301, 303 Register 302 , 304 Carrier clock generator 305 Switching circuit 306 Polarity inverter 307 Waveform generation memory 308 Switching circuit 309, 310 Register 311 Adder

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tsutomu Suda 3-14-20 Higashinakano, Nakano-ku, Tokyo International Electric Company (56) References JP-A-4-318729 (JP, A) JP-A-Hei 6-69969 (JP, A) JP-A-61-214844 (JP, A) JP-A-7-273818 (JP, A) JP-A-3-132132 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claim 1] A first shift register for holding a value of an input signal of an in-phase component for a certain period of time, and a first rectangular carrier wave clock having a carrier frequency for the in-phase component. /> a first carrier wave clock generator for outputting a click, a second shift register that holds a certain time the value of the input signal of the quadrature component, second rectangular carrier for quadrature component has a carrier frequency black a second carrier clock generator for outputting a clock; an in-phase component data and clock output from the first shift register and the first carrier clock generator; and a second shifter. A first switch that switches and outputs data and a clock of the quadrature component output from the register and the second carrier clock generator; and a switch of the in- phase component or the quadrature component output from the first switch. Data A polarity inverter for inverting the polarity of the data receives the clock, and waveform generation memory for outputting a bandlimited waveform stored in advance as the address output of the polar inverter, switching it to the output of the waveform generator memory A second switch for distributing and outputting the in-phase component and the quadrature component, a first register for storing the in-phase component output output from the second switch for a predetermined time, and an output from the second switch A digital quadrature modulation circuit comprising: a second register for storing quadrature component outputs for a certain period of time; and an adder for adding the outputs of the first and second registers to output a quadrature modulated wave.