JPH0887026A - Liquid crystal display panel - Google Patents

Abstract

PURPOSE: To decrease unnecessary parasitic capacitances without lowering the opening rate of a color liquid crystal display device in delta arrangement and to prevent its display grade from degrading. CONSTITUTION: This liquid crystal display panel is provided with gate electrodes 15 in positions not overlapping on orthogonally intersecting parts 12a of data lines 12 by drawing out these electrodes to the length at which the electrodes do not arrive at the intermediate points with the adjacent gate lines in parallel with the orthogonally intersecting parts 12a of the data lines 12. The display panel is also provided with source electrodes 22 in positions not overlapping on the gate electrodes 15. Consequently, the parasitic capacitors are decreased without lowering the opening rate. Channel regions 17a of thin-film transistors (TFTs) 13 are formed by self-alignment. Consequently, the overlapping parts of the source regions 17b and gate regions 15 of the TFTs 13 on the left side and right side of the data lines 12 are made the same. Then, the parasitic capacitances Cgs between the gates and the sources are made the same and the optical characteristics are made the same as well and eventually, the degradation in the display grade is averted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel.

[0002]

2. Description of the Related Art Color liquid crystal display devices include R (red) and G
There are several types depending on the arrangement of the (green) and B (blue) color filter elements and the corresponding pixel electrodes, and one of them is a delta as shown in the schematic configuration in FIG. There is something called an array. In this color liquid crystal display device, pixel electrodes R, G, which display the same color,
The gate lines 2 connected to the scanning drive circuit 1 are linearly arranged in the left-right direction because the Bs are arranged in a zigzag pattern in the vertical direction, but the data lines 4 connected to the signal drive circuit 3 are arranged. Are pixel electrodes R, G, and B that display the same color
Are arranged so as to meander in the vertical direction so as to pass through each of the vicinity.

FIG. 3 shows a part of a concrete example of a liquid crystal display panel in such a conventional liquid crystal display device. The data line 4 has an orthogonal portion 4a orthogonal to the gate line 2 and a parallel portion 4b parallel to the gate line 2. Then, as an example, taking the pixel for R, the pixel electrode R and the thin film transistor 5 are arranged line-symmetrically alternately on the left side and the right side with respect to the adjacent orthogonal portion 4a. Each thin film transistor 5 has an extending portion 2b extending from the linear portion 2a of the gate line 2 so as to partially overlap the orthogonal portion 4a of the data line 4 as a gate electrode, and is parallel to the orthogonal portion 4a of the data line 4. The extended portion 6 extended and connected to each pixel electrode R is used as a source electrode.

[Problems to be Solved by the Invention]

By the way, in such a conventional liquid crystal display panel, the gate electrode 2b drawn out in a direction orthogonal to the gate line 2 is drawn out to the vicinity of the adjacent gate line 2, and the gate electrode 2b is almost in the longitudinal direction. The source electrode 6 is provided along the whole. As a result, the overlapping portion between the orthogonal portion 4a of the data line 4 and the gate electrode 2b and the overlapping portion between the gate electrode 2b and the source electrode 6 become large, so that the parasitic capacitance between the orthogonal portion 4a of the data line 4 and the gate electrode 2b is increased. There is also a problem that the parasitic capacitance between the gate electrode 2b and the source electrode 6 becomes large. In order to eliminate the overlapping portion between the orthogonal portion 4a of the data line 4 and the gate electrode 2b and the overlapping portion between the gate electrode 2b and the source electrode 6, it is conceivable to separate them in the left-right direction. However, there is another problem that the aperture ratio decreases. Further, since the left thin film transistor 5 and the right thin film transistor 5 are line-symmetrically arranged with the data line 4 interposed therebetween, when these thin film transistors 5 are formed in the left and right directions, although not shown, the thin film transistor 5 is not shown. Of the source region of the semiconductor thin film forming a part of the gate electrode 2b,
Left side thin film transistor 5 and right side thin film transistor 5
And will shift in different directions. Therefore, in such a case, the parasitic capacitance Cgs between the gate and source of the left thin film transistor 5 and the right thin film transistor 5 is
However, there is a problem that the display quality is deteriorated due to the difference in the optical characteristics. An object of the present invention is to provide a liquid crystal display panel that can reduce unnecessary parasitic capacitance without lowering the aperture ratio and can prevent display quality from deteriorating.

[0005]

According to the first aspect of the present invention,
Data lines arranged in a straight line in the left-right direction, a data line having an orthogonal portion orthogonal to the gate line and a parallel portion parallel to the gate line, and arranged to meander in the vertical direction, and the data line. In a liquid crystal display panel having thin film transistors alternately connected to the left side and the right side, and a pixel electrode connected to the thin film transistor, the left side thin film transistor and the right side thin film transistor are line-symmetrical across the data line. A gate electrode that is provided in a position that does not overlap the orthogonal portion of the data line and that is extended in parallel to the orthogonal portion of the data line and has a length that does not reach the midpoint between the adjacent data lines, The structure has a gate electrode and a source electrode provided at a position where it does not overlap. According to a second aspect of the invention, the channel region of the thin film transistor is formed by self-alignment.

[0006]

According to the first aspect of the invention, the gate electrode is drawn out at a position where it does not overlap the orthogonal portion of the data line and in a length parallel to the orthogonal portion of the data line and not reaching the intermediate point between the adjacent data lines. Since the source electrode is provided at a position that does not overlap the gate electrode, unnecessary parasitic capacitance can be reduced without lowering the aperture ratio. Further, according to the second aspect of the present invention, since the channel region of the thin film transistor is formed by self-alignment, the thin film transistor on the left side and the thin film transistor on the right side of the data line have the same overlapping portion between the source region and the gate electrode. Can be, therefore C
The gs is the same, the optical characteristics are the same, and it is possible to prevent the display quality from deteriorating.

[0007]

1 (A) and 1 (B) show the essential parts of a liquid crystal display panel in an embodiment of the present invention. Also in this case, the gate lines 11 are arranged in a straight line in the left-right direction because the pixel electrodes R, G, B displaying the same color are arranged in a zigzag pattern in the vertical direction in the delta arrangement. However, the data lines 12 are arranged in a meandering manner in the vertical direction so as to pass near the pixel electrodes R, G, and B displaying the same color. Therefore, the data line 12
Has an orthogonal portion 12a orthogonal to the gate line 11 and a parallel portion 12b parallel to the gate line 11. Then, taking the pixel for R as an example, the pixel electrode R and the thin film transistor 13 are arranged line-symmetrically alternately on the left side and the right side with respect to the adjacent orthogonal portion 12a.

Here, in each thin film transistor 13, a gate line is drawn out in parallel with the orthogonal portion 12a of the data line 12 as a gate electrode 15 at a position where it does not overlap with the orthogonal portion 12a of the data line 12. The length 15 is set so as not to reach the midpoint of the adjacent gate line. The source electrode 22 of each thin film transistor 13 is provided at a position where it does not overlap with the gate electrode 15.

Next, the structure of the thin film transistor 13 will be mainly described. The gate line 11 and the gate electrode 15 slightly extended from the gate line 11 in a direction orthogonal to the gate line 11 are provided at predetermined positions on the upper surface of the glass substrate 14.
Are formed. Gate line 11 and gate electrode 1
A gate insulating film 16 is formed on the upper surface of the glass substrate 14 including the glass. The semiconductor thin film 1 made of amorphous silicon, polysilicon, or the like is formed on the upper surface of the gate insulating film 16 at the gate electrode 15 and the portions corresponding to the left and right sides thereof.
7 are formed. A channel protection film 18 is formed on the upper surface of the semiconductor thin film 17 in the portion corresponding to the gate electrode 15. Ions such as phosphorus and boron are implanted using the channel protection film 18 as a mask, so that the semiconductor thin film 17 under the channel protection film 18 becomes a channel region 17a, and the left and right sides thereof are the source regions 17b.
And a drain region 17c. Semiconductor thin film 17
An interlayer insulating film 19 is formed on the upper surface of the gate insulating film 16 including the channel protective film 18. Source area 17
Contact holes 20 and 21 are formed in the interlayer insulating film 19 in a portion corresponding to b and the drain region 17c. A source electrode 222 and a drain electrode 33 are formed in the contact holes 20 and 21. The data line 12 is formed simultaneously with the formation of the electrodes 22 and 23. The source electrode 22 is connected to the pixel electrode R formed at a predetermined position on the upper surface of the interlayer insulating film 19.

In this way, each thin film transistor 13
The gate electrode 15 and the gate electrode 15 are overlapped with each other so as not to overlap the orthogonal portion 12a of the data line 12 and to a length parallel to the orthogonal portion 12a of the data line 12 so as not to reach an intermediate point between adjacent data lines. Since the structure has the source electrode 22 provided at a position not provided, the area occupied by the thin film transistor 13 can be reduced, and thus the aperture ratio can be prevented from decreasing, and unnecessary parasitic capacitance can be reduced. You can

By the way, when the channel protection film 18 of the thin film transistor 13 is formed in this liquid crystal display panel, it is formed by photolithography by backside exposure using the gate electrode 15 as a mask.
Will be self-aligned and formed. Then, when ions such as phosphorus and boron are implanted using the channel protective film 18 formed by self-alignment as a mask, the channel region 17a is formed by self-alignment. As a result, in the thin film transistor 13 on the left side and the thin film transistor 13 on the right side of the data line 12 for R, the overlapping portion of the source region 17b and the gate electrode 15 can be the same, and therefore Cgs is the same and the optical characteristics are the same. As a result, it is possible to prevent the display quality from deteriorating.

In the above embodiment, the thin film transistor 13 is a normal thin film transistor having a MOS structure, but it may be a thin film transistor having an LDD structure having a low concentration impurity implantation region between the channel region and the source and drain regions. . Also in this case, if the channel region is formed by self-alignment, the overlapping portion of the source region and the gate electrode, which are the low-concentration impurity implantation region, in the thin film transistor on the left side and the thin film transistor on the right side of the data line can be the same.

[0013]

As described above, according to the first aspect of the invention, the gate electrode is located at a position where the gate electrode does not overlap with the orthogonal portion of the data line, and in parallel with the orthogonal portion of the data line and in the middle of the adjacent data line. Since the source electrode is provided so as to extend so as not to reach the point and not overlap with the gate electrode, unnecessary parasitic capacitance can be reduced without lowering the aperture ratio. Further, according to the second aspect of the present invention, since the channel region of the thin film transistor is formed by self-alignment, the thin film transistor on the left side and the thin film transistor on the right side of the data line have the same overlapping portion between the source region and the gate electrode. Therefore, the Cgs are the same, the optical characteristics are the same, and it is possible to prevent the display quality from deteriorating.

[Brief description of drawings]

FIG. 1A is a plan view of a main part of a liquid crystal display panel according to an embodiment of the present invention, and FIG. 1B is a sectional view taken along line XX thereof.

FIG. 2 is a schematic configuration diagram of a conventional delta array color liquid crystal display device.

FIG. 3 is a partial plan view showing a specific example of a liquid crystal display panel in such a conventional color liquid crystal display device.

[Explanation of symbols]

 11 gate line 12 data line 12a orthogonal part 12b parallel part R, G, B pixel electrode 13 thin film transistor 15 gate electrode 17 semiconductor thin film 17a channel region 22 source electrode 23 drain electrode

Claims (2)

[Claims] 1. A data line having a gate line linearly arranged in the left-right direction, an orthogonal portion orthogonal to the gate line, and a parallel portion parallel to the gate line, the data line being meandering in the vertical direction. In the liquid crystal display panel having a thin film transistor alternately connected to the left side and the right side of the data line, and a pixel electrode connected to the thin film transistor, the left side thin film transistor and the right side thin film transistor are connected to the data line. It is provided so as to be line-symmetrical, and is provided at a position that does not overlap with the orthogonal portion of the data line and that is parallel to the orthogonal portion of the data line and has a length that does not reach an intermediate point between adjacent data lines. A liquid crystal display panel having a structure having a gate electrode and a source electrode provided at a position not overlapping with the gate electrode. 2. The liquid crystal display panel according to claim 1, wherein the channel region of the thin film transistor is formed by self-alignment.