JPH088652A - Frequency synthesizer of digital direct synthesization system - Google Patents

Abstract

PURPOSE:To provide a digital direct synthesis type frequency synthesizer of a simple constitution which can generate different waveforms in a short time with no discontinuation of phases. CONSTITUTION:When the waveform data which are read out in accordance with the output address received from a phase accumulator 1 are outputted, plural frequency registers 3 output different frequency data in response to such conditions that are satisfied by the output of the accumulator 1 (e.g. the conditions where a prescribed phase point is defined in a single cycle of the waveform data, the conditions where the number of waves of a waveform read out of a memory is equal to a prescribed number, etc.). Then one of these registers 3 is selected and supplied as the phase advancement degree data of the accumulator 1. Thus various waveforms and deformed waveforms are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital direct synthesis frequency synthesizer, and more particularly to a digital direct synthesis frequency synthesizer capable of synthesizing and outputting various waveforms with a simple structure.

[0002]

2. Description of the Related Art A conventional digital direct synthesis type frequency synthesizer stores necessary output waveform data in advance in a memory such as a ROM or a RAM for one cycle corresponding to an address, and stores the waveform data required for reading the waveform data from the memory. The address corresponding to the cycle is repeatedly generated from the phase accumulator.

FIG. 11 shows a block diagram of a typical configuration example of such a synthesizer. The waveform data conversion unit 2 is a memory that stores the waveform data to be output, and, for example, a ROM or RAM is used. Waveform data converter 2
The address data supplied to is generated from the phase accumulator (cumulative adder) 1. The phase accumulator 1 is composed of an adder 11 and a D-flip-flop (D-FF) 12 as an output register. One terminal A of the adder 11 receives data defining the frequency of the output data.
It is supplied from the frequency register 3 as an input register. That is, the output from the frequency register 3 is data that defines the phase advance. The output of the adder 11 is D
-Supplied to flip-flop 12. The D-flip-flop 12 is driven by a clock having a predetermined frequency, outputs the address data of the waveform data conversion unit 2, and adds the adder 1
The output from 1 is output to the waveform data conversion unit 2 and is also supplied to the other input terminal B of the adder 11.

As described above, the conventional digital direct synthesis frequency synthesizer sets the frequency of the output waveform by giving the phase accumulator 1 the amount of change in the phase for each clock (defined by the frequency register 3). Has been done. Then, the digital waveform data read from the waveform data converter 2 is converted into an analog waveform signal by a D / A converter, and then a desired waveform signal is obtained through a low pass filter.

Further, in order to obtain a desired waveform signal, the DSP as described above is used in the waveform data conversion section 2 without using the above memory.
It is also possible to obtain waveform data by means of data calculation processing by providing digital calculation means such as.

[0006]

As described above, in the conventional digital direct synthesis frequency synthesizer, the waveform data previously stored in the memory such as the ROM or the RAM is sequentially read according to the address data and converted into the analog signal. After that, a desired waveform is obtained by performing a low-pass filtering process. In such a synthesizer, the waveform obtained by reading the waveform data stored in the memory is fixed, and when it is desired to obtain another modified waveform, the waveform data stored in the memory is changed to the other modified waveform. I have to rewrite.

Alternatively, the other modified waveform is stored in another memory, and it is necessary to switch to another memory at a predetermined timing. Alternatively, it is necessary to divide one memory into a plurality of areas, store different waveform data in each divided area, and switch the areas to be read according to the required waveform.

Further, the conventional generation of different waveform data as described above causes a problem that a phase discontinuity occurs at the time of switching generation from one waveform to another waveform. For example, in FIG. 12, when the waveform is switched from the waveform W1 to the waveform W2 at the switching timing t, the waveform jumps (discontinuity) occurs at the timing t. It is also possible to sequentially rewrite the stored waveform data to other waveform data while reading the waveform data from the memory, but not only is it time-consuming to update the waveform, but it is output during the update period. There is a problem that the generated waveform becomes an irregular waveform.

Therefore, an object of the present invention is to provide a simple structure,
An object of the present invention is to provide a digital direct synthesis type frequency synthesizer capable of deforming a waveform in a short time without jumping of the waveform.

[0010]

In order to solve the above-mentioned problems, a digital direct synthesis type frequency synthesizer of the present invention is configured such that an addition output from an adder is added to address data in a waveform data generating means or memory for storing predetermined waveform data. A digital signal which outputs the waveform data read from the waveform data generating means or the memory by supplying a predetermined frequency data to the other input terminal of the adder In the direct synthesizer frequency synthesizer, a plurality of frequency registers outputting different frequency data, and an output from one frequency register of the plurality of frequency registers is selected and supplied to the other input terminal of the adder. Selecting means to determine that the output of the adder satisfies a predetermined determination condition. Constructed and a determination unit for controlling said selection means based on the discrimination result. The determination condition is that the phase point in one cycle of the waveform data stored in the waveform data generating means or the memory is a predetermined phase point, and the wave number of the waveform read from the memory is a predetermined number. The frequency data of the plurality of frequency synthesizers can be changed according to the discrimination result of the discriminator.

[0011]

In the present invention, when outputting the waveform data read according to the output address from the phase accumulator,
Corresponding to the condition that the output from the phase accumulator is satisfied (the condition that the phase point in one cycle of the waveform data becomes a predetermined phase point, the condition that the wave number of the waveform read from the memory becomes a predetermined number, etc.) By selecting one frequency register from a plurality of frequency registers that respectively output different frequency data and supplying it as phase advance data of the phase accumulator, various waveforms and modified waveforms are output.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a digital direct synthesis frequency synthesizer according to the present invention. In FIG. 1, the components designated by the same reference numerals as those in FIG. 11 have the same functions.

As described above, in the phase accumulator 1, the phase at that point and the phase advance are added for each clock, and this phase advance is proportional to the frequency of the output waveform.

In this embodiment, frequency registers 3 (1) and 3 (2) for outputting the frequencies f1 and f2, respectively, are provided, and these frequency registers 3 (1) S3 (2) are output from the phase accumulator 1 ( The output of the D-flip-flop 12) is determined, the selector 4 is switched and controlled based on the determination result, and the output of the selected frequency register is supplied to the input terminal A of the adder 11.

In this embodiment, the state to be discriminated is the phase state of the phase accumulator 1. That is, the phase of the output of the phase accumulator 1 is 0 ° or more and 1
The frequency f of the frequency register 3 (1) when the angle is less than 80 °
When 1 is 180 ° or more and less than 360 °, the frequency register 3 (2) frequency f2 is supplied to the input terminal A of the adder 11 of the phase accumulator 1. This phase state determination is “0” when the phase is 0 ° or more and less than 180 °,
MSB that becomes “1” when the angle is 180 ° or more and less than 360 °
Can be done using.

For example, in the waveform data converter 2,
Consider a case where the waveform data is converted so as to increase according to the phase when the phase is 0 ° or more and less than 180 °, and decrease when the phase is 180 ° or more and less than 360 °. The waveform data thus obtained has a triangular waveform as shown in FIG.

In FIG. 1, assuming that the frequency set in the frequency registers 3 (1) and 3 (2) is 500 Hz, as shown in FIG. 2 (a), a period of 2 ms (frequency 50
A triangular waveform of 0 Hz) is obtained. Now, the phase is 0 ° or more 1
Frequency register 3 (1) output when the angle is less than 80 °
Frequency of 333, 333 ... Hz, 180 ° or more 3
Frequency register 3 (2) output when the angle is less than 60 °
If the frequency of is set to 1 KHz, the waveform data converter 2
The rising part of the waveform output from is 1.5 ms, the falling part is 0.5 ms, and the period of the entire waveform is 1.5+
Although 0.5 = 2 ms does not change, since the time ratios of the rising portion and the falling portion of the waveform are different, a sawtooth (asymmetrical triangular wave) waveform is obtained as shown in FIG. 2B.

In the present embodiment, different waveforms (deformed waveforms) can be generated very quickly only by rewriting (updating) the frequencies set in the frequency registers 3 (1) and 3 (2). In this case, when waveform transformation is executed,
No phase discontinuity occurs.

By the way, in the waveform generation with the above configuration, a phase shift occurs depending on the switching timing of the output waveform. For example, when the frequency is switched at the timing t1 as shown in FIG. 3A, the waveform is deformed in the middle of the waveform, the cycle is changed for a moment, and the phase shift occurs. Therefore, in the embodiment of the present invention, the timing t2 at which the waveform conversion is executed is managed, and the waveform conversion is executed at the accurate timing t2 of the cycle of 2 ms. It prevents the occurrence of phase shift.

Next, the waveform data read and output from the waveform data conversion unit 2 in FIG. 1 has a phase of 0 ° to 180 °.
Consider the waveform data that is a certain constant data (for example, a positive peak value) when it is less than, and another constant data (for example, a negative peak value) when it is 180 ° or more and less than 360 °. The waveform obtained in this case is a square wave (rectangular wave, pulse wave) as shown in FIG.

In this case, if the frequencies of the two frequency registers 3 (1) and 3 (2) as shown in FIG. 1 are changed,
As shown in FIG. 4B, the duty ratio of the square wave can be changed.

The next embodiment of the present invention is an example of changing the frequencies set in the frequency registers 3 (1) and 3 (2) in the configuration of FIG. Frequency register 3
When both (1) and 3 (2) are 500 Hz, the waveform data converter 2 obtains a triangular wave as shown in FIG. Here, the frequency register 3 (1) is 50
If the frequency register 3 (2) is changed to 250 Hz while maintaining 0 Hz, the rising time of the triangular wave does not change and only the falling time thereof doubles, as shown in FIG. 5 (b).
Further, for a square wave as shown in FIG. 5C, if the set frequency is changed in the same manner, it is possible to change only the pulse period while keeping the pulse width constant. According to this embodiment, it is possible to compress or expand an arbitrary section of the waveform.

Next, another embodiment of the present invention will be described.
In this embodiment, n frequency registers 3 (1), 3 (2), 3 (3), ..., 3 (n) are provided as shown in FIG. The output is selected for each predetermined phase range of the accumulator 1 and supplied to the input terminal A of the phase accumulator 1. In this embodiment, the frequencies f1, f2, f3 and f4 are set in the frequency registers 3 (1), 3 (2), (3) and 3 (4), respectively, and the phase is 0 ° or more, 135 When the temperature is less than °, the frequency f1,135 ° of the frequency register 3 (1)
When the frequency f2 of the frequency register 3 (2) is 180 ° or more and less than 180 °, the frequency f3 of the frequency register 3 (3) is 315 ° or more, 360 ° when the frequency f3 is 180 ° or more and less than 315 °.
If the frequency f4 of the frequency register 3 (4) is less than
It is input to the accumulator 1 via the selector 4.

The phase range is discriminated by the discriminating section 5, and the selector 4 is controlled based on the discrimination result. Discrimination unit 5
Is the waveform switching timing t2 in the example of FIG.
It is also possible to adopt a configuration for determining.

Assuming a triangular wave as the waveform data, if 500 Hz is set in all the frequency registers 3 (1) to 3 (4), a triangular wave as shown in FIG. 7A is obtained. Here, 750 Hz for the frequency registers 3 (1) and 3 (3) and 25 for the frequency registers 3 (2) and 3 (4).
When 0 Hz is set, a deformed waveform as shown in FIG. 7B is obtained. In addition, the frequency registers 3 (1) and 3 (3) have a frequency of 1 kHz.
200 Hz for (2) and 500 for frequency register 3 (4)
When Hz is set, a further deformed waveform as shown in FIG. 7C is obtained. In this way, by dividing the waveform in the time axis direction and changing the frequency of each divided portion, the waveform can be variously modified.

Next, assuming a trapezoidal wave as the waveform data stored in the waveform data converter 2, the frequency f1 is 90 ° or more and 180 ° or more when the phase of the output of the phase accumulator 1 is 0 ° or more and less than 90 °. Frequency f2, 1 when less than
Frequency f3, 270 ° when 80 ° or more and less than 270 °
An embodiment will be described in which the determination unit 5 switches the selector 4 so that the frequency f4 is supplied to the phase accumulator 1 when the angle is less than 360 °.

When 500 Hz is set in all the frequency registers 3 (1) to 3 (4), as shown in FIG. 8 (a), a trapezoid having the same rise time, flat portion time, and fall time is used. The waveform is obtained. On the other hand, the frequency registers 3 (1) and 3 (3) have 500 Hz, and the frequency register 3
When 166, 66 ... Hz is set in (2) and 3 (4), a deformed trapezoidal wave as shown in FIG. 8B is obtained. In addition, the frequency register 3 (1) has 16
6,66 ... Hz, 500H in frequency register 3 (2)
When z, 1 kHz is set in the frequency register 3 (3) and 142.857 ... Hz is set in the frequency register 3 (4), a waveform as shown in FIG. 8C is obtained.

As described above, the waveform is divided into the rising portion, the flat portion 1, the falling portion, and the flat portion 2, and each of them is given an independent frequency, so that the falling edge, the falling time, the waveform period, the pulse width, etc. The parameters of can be changed freely.

Such a waveform parameter setting method is generally performed in a pulse generator. However, the pulse generator generates time in an analog manner, and cannot be as accurate as a synthesizer.

According to this method, it is possible to easily construct a high-accuracy pulse generator using a digital direct synthesis frequency synthesizer.

A further embodiment of the present invention is an example in which the discriminator 5 detects the wave number of the output waveform and switches the frequency based on the detection result.

As an example, 1.5 waves 500 Hz, 3 waves 1
Consider the case of repeating kHz. The waveform takes a sine wave as an example. In FIG. 9, the frequency is switched at 0 ° or 180 °. In this case, the waveform is not smooth at the frequency switching point. In FIG. 10, the frequency is 90 °,
Alternatively, it is switched at the point of 270 °. In this case, the waveform is smooth even at the frequency switching point. In this way, if the discriminating unit 5 has both the wave number detecting function and the phase detecting function, the use is further expanded.

The above example is an example of FSK (frequency shift keying), but the influence of the phase of the frequency switching point can be easily removed. Realization method of the phase detection means, resolution of the wave number detection means and its realization method, processing methods such as a method of combining the results obtained from the phase detection means and the wave number detection means, frequency switching realization method and switchable frequency types, etc. Needless to say, more complicated waveform transformation can be performed by using the present invention.

[0034]

As described above, the digital direct synthesis type frequency synthesizer according to the present invention can generate different waveforms in a short time with high precision and without phase discontinuity with a simple structure.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a digital direct synthesis frequency synthesizer according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the embodiment of the present invention shown in FIG.

FIG. 3 is a waveform diagram for explaining the operation of the embodiment of the present invention shown in FIG.

FIG. 4 is a waveform diagram for explaining the operation of the embodiment of the present invention shown in FIG.

5 is a waveform chart for explaining the operation of the embodiment of the present invention shown in FIG.

FIG. 6 is a circuit diagram showing another embodiment of the frequency synthesizer for digital direct synthesis according to the present invention.

FIG. 7 is a waveform chart for explaining the operation of the embodiment of the present invention shown in FIG.

FIG. 8 is a waveform chart for explaining the operation of the embodiment of the present invention shown in FIG.

9 is a waveform chart for explaining the operation of the embodiment of the present invention shown in FIG.

10 is a waveform chart for explaining the operation of the embodiment of the present invention shown in FIG.

FIG. 11 is a block diagram showing the configuration of a conventional digital direct synthesis frequency synthesizer.

FIG. 12 is a waveform diagram for explaining the problems of the conventional digital direct synthesis frequency synthesizer shown in FIG.

[Explanation of symbols]

1 Phase Accumulator 2 Waveform Data Converter 3 (1), 3 (2), 3 (3), 3 (4), ..., 3
(N) Frequency register 4 Selector 5 Discrimination unit

Claims (4)

[Claims] 1. An addition output from the adder is output as address data to a waveform data generating means or memory for storing predetermined waveform data and is supplied to one input terminal of the adder, and the other input terminal of the adder is supplied. In the digital direct synthesis frequency synthesizer which is supplied with predetermined frequency data and outputs the waveform data read from the waveform data generating means or the memory, a plurality of frequency registers which respectively output different frequency data, Selection means for selecting an output from one frequency register of the plurality of frequency registers and supplying it to the other input terminal of the adder, and determining that the output of the adder satisfies a predetermined determination condition. And a discriminating section for controlling the selecting means based on the discrimination result. Junction formation method frequency synthesizer. 2. The discriminating condition is a condition that a phase point in one cycle of the waveform data stored in the waveform data generating means or the memory becomes a predetermined phase point.
Digital direct synthesis frequency synthesizer described in. 3. The frequency synthesizer according to claim 1, wherein the discrimination condition is a condition that the wave number of the waveform read from the waveform data generating means or the memory becomes a predetermined number. 4. The digital direct synthesis frequency synthesizer according to claim 1, wherein the frequency data of the plurality of frequency synthesizers can be changed according to the discrimination result of the discriminator.