JPH088488B2 - Variable frequency divider - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention outputs a pulse proportional to the count value of a D / A conversion counter composed of a preset counter in a cycle according to a total frequency division number. More specifically, the present invention relates to a variable frequency divider circuit that superimposes an output pulse from a D / A conversion counter on a phase comparison output in a PLL circuit to enable highly accurate frequency control.

[Prior Art] Conventionally, there has not been a variable frequency dividing circuit of this type. As a similar variable frequency dividing circuit, Japanese Patent Application No. Sho 63-229693 was filed by the present applicant.
There is a variable frequency divider circuit proposed in No.

The variable frequency divider circuit according to Japanese Patent Application No. Sho 63-229693 mentioned above, as shown in FIG. 4, divides the frequency of the frequency-divided signal f _C by a 2-coefficient prescaler 1, a swallow counter 2, a main counter 3, D / A conversion counter 4, and m, n (m <
The arithmetic circuit 5 is provided for receiving the frequency division number setting code n) and setting the count numbers of the swallow counter 2 and the main counter 3.

The arithmetic circuit 5 uses the frequency division number setting codes n, m to (m +
2 ^M ) and (n-1) are calculated and set as the count numbers in the swallow counter 2 and the main counter 3, respectively.

In the 2-coefficient prescaler 1, the frequency division control signal M _OD performs the frequency division operation during the high potential period (2 ^M +1), and the frequency division control signal M _OD performs the low potential period during the 2 ^M frequency division operation to generate the divided signal f The frequency of _C is divided and the intermediate divided clock C _K is output.

The swallow counter 2 receives the intermediate frequency-divided clock C _K as a count input, receives the start signal ST output every time the (n−1) frequency-dividing operation in the main counter 3 is completed, and receives the intermediate frequency-divided clock C _K (m + 2 ^M). ) The period division control signal from the end of (m + 2 ^M ) counting to the input of the next start signal ST after the period division control signal M _OD to be counted is set to high potential
The switching of the frequency division number of the 2-coefficient prescaler 1 is controlled by setting M _OD to a low potential.

The main counter 3 outputs the intermediate divided clock C _K to (n-1)
Frequency division is performed to obtain a frequency division signal f _D , and a start signal ST is sent every (n-1) frequency division.

When the preset value P is pelset, the D / A conversion counter 4 counts the intermediate frequency-divided clock C _K , generates a high potential output until the count value reaches the preset value, and when the count value reaches the preset value. The low potential output is generated until the next start signal is supplied from. D / A conversion counter 4
_Is shown as the pulse width converted signal D _AP .

In the variable frequency dividing circuit having such a configuration, the total frequency dividing number q is q = (2 ^M +1) × (m + 2 ^M ) +2 ^M × (n−1−m−2 ^M ) = m + 2 ^M × n. … (1).

This total frequency division number q is counted by the swallow counter 2 for the frequency division setting code m, and the main counter 3
Then, the frequency division setting code n is frequency-divided by n, and the main counter 3 counts n times. During the m counting period, the 2-coefficient prescaler 1 frequency-divides (2 ^M +1) and the remaining (n- m) Counting period is 2 ^M with 2-coefficient prescaler 1
Total frequency division number in the conventional variable frequency dividing circuit for frequency division operation qq = m * ( ^2M + 1) + (nm) * ^2M = m + ^2M * n ....
It is the same as (1 ').

That is, the total number of divisions by the variable frequency divider circuit shown in FIG. 4 is the same as that of the conventional variable frequency divider circuit.

Furthermore, in the variable frequency dividing circuit shown in FIG. 4, the swallow counter 2 counts the intermediate frequency dividing block C _K , and the minimum 2
^M (when m = 0) Count period High potential division control signal M
_In order to output _OD , the 2-coefficient prescaler 1 performs (2 ^M +1) frequency division operation during this period. Now, the pulse width conversion signal D
_If the pulse width ratio of _AP is d, A pulse train is obtained, and by averaging in the range of 0 ≦ P ≦ 2 ^M , a voltage or current proportional to the preset value P is obtained.

[Problems to be Solved by the Invention] However, when the variable frequency dividing circuit according to Japanese Patent Application No. 63-229693 is used, the frequency dividing number setting codes m and n are received, and (m + 2 ^M ) and (n- There is a problem that an arithmetic circuit for performing each of 1) is required, and the configuration of the variable frequency dividing circuit becomes complicated.

Furthermore, since the period in which the 2-coefficient prescaler performs the 2 ^M frequency division operation, that is, the (n-1-m-2 ^M ) counting period must be a positive number, n ≧ 1 + m + 2 ^M , and
Since 2 ^M −1 ≧ m ≧ 0, n ≧ 2 ^{(M + 1),} and the range in which continuous frequency division numbers are obtained is q ≧ 2 ^M × (2 ^M +1) + (2 ^{(M + 1)} −2 ^M ) × 2 ^M = 2 ^{(M + 1)} +2 ^M has the problem that it is restricted, and the main counter has (n-1) frequency division operation for frequency division setting code n. There was a problem that it had to be done.

The present invention has been made in view of the above problems,
A simple configuration that does not require an arithmetic circuit, and there are few restrictions on the range in which continuous frequency divisions can be obtained, and D / A
An object of the present invention is to provide a variable frequency divider circuit that enables high-precision frequency control by superimposing an output pulse from a conversion counter on a phase comparison output in a PLL circuit.

[Means for Solving the Problems] A variable frequency dividing circuit according to claim 1 of the present invention divides the frequency-divided output of the frequency-divided signal by a 2-coefficient prescaler and a frequency-divided output of the 2-coefficient prescaler by n. The main counter and the two-coefficient prescaler during the m (m <n) counting period in the n-frequency division of the main counter are caused to perform frequency division for one counting, and the other two-coefficient prescaler during the (n−m) counting period. The swallow counter for performing the frequency division for counting and the counting of the frequency-divided output of the 2-coefficient prescaler are started in synchronization with the end of the frequency division by n by the main counter, and the frequency-divided output is counted from the start of the counting. A D / A conversion counter that generates an output of a predetermined level until the count value reaches a preset value, and the phase comparison output of the PLL circuit and the output of the D / A conversion counter are superimposed to make the PLL. Supplying the reduction filter of the road, and is characterized in that so as to start counting in swallow counter in synchronism with the output disappearance of the D / A conversion counter.

According to a second aspect of the present invention, there is provided a variable frequency divider circuit having a two-coefficient prescaler for dividing the frequency of a signal to be frequency-divided, a main counter for dividing the frequency-divided output of the two-coefficient prescaler by n, and n minutes for the main counter. A swallow that causes one coefficient to be divided in the two-coefficient prescaler during m (m <n) counting periods in the cycle, and the other coefficient to be divided in the two-coefficient prescaler during (nm) counting period. The counter and the swallow counter start counting the frequency-divided output of the 2-coefficient prescaler in synchronism with the end of counting, and from the start of the counting until the count value obtained by counting the frequency-divided output reaches a preset value. And a D / A conversion counter that generates a level output, and superimposes the phase comparison output of the PLL circuit and the output of the D / A conversion counter and supplies it to the reduction filter of the PLL circuit. In addition, the swallow counter starts counting in synchronization with the end of the frequency division by n by the main counter.

[Operation] In the variable frequency dividing circuit according to claim 1 of the present invention, the D / A conversion counter starts counting the output of the 2-coefficient prescaler in response to the frequency division end signal of the main counter, and from the start of this counting, Since the output of a predetermined level is generated until the count value obtained by counting the outputs of the two-coefficient prescaler reaches a preset value and the counting of the swallow counter is started in synchronization with the generation of this output, the present invention is also claimed. In the variable frequency dividing circuit according to item 2, the count of the swallow counter is started by the frequency division end signal of the main counter, and D / A is generated by the count end signal of the swallow counter.
Since the conversion counter starts counting the output of the two-coefficient prescaler and the output of a predetermined level is generated until the count value obtained by counting the output of the two-coefficient prescaler reaches a preset value, In the variable frequency dividing circuit according to claims 1 and 2 of the invention, the total frequency dividing number is the same as that of the conventional variable frequency dividing circuit, and the variable frequency dividing circuit of Japanese Patent Application No. 63-229693 is disclosed. It does not require an arithmetic circuit as in.

 Furthermore, the restriction of the continuous frequency division number is relaxed.

[Embodiment] Next, an embodiment of a variable frequency dividing circuit according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a variable frequency dividing circuit according to the present invention, and FIG. 3 is a block diagram showing a configuration of another embodiment of a variable frequency dividing circuit according to the present invention.

First, a variable frequency dividing circuit 22A according to an embodiment of the present invention will be described.

The variable frequency dividing circuit 22A is supplied with the frequency-divided signal F _{C and} has a 2-coefficient prescaler 32 for switching the frequency division ratio thereof, a swallow counter 34, and a main counter 36, and further D /
It has an A conversion counter 40.

The D / A conversion counter 40 is supplied with (P) as a preset value.

In FIG. 1, reference symbol C _K is an intermediate divided clock and ST ₁ is D
This is a start signal of the / A conversion counter 40, and ST ₂ is a start signal of the swallow counter 34. Furthermore, M _OD is 2
A frequency division control signal of the coefficient prescaler 32, F _D is a frequency division signal, and D _AP is a pulse width conversion signal. Further, m and n are frequency division number setting codes, and P is a preset value as described above.

The 2-coefficient prescaler 32 performs an operation of frequency division 2 ^M +1 while the frequency division control signal M _OD is at a high potential, frequency- _divides the frequency of the frequency-divided signal F _C , and sends an intermediate frequency-divided clock C _K. Further, the frequency division control signal M _OD performs a 2 ^M frequency division operation while the potential is low, divides the frequency of the frequency-divided signal F _C and outputs the intermediate frequency division clock C _K.

The start signal ST ₂ is supplied to the swallow counter 34, and the frequency division control signal M _OD is maintained at a high potential during the period in which the frequency division number setting code m of the intermediate frequency division clock C _K is counted.
Further, the frequency division control signal M _OD is maintained at a low potential until the next start signal ST ₂ is supplied.

Further, the main counter 36 divides the intermediate frequency-divided clock C _K by the frequency-division-number setting code n to send a frequency-divided signal F _D, and at the same time, outputs a start signal ST ₁ for each frequency-division of the frequency-division setting code n. Send out.

When the start signal ST ₁ is supplied, the D / A conversion counter 40 is preset with the preset value P, starts counting the intermediate frequency-divided clock C _K , and has a pulse width during the period of counting up to the preset value P. The conversion signal D _AP is maintained at a high potential and the start signal ST ₂ is sent to the swallow counter 34 at the end of counting the preset value P. Further, the pulse width conversion signal D _AP is maintained at a low potential until the next start signal ST ₁ arrives.

Therefore, as shown in FIG. 2 (a), the D / A conversion counter 40 starts counting the intermediate frequency-divided clock C _K from the time when the start signal ST ₁ is input, and at the same time, FIG. 2 (b).
Pulse width conversion signal that generates a high potential output and changes to a low potential output when the count value reaches the preset value P as shown in
D _AP is transmitted.

Next, the frequency dividing operation of the variable frequency dividing circuit 22A will be described with reference to FIG.

FIG. 5 (a) shows the intermediate divided clock C _K obtained by dividing the divided signal F _C, and FIG. 5 (b) shows the pulse width conversion signal D
The _AP, a fifth diagram (c) is frequency-division control signal M _OD, FIG. 5 (d) shows a divided signal F _D, respectively.

The divided signal F _C in 2 modulus prescaler 32 when of the divided signal F _C is input frequency-division control signal M _OD is low potential
Is divided by 2 ^{M and} output from the 2-coefficient prescaler 32 as an intermediate divided clock C _K. The main counter 36 _divides in response to the intermediate divided clock C _K. Main counter
When the counter 36 counts the intermediate frequency-divided clock C _K by n, the start signal ST ₁ is output from the main counter 36. The D / A conversion counter 40 receiving the start signal ST ₁
Starts counting the C _K, Doing count to the preset value P,
The pulse width conversion signal D _AP is changed from the high potential to the low potential and the start signal ST ₂ is output. The frequency division control signal M _OD output from the swallow counter 34 in response to the start signal ST ₂ is controlled from a low potential to a high potential. In response to the division control signal M _OD that has been set to the high potential, the division number in the 2-coefficient prescaler 32 is switched from 2 ^M to (2 ^M +1), and the frequency-divided signal F _C in the prescaler 32 becomes (2 ^M +
1) The frequency-divided signal F _{C that} has been frequency-divided and frequency-divided by (2 ^M +1) is output from the prescaler 32 as an intermediate frequency-divided clock C _K. In response to this intermediate divided clock C _K , the swallow counter
When 34 counts the intermediate divided clock C _K by m, the division control signal M _OD is changed from the high potential to the low potential, and the division number in the 2-coefficient prescaler 32 is switched from (2 ^M +1) to 2 ^M. the divided signal F _C Te is 2 ^M division in the prescaler 32, 2 ^M division has been the divided signal F _C is output from the 2-modulus prescaler 32 as an intermediate divided clock C _K.

On the other hand, when the main counter 36 counts the intermediate frequency-divided clock C _K n times from when the start signal ST ₁ is output, the main counter 36 again outputs the start signal ST ₁ , and the above is repeated.

In FIG. 5 (a), the period A ₁ is a 2-coefficient prescaler.
32 indicates the period in which the divided signal F _C is _divided by 2 ^M , and the period A ₂
Indicates a period during which the 2-coefficient prescaler 32 divides the divided signal F _C by (2 ^M +1). Also, the pulse width conversion signal
The period T in which the D _AP is at a high potential is T = (1 / F _C ) × 2 ^M × P, which is a period proportional to the preset value P.

From the above respective configurations and operations of the variable frequency dividing circuit 22A, the total frequency division number q ″ of the variable frequency dividing circuit 22A is: q ″ = (2 ^M +1) × m + 2 ^M × (nm) = m + 2 ^M × n …
... (2), which is the same as the conventional case.

Further, if the pulse width ratio of the pulse width conversion signal D _AP is d, The pulse train is obtained, and by averaging, a D / A conversion voltage (or current) proportional to the preset value P is obtained.

To obtain consecutive frequency division numbers, n ≧ m + P, 2 ^M −1 ≧
Since m ≧ 0, the continuously variable frequency division number q ′ is q ′ ≧ 2 ^2M −1 + 2 ^M × P (4).

Thus, in the range of 0 ≦ P ≦ q−2 ^M , averaging is proportional to the preset value P, and m + 2 ^M ×
High-precision D / A conversion voltage (or current) inversely proportional to n
That is, the pulse width conversion signal D _AP is obtained.

Next, a PLL circuit using the variable frequency dividing circuit 22A will be described.

The PLL circuit includes a reference oscillator / divider 12 and a crystal oscillator 1
2x, phase comparator 14, low-pass filter 16, VCO 18,
It has a variable frequency dividing circuit 22A or a variable frequency dividing circuit 22B described later.

In these configurations, the output signal changes from pull-in operation (frequency match) to lock-in operation (synchronization) of VCO18.
F ₀ is derived.

This operation will be described. The comparison frequency signal (reference signal) F _R sent from the reference oscillator / divider 12 is supplied to the phase comparator 14.

On the other hand, the divided signal F _C from the VCO 18 is fed to the variable frequency divider 22A (22
The frequency-divided signal F _D having a frequency equal to that of the comparison frequency signal F _R is supplied to the phase comparator 14.

The phase comparison signal S _P sent from the phase comparator 14 is supplied to the low-pass filter 16, and the control signal S _C integrated here is VC.
Applied to O18. In this case, the variable frequency divider 22A (22B)
From, a pulse width conversion signal D _AP corresponding to the amount of phase slip and the amount of phase shift of the phase comparison signal S _P is transmitted. Here, the pulse width conversion signal D _AP and the phase comparison signal S _P are supplied to the low pass filter 16 so as to cancel each other. As a result, the control signal S _C of DC voltage (current) with less ripple is transmitted.

As described above, the basic operation and the like are well known in the art (for example, Japanese Patent Laid-Open No. 63-28131), and a detailed description thereof will be omitted, but the description will be made in relation to the D / A conversion counter 40 (41). To do.

Preset value P to be supplied to the D / A converter counter 40 (41) corresponds to X _L supplied to the D / A converter shown in JP-A-63-28131, latches a digital adder The output of the numerical integrator consisting of and is added for each output of the strobe signal, resulting in P, 2P, 3P, ..., and the D / A conversion counter 40 (41) undergoes intermediate frequency division until it reaches the preset value. The clock C _K is counted and a high potential output is generated during this counting period.

Therefore, the envelope of the pulse width converted signal D _AP output from the D / A converter counter 40 (41) becomes a saw-tooth wave, it becomes similar to the output waveform of the D / A converter shown in the publication.

On the other hand, the phase comparison signal output from the phase comparator 14 is VC
The output of O18, that is, a phase slip that occurs while the divided signal F _C is being divided causes a sawtooth wave. Therefore, the pulse width conversion signal D _AP is added to the low-pass filter 16 so as to cancel the sawtooth wave of the phase comparison signal S _P. As a result, the phase slip of the phase comparison signal S _P is canceled, so that a high accuracy can be performed the output frequency control of the PLL circuit.

Next, a variable frequency dividing circuit 22B according to another embodiment of the present invention will be described.

The variable frequency dividing circuit 22B has the same configuration as the variable frequency dividing circuit 22A, but as described later, the start signal ST ₁ is supplied to the swallow counter 35 instead of the D / A conversion counter 40,
Further, the start signal ST ₂₁ is supplied to the D / A conversion counter 41 instead of the swallow counter 34.

In FIG. 3, reference character C _K is an intermediate frequency-divided clock, ST ₁ is a start signal of the swallow counter 35, and ST ₂₁ is a D / A.
This is a start signal for the conversion counter 41. Furthermore, M _OD is 2
A frequency division control signal of the coefficient prescaler 32, F _D is a frequency division signal, and D _AP is a pulse width conversion signal. Further, m and n are frequency division number setting codes, and P is a preset value.

In the 2-coefficient prescaler 32, the frequency division control signal M _OD performs the operation of 2 ^M +1 division during the high potential period, and further, the frequency division control signal M _OD performs the operation of 2 ^M division during the low potential period. Thus, an intermediate divided clock C _K obtained by _dividing the frequency of the divided signal F _C is obtained.

In the swallow counter 35, the start signal ST ₁ is supplied and the frequency division control signal M _OD is maintained at a high potential during the period in which the intermediate frequency division clock C _K is counted by the frequency division number setting code m, and then the frequency division control signal M _OD is maintained at a high potential. Generates a start signal ST ₂₁ at the end of counting the number setting code m. Further, the frequency division control signal M _OD is maintained at a low potential until the next start signal ST ₁ is supplied. The start signal ST ₂₁ is supplied to the D / A conversion counter 41.

The main counter 36 divides the intermediate frequency-divided clock C _K into the frequency-division-number setting code n to obtain the frequency-divided signal F _D , and sends out the start signal ST ₁ for each frequency-division of the frequency-division number setting code n.

Similar to the D / A conversion counter 40, the D / A conversion counter 41 supplies the start signal ST _{21 and the} pulse width conversion signal D _AP during the period in which the intermediate divided clock C _K is counted up to the preset value P. Is maintained at a high potential, and the pulse width conversion signal D _AP is maintained at a low potential until the next start signal ST ₂₁ is supplied. Therefore, the pulse width conversion signal _DAP output from the D / A conversion counter 41 is as shown in FIG. 2 (b).

Next, the frequency dividing operation of the variable frequency dividing circuit 22B will be described with reference to FIG.

FIG. 6 (a) shows the intermediate divided clock C _K obtained by dividing the divided signal F _C, and FIG. 6 (b) shows the pulse width conversion signal D
_AP , FIG. 6 (c) shows the frequency division control signal M _OD , and FIG. 6 (d) shows the frequency division signal F _D.

The divided signal F _C in 2 modulus prescaler 32 when of the divided signal F _C is input frequency-division control signal M _OD is low potential
Is divided by 2 ^{M and} output from the 2-coefficient prescaler 32 as an intermediate divided clock C _K. In response to this intermediate divided clock C _K , the main counter 36 divides the frequency, and the main counter 36
When the counter 36 counts the intermediate frequency-divided clock C _K for n, the main counter 36 outputs the start signal ST ₁ . Upon receiving the start signal ST ₁ , the swallow counter 35 receives the frequency division control signal M
Change _OD from low potential to high potential. In response to the division control signal M _OD that has been set to the high potential, the division number in the 2-coefficient prescaler 32 is switched from 2 ^M to (2 ^M +1), and the frequency-divided signal F _C in the prescaler 32 becomes (2 ^M +1) divided. The divided signal F _C divided by (2 ^M +1) is the prescaler.
32 is output as an intermediate frequency-divided clock C _K from frequency division control signal M _OD to the swallow counter 35 receives the intermediate frequency clock C _K is output to the intermediate frequency clock C _K from the swallow counter 35 when m counted Is changed from a high potential to a low potential, and at the same time, a start signal ST ₂ is output. 2 upon receiving the frequency division control signal M _OD controlled from high potential to low potential
The frequency division number in the coefficient prescaler 32 is from (2 ^M +1) to 2 ^M
Switched on by the frequency-divided signal F _C is 2 ^M division in the prescaler 32, 2 ^M division has been the divided signal F _C is output as an intermediate frequency-divided clock C _K from the prescaler 32. The D / A conversion counter 41 receives the start signal ST ₂ and the prescaler 32
When the counting of the intermediate frequency-divided clock C _{K obtained} by dividing the frequency-divided signal F _C by 2 ^M is started and counting is performed up to the preset value P, the pulse width conversion signal D _AP is changed from the high potential to the low potential. .

On the other hand, when the main counter 36 counts the intermediate frequency-divided clock C _K n times from when the start signal ST ₁ is output, the main counter 36 again outputs the start signal ST ₁ , and the above is repeated.

In FIG. 6 (a), the period A ₁ is a 2-coefficient prescaler 32.
Indicates the period during which the divided signal F _C is _divided by 2 ^M , and the period A ₂ indicates the period during which the 2-coefficient prescaler 32 divides the divided signal F _C by (2 ^M +1). . Also, the pulse width conversion signal D
The period T when _AP is at a high potential is T = (1 / F _C ) × 2 ^M × P,
The period is proportional to the preset value P.

Here, also in the above-mentioned variable frequency dividing circuit 22B, the total frequency dividing number q ″ is the same as that in the above equation (2), and the pulse width rate is also the same as in the equation (3). The frequency q'is also the same as in the equation (4).

The pulse width conversion signal output from the D / A conversion counter 41 in the variable frequency dividing circuit 22B is converted into D in the variable frequency dividing circuit 22A.
Like the pulse width conversion signal output from the / A conversion counter 40, high-precision frequency control can be performed by superimposing it on the phase comparison output of the PLL circuit, as in the case of the variable frequency dividing circuit 22A.

[Effects of the Invention] As described above, according to the variable frequency dividing circuit of claims 1 and 2 of the present invention, the same total frequency dividing number as that of the conventional variable frequency dividing circuit can be obtained. The effect that the arithmetic circuit for calculating (m + 2 ^M ) and (n-1) from the frequency division number setting codes n and m, which is required in the variable frequency dividing circuit of No. 229693, becomes unnecessary and the configuration becomes simple. can get.

Further, according to the variable frequency dividing circuit of claims 1 and 2, the total frequency dividing number which can be continuously varied is such that the 2-coefficient prescaler performs frequency dividing operation of 2 ^M +1 and 2 ^M , and the preset value is When P is set, 2 2 ^M -1 + 2 ^M × P or more, which is more effective than the variable frequency divider circuit of Japanese Patent Application No. 63-229693.

Furthermore, according to the variable frequency divider circuit of the first and second aspects of the present invention, the pulse width conversion signal of the variable frequency divider circuit is PL
By superimposing it on the phase comparison output of the L circuit, it is possible to obtain an effect that the output frequency of the PLL circuit can be controlled with high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a variable frequency dividing circuit according to the present invention, and FIG. 2 is a D / A conversion counter in one embodiment of the variable frequency dividing circuit according to the present invention and another embodiment. 3 is a block diagram showing the configuration of another embodiment of the variable frequency dividing circuit according to the present invention, and FIG. 4 is a variable component proposed by the applicant of the present patent application. FIG. 5 is a block diagram showing a configuration of a frequency divider circuit, FIG. 5 is a timing diagram for explaining a frequency dividing operation in one embodiment of the variable frequency divider circuit according to the present invention, and FIG. 6 is another diagram of the variable frequency divider circuit according to the present invention. FIG. 7 is a timing chart for explaining the frequency dividing operation in the embodiment of the present invention, and FIG. 7 is a block diagram showing a configuration of a PLL circuit to which a pulse width conversion signal is supplied in an embodiment of the variable frequency dividing circuit according to the present invention. 22A, 22B ...... Variable frequency divider, 32 ...... 2 coefficient prescaler 34, 35 ...... Swallow counter, 36 ...... Main counter 40, 41 ...... D / A conversion counter, D _AP ...... Pulse width conversion signal F _C …… Divided signal, F _D …… Divided signal M _OD …… Divided control signal, m, n …… Division number setting code P …… Preset value, ST ₁ , ST ₂ , ST ₂₁ …… Start signal

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-63-28131 (JP, A) JP-A-57-201342 (JP, A) JP-A-53-121559 (JP, A)

Claims (2)

[Claims] 1. A 2-coefficient prescaler for dividing the frequency of a frequency-divided signal, a main counter for dividing the divided output of the 2-coefficient prescaler by n, and m (m <n) during n division in the main counter. A swallow counter that causes one coefficient to be divided by the two-coefficient prescaler during the counting period, and a (n−m) swallow counter that causes the other coefficient to be divided during the counting period by the main counter. The counting of the frequency-divided output of the 2-coefficient prescaler is started in synchronism with the end of, and the output of a predetermined level is generated from the start of the counting until the count value by the counting of the frequency-divided output reaches a preset value. A / A conversion counter is provided, and the phase comparison output of the PLL circuit and the output of the D / A conversion counter are superimposed and supplied to the reduction filter of the PLL circuit.
A variable frequency divider circuit, wherein counting is started in a swallow counter in synchronization with the disappearance of the output of an / A conversion counter. 2. A 2-coefficient prescaler for dividing the frequency of a frequency-divided signal, a main counter for dividing the divided output of the 2-coefficient prescaler by n, and m (m <n) during division by n in the main counter. A swallow counter that causes one of the counts to be divided by the two-coefficient prescaler during the counting period, and a count of the swallow counter that causes the other coefficient to be divided by the two-coefficient prescaler during the counting period (nm). The D / A which starts counting the frequency-divided output of the 2-coefficient prescaler in synchronization with the above and outputs a predetermined level from the start of the counting until the count value obtained by counting the frequency-divided output reaches a preset value. A conversion counter is provided, and the phase comparison output of the PLL circuit and the output of the D / A conversion counter are superimposed and supplied to the reduction filter of the PLL circuit. A variable frequency divider circuit characterized in that counting is started in a swallow counter in synchronization with the end of frequency division.