JPH088478A - Ld driving current limiting circuit - Google Patents

Abstract

PURPOSE:To provide an LD driving current limiting circuit which does not fall into an abnormal control state even after occurrence of a current limiting state in a circuit to be used to limit the driving circuit of the LD. CONSTITUTION:An LD current control signal, which controls the circuit of a light emitting element in accordance with the error voltage between the voltage on the side of monitoring which monitors the photo-output of a light emitting element 4 by an APC output-stage circuit 1, is generated, and at the same time, an LD current control signal is controlled in such a manner that it becomes constant, an output current is generated on a transistor 5, which is series-connected to a constant current source 10 in accordance with the LD current control signal, by a current control circuit 2, a driving current is generated from a transistor 6 by an LD driving circuit 3 in the state of constant relation with the current of the transistor 5, and the light-emitting element is driven. At this time, the LD driving current is controlled by restricting the current of the transistor 5 using the constant current source 10.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a laser diode (L
The present invention relates to a circuit for limiting a drive current of D), and particularly to an LD drive current limiting circuit for limiting an LD drive current of an electro-optical conversion circuit device in optical communication.

In optical communication, normally, an LD is used as a light source to generate an optical signal and the optical signal is transmitted through an optical fiber for communication. At this time, in order to keep the optical output constant, automatic optical output is performed. A control (APC) circuit is used.

In the APC circuit, it is necessary that the optical output level can be stabilized with high accuracy and that the operation of the APC circuit does not become abnormal even after the current limiting state occurs.

[0004]

2. Description of the Related Art FIG. 6 shows a general structure of a transmission circuit used for optical communication. 11 is an LD for generating an optical signal, 12 is an LD 11 driven by a data input signal DATA. LD drive circuit for emitting light
Reference numeral 13 is an APC circuit for stabilizing the light output of the LD 11, and 14 is a photodiode (PD) for detecting the light generated by the LD 11.

The LD 11 emits light by receiving an LD drive current from the LD drive circuit 12. In general, LD
When the driving current is constant, the light output decreases when the temperature is high, but on the contrary, the light output increases when the temperature is low. Therefore, the LSI that constitutes the optical transmission circuit
By incorporating the APC circuit 13 into the LD1,
A method of controlling the LD drive current so that the light output level of 1 is always constant is generally used.

The PD 14 receives the back light of the LD 11 and generates an electric signal (monitor current) corresponding to an optical signal.
The APC circuit 13 compares the monitor current with the reference signal and feeds back a control signal (LD current control signal) corresponding to the difference to the LD drive circuit 12. The LD drive circuit 12 controls the magnitude of the drive current for the LD 11 in accordance with the LD current control signal, so that feedback control is performed so that the monitor current and the reference signal match.
The light output of 11 is stabilized.

In this case, when the light output of the LD 11 is extremely small, or when the monitor input signal is disconnected due to imperfect connection in the light output monitor portion, the APC circuit 1
3 operates in a direction in which the monitor current from the PD 14 always tries to match the reference signal, so that an excessive drive current is output from the LD drive circuit 12 and the LD 11 is destroyed or L
There is a problem that the D drive circuit 12 may be destroyed.

On the other hand, in the conventional LD drive circuit, the LD
A method of preventing destruction of the LD and the LD drive circuit by providing a current limiting function is used.

FIG. 7 shows a conventional LD drive circuit with a current limiting function, which uses a current comparison circuit. In the figure, 15 is a constant current source that generates a reference current I ₀ , and 16 is a current comparison circuit that generates a current I ₁ that is determined according to an LD current control signal and performs a current comparison with the reference current I _0. . Tr1 to Tr5 are NchM
The OS transistors and Tr6 and Tr7 are Pch MOS transistors.

In FIG. 7, the Pch MOS transistors Tr6 and 7 form a current mirror, and an LD current control signal from an APC circuit (not shown) is applied to the gate of the Nch MOS transistor Tr1 to form an LD.
The current of the Nch MOS transistor Tr2 increases or decreases according to the increase or decrease of the current control signal. Further, the Nch MOS transistors Tr2, 4 form a current mirror, and therefore the Nch MOS transistor Tr that drives the LD 11
The currents of 4 and 5 are controlled according to the LD current control signal. At this time, by controlling the gate of the Nch MOS transistor Tr5 by the data input signal DATA, the LD 11 generates an optical output that is turned on / off according to the data input signal DATA.

On the other hand, the current comparison circuit 16 generates the current I ₁ determined by the LD current control signal, and the constant current source 1
By comparing the reference current I ₀ from 5, when the current value I ₁ exceeds the reference current value I _0, a high level, when the current value I ₁ falls below the reference current value I _0, and a low level To generate a switch (SW) signal.

When the SW signal is at low level, Nch
The MOS transistor Tr3 is turned off, and therefore
The current of the Nch MOS transistor Tr4 is not affected by the SW signal. On the other hand, when the SW signal is at the high level, the Nch MOS transistor Tr3 is turned on and the gate voltage of the Nch MOS transistor Tr4 is lowered, so that the current of the Nch MOS transistor Tr4 is reduced.

Therefore, according to the circuit shown in FIG.
When the D current control signal increases above a predetermined value, LD11
LD11 or LD driving Nch by limiting the current of
The MOS transistors Tr4, 5 can be protected.

[0014]

In the conventional LD drive current limiting circuit shown in FIG. 7, once the current limiting operation is started by the increase of the LD current control signal, the optical output of the LD 11 is lowered, and Since the LD current control signal is controlled in the direction of increasing, it is impossible to restore the state of the LD current control signal such that the APC operation is performed. Therefore, the LD drive circuit should perform the normal operation thereafter. There was a problem that could not be.

The present invention is intended to solve the problems of the prior art as described above, and has an LD having an APC function.
An object of the present invention is to provide an LD drive current limiting circuit that can always correctly limit the LD drive current without falling into an abnormal control state even if the LD drive current limiting operation is performed in the drive circuit. .

[0016]

[Means for Solving the Problems]

(1) FIG. 1 shows the basic configuration of the present invention.
In the present invention, the LD current control signal for controlling the current of the light emitting element is generated in accordance with the error voltage between the monitor side voltage monitoring the light output of the light emitting element 4 and the reference voltage, and
An APC output stage circuit 1 for controlling the LD current control signal to be constant, and a constant current source 10 according to the LD current control signal.
A current limiting circuit 2 for generating an output current in a transistor 5 connected in series with the LD, and an LD driving circuit 3 for generating an LD driving current from the transistor 6 and driving the light emitting element 4 in a constant relationship with the current of the transistor 5. Equipped with a constant current source 10
The LD drive current is limited by limiting the current of the transistor 5 by.

(2) In (1), the APC output stage circuit 1
Is charged by the current of the transistor 7 and a transistor 7 which causes a current to flow in accordance with an error voltage between the monitor side voltage and the reference voltage, and is discharged through a resistor R1 connected in parallel to generate an LD current control signal. Capacitor C generated
1 and a transistor 8 that is controlled by a switch voltage at the drain of the transistor 5 to turn on or off the current of the transistor 7.

(3) In (1), the error voltage is the monitor current of the light receiving element 9 for detecting the light output of the light emitting element 4 and the signal current corresponding to the data input signal for controlling the light output of the light emitting element 4. Of the output voltage obtained by current / voltage conversion by the I / V conversion circuit 21 are detected by the peak detection circuits 22 and 23, and they are superposed so that the peaks of the envelopes of the detection signals coincide with each other. Get by the time difference.

(4) In (1), the transistor 5 of the current limiting circuit and the transistor 6 of the LD driving circuit form a current mirror.

(5) In (4), the transistors 5 and 6 are Nch MOS transistors Tr, and the constant current source 10 and the light emitting element 4 are transistors 5 and 6, respectively.
Connect to the power supply side of.

(6) In (4), the transistors 5 and 6 are Pch MOS transistors Tr, and the constant current source 10 and the light emitting element 4 are transistors 5 and 6, respectively.
Connect to the ground side of.

[0022]

[Action]

(1) In the APC output stage circuit 1, an error voltage is generated by comparing the monitor side voltage monitoring the light output of the light emitting element 4 with the reference voltage, and the LD current control signal is generated by this error voltage. The LD current control signal is controlled to be constant by utilizing the terminal voltage of the capacitor charged by the generation of the error voltage.

In the current limiting circuit 2, an output current is generated in the transistor 5 connected in series with the constant current source 10 according to the LD current control signal. Further LD drive circuit 3
Then, the LD drive current is generated from the transistor 6 in a constant relationship with the current of the transistor 5 to drive the light emitting element 4.

According to the present invention, the current of the transistor 5 is limited within the range of the value by the constant current of the constant current source 10. Therefore, even if the LD current limiting operation is performed, the abnormal control state is thereafter generated. Never fall into.

(2) In the APC output stage circuit 1, the transistor 7 causes a current to flow according to the error voltage between the monitor side voltage and the reference voltage, and the capacitor C1 is charged by the current of the transistor 7 and connected in parallel. Resistance R
The LD current control signal is generated by discharging through 1. At this time, the on / off of the current of the transistor 7 is controlled by the switch voltage generated at the drain of the transistor 5.

Therefore, the LD current control signal is controlled so as to be almost constant at all times without any abrupt change when the error voltage is generated, so that the LD drive current can be stabilized.

(3) The error voltage in this case is the monitor current of the light receiving element 9 for detecting the light output of the light emitting element 4 and the signal current corresponding to the data input signal for controlling the light output of the light emitting element 4. Are subjected to current / voltage conversion by the I / V conversion circuit 21 to generate an output voltage, the peaks of the obtained output voltage are detected by the peak detection circuits 22 and 23, and the envelope of this detection signal is detected in the comparison circuit 24. It is obtained by superimposing and comparing so that the peaks of the lines coincide with each other and obtaining the difference.

In the present invention, L for controlling the drive current of the LD
The D current control signal is not obtained by comparing the currents,
Since the voltage value is compared and obtained, the circuit configuration becomes easy.

(4) The transistor 5 of the current limiting circuit 2,
By configuring the transistor 6 of the LD drive circuit 3 so as to form a current mirror, it is possible to make each current have a fixed relationship according to the ratio of the channel width.

(5) Transistors 5 and 6 of LD drive circuit 3
Can be configured using the Nch MOS transistor Tr. In this case, the constant current source 10 and the light emitting element 4
And are connected to the power supply sides of the transistors 5 and 6, respectively.

(6) Transistors 5 and 6 of LD drive circuit 3
Can be configured using a Pch MOS transistor Tr. In this case, the constant current source 10 and the light emitting element 4
And are connected to the ground side of the transistors 5 and 6, respectively.

[0032]

FIG. 2 shows an embodiment (1) of the present invention, in which 1 is an APC output stage circuit for generating an output signal of the APC circuit, and 2 is a drive current limiter for the LD 11. A current limiting circuit 3 indicates an LD drive circuit that generates a drive current for the LD 11.

In the APC output stage circuit 1, Tr11,
Tr12 is a Pch MOS transistor Tr, C1 is a capacitor, and R1 is a resistor. In the current limiting circuit 2, 17 is a constant current source for generating a constant current I _CONST , and Tr1.
Reference numeral 3 is an Nch MOS transistor Tr. In the LD drive circuit 3, Trs 14 and 15 are Nch MOS transistors Tr.

FIG. 3 shows an APC input stage circuit, in which 21 is a current / voltage (I / V) conversion circuit for converting a current input into a voltage output, and 22 and 23 are peaks of the input voltage, respectively. A peak detecting circuit for detecting 24 is a comparing circuit for comparing outputs of the peak detecting circuits 22 and 23.

The PD 14 receives the back light of the LD 11, generates a monitor current corresponding to an optical signal, and inputs it to the I / V conversion circuit 21. A signal current based on the data input signal DATA is also input to the I / V conversion circuit 21. I /
The V conversion circuit 21 converts both current inputs into voltage signals and outputs them. The peak detection circuits 22 and 23 are I / V
An output signal from the conversion circuit 21 is generated by detecting the peak value of each voltage signal. The comparison circuit 24 compares the outputs of the peak detection circuits 22 and 23 to generate the error voltage V _E.

FIG. 4 is a time chart for explaining the operation of the circuit of the present invention, in which the data input signal DAT is
A ,, are the output signals of the I / V conversion circuit 21, are the output signals of the peak detection circuits 22 and 23, are the output signals of the comparison circuit 24, are the APC charging currents I _APC ,
Is an LD current control signal V _PCNT and is a switch signal V _SW , and their positions are indicated by the same numbers in FIGS. 2 and 3. Hereinafter, FIG. 2 to FIG.
Based on the above, the operation of the circuit of the present invention will be described.

The data input signal DATA is composed of a pulse signal corresponding to the transmitted light output. PD14 is LD
A monitor current whose magnitude changes according to the optical output of 11 is generated. The I / V conversion circuit 21 converts the monitor current signal from the PD 14 and the current signal corresponding to the data input signal DATA into voltage signals, respectively _, and generates an output voltage having the same peak value of the envelope. To do. The peak detection circuits 22 and 23 detect the peak of the output voltage _, and monitor the voltage V _MON on the monitor side and the voltage V _{MON on the} reference side, respectively.
Generate _REF .

The comparison circuit 24 uses the monitor side voltage V._MONWhen
Reference voltage V_REFAnd monitor side voltage V_MON>
Reference voltage V_REFBecomes high level, the monitor side power
Pressure V _MON<Reference voltage V_REFWhen it becomes a low level
Difference voltage V_ETo occur.

In the APC output stage circuit 1, Pch M
The OS transistor Tr12 is turned off when the error voltage V _E is high level, and is turned on when the error voltage V _E is low level. When the Pch MOS transistor Tr12 is turned on, the APC charging current I _APC is generated and the terminal voltage of the capacitor C1, that is, the LD current control signal V _PCNT rapidly rises.

When the LD current control signal V _PCNT is applied to the gate of the Nch MOS transistor Tr13 of the current limiting circuit 2, a current flows through the constant current source 17 and the switch voltage V _{SW is} applied to the drain of the Nch MOS transistor Tr13. To occur. The Pch MOS transistor Tr11 is turned off when the switch voltage V _SW is high level, and is turned on when the switch voltage V _SW is low level.

[0041] By Pch MOS transistor Tr11 is turned on, PchMOS transistor Tr12 is turned off, since the APC charging current I _APC is not flow, thereafter, LD current control signal V _PCNT
Is the time constant C1 · R1 depending on the discharge of the capacitor C1.
Gradually decreases according to. When the LD current control signal V _{PCNT is applied} to the gate of the Nch MOS transistor Tr13, the Nch MOS transistor Tr13 flows a current that changes according to the change of the LD current control signal V _PCNT .

On the other hand, the Nch MOS transistor Tr14 of the LD drive circuit 3 is connected to the Nch MO transistor of the current limiting circuit 2.
The gate is commonly connected to the S transistor Tr13,
Since the current mirror is formed, the LD drive current I _LD that changes according to the change of the LD current control signal V _PCNT also flows through the Nch MOS transistor Tr14, and the optical output of the _{LD 11} connected in series changes. Nch MO
The gate of the S transistor Tr15 is connected to the data input signal D
Controlled by the ATA, the LD 11 generates an optical output that turns on and off according to the data input signal DATA.

As described above, in the circuit shown in FIG.
The optical output level of D11 is controlled by the LD current control signal V _PCNT . The LD current control signal V _PCNT is LD11.
The monitor side voltage V _MON <
APC charging current I _APC when the reference voltage V _REF is reached
Flows and the capacitor C1 is charged to rapidly rise, which raises the optical output level of the LD 11. When the monitor side voltage V _MON > the reference side voltage V _REF due to the increase in the optical output level of the LD 11, the LD voltage control signal V _PCNT increases and the switch voltage V _SW decreases, so that the APC charging current I _APC flows. Since it disappears, the charging of the capacitor C1 stops and the rise of the LD current control signal V _PCNT also stops.

After that, as the capacitor C1 is discharged, L
The D current control signal V _PCNT gradually decreases, which causes L
The optical output level of D11 drops and the monitor side voltage V _MON
<When the reference side voltage V _REF is reached, the APC operation of keeping the optical output level of the LD 11 constant is performed by repeating the change in which the APC charging current I _APC again flows and the LD current control signal V _PCNT rises.

When the optical output of the LD 11 drops due to deterioration of the LD 11 and the monitor side voltage V _MON drops abnormally, the LD current control signal V _PCNT rises and Nch M
Although the current of the OS transistor Tr13 tends to increase, the current of the Nch MOS transistor Tr13 is limited by the current I _CONST of the constant current source 17 connected in series and does not increase above a certain value. Since the Nch MOS transistor Tr14 that drives the LD11 forms a current mirror with the Nch MOS transistor Tr13 as described above, the drive current I _{LD of the} LD11 also does not increase above a certain value. The destruction of the driven Nch MOS transistors Tr14, 15 is prevented.

Nch of the LD drive circuit in this case
 Current limit value I of MOS transistor Tr14
_LDMAXIs an Nch MOS transistor Tr13, 14
Same channel length L_8,L₉ And channel width it
Each W_8,W₉ When I said_LDMAX= I_CONST× (W₉ / W₈ ), LD drive current I_LDIs the current limiting circuit
Constant current value I of the constant current source _CONSTAnd Nch MOS tiger
Limited by the ratio of the channel widths of the transistors Tr13 and Tr14
To be done.

FIG. 5 shows an embodiment (2) of the present invention, in which the same parts as those in FIG.
Tr13 ', Tr14', Tr15 'are Pch MOS
Transistor 11 'is an LD for generating an optical signal,
_{Reference numeral} 17 'is a constant current source for generating a constant current I _CONST .

The embodiment shown in FIG. 5 is the same as the embodiment shown in FIG.
Instead of Tr14 and Tr15, Pch MOS transistors Tr13 ′, Tr14 ′ and Tr15 ′ were used.
When a so-called current discharge type LD drive circuit is used, L
3 illustrates a configuration of a D drive current limiting circuit.

In the circuit of FIG. 5, the LD 11 'and the constant current source 17' are changed according to the change of the transistor used.
Are Pch MOS transistors Tr13 ′,
It is provided on the ground side of Tr14 '. The operation of the circuit of FIG. 5 is similar to that of the embodiment shown in FIG.

[0050]

As described above, according to the present invention, an LD which forms a current mirror together with this transistor in an LD drive circuit by limiting the current flowing through the transistor of the current limiting circuit using a constant current source.
Since the current of the driving transistor is limited and the APC charging current is cut off as the LD current control signal increases, the increase of the LD current control signal is suppressed, so that the LD drive current limiting operation is performed. However, the LD drive current can always be correctly limited without being in an abnormal control state, and the destruction of the LD can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing an embodiment (1) of the present invention.

FIG. 3 is a diagram showing an APC input stage circuit.

FIG. 4 is a time chart explaining the operation of the circuit of the present invention.

FIG. 5 is a diagram showing an embodiment (2) of the present invention.

FIG. 6 is a diagram showing a general configuration of a transmission circuit used for optical communication.

FIG. 7 is a diagram showing a conventional LD drive circuit with a current limiting function.

[Explanation of symbols]

 1 APC output stage circuit 2 current limiting circuit 3 LD drive circuit 4 light emitting element 5 transistor 6 transistor 7 transistor 8 transistor 9 light receiving element 10 constant current source 21 I / V conversion circuit 22 peak detection circuit 23 peak detection circuit 24 comparison circuit C1 capacitor R1 resistance

Claims (6)

[Claims] 1. An LD current control signal for controlling a current of the light emitting element according to an error voltage between a monitor side voltage monitoring a light output of the light emitting element (4) and a reference voltage, and the LD current control. Control to keep the signal constant A
A PC output stage circuit (1), a current limiting circuit (2) for generating an output current in a transistor (5) connected in series with a constant current source (10) in response to the LD current control signal, and the transistor (5). The LD driving current is generated from the transistor (6) in a constant relationship with the current of (5) to generate the light emitting element (4).
And an LD drive circuit (3) for driving the LD drive circuit, the LD drive current limiting circuit limiting the current of the transistor (5) by the constant current source (10). . 2. The APC output stage circuit (1) is charged by a transistor (7) which causes a current to flow according to an error voltage between the monitor side voltage and a reference voltage, and the current of the transistor (7). , Resistors connected in parallel (R
1) a capacitor (C1) which discharges through the LD current control signal and a transistor (7) which turns on or off the current of the transistor (7) controlled by the switch voltage at the drain of the transistor (5). 8) The LD drive current limiting circuit according to claim 1, further comprising: 3. A signal in which the error voltage corresponds to a monitor current of a light receiving element (9) for detecting the light output of the light emitting element (4) and a data input signal for controlling the light output of the light emitting element (4). The peaks of the output voltage obtained by current / voltage conversion of the current and the I / V conversion circuit (21) are detected by the peak detection circuits (22) and (23), and the peak is detected by the comparison circuit (24). 2. The LD drive current limiting circuit according to claim 1, wherein the LD drive current limiting circuit is obtained by a difference when overlapping and comparing so that peaks of envelopes of signals coincide with each other. 4. The transistor (5) of the current limiting circuit
The L according to claim 1, characterized in that the transistor and the transistor (6) of the LD drive circuit form a current mirror.
D drive current limiting circuit. 5. The transistors (5) and (6) are Nc.
5. The hMOS transistor Tr, which is characterized in that the constant current source (10) and the light emitting element (4) are connected to the power supply sides of the transistors (5) and (6), respectively. LD drive current limiting circuit. 6. The transistors (5), (6) are Pc
5. The hMOS transistor Tr, which is characterized in that the constant current source (10) and the light emitting element (4) are connected to the ground side of the transistors (5) and (6), respectively. LD drive current limiting circuit.