JPH088417A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having a two-layered electrode structure wherein metal is used for an upper layer electrode and a lower layer electrode, and an interlayer insulating film.is not damaged by shock at the time of wire bonding. CONSTITUTION:A bipolar type semiconductor chip has an emitter region 22 wherein a main current flows and a base region 11 for controlling the main current, in the vicinity of the surface. The above semiconductor chip has a structure wherein a trench 5 is formed on the surface of the base region 11, a metal base electrode 1 which is in ohmic contact with the base region 11 is formed in the trench 5, an interlayer insulating film 3 is formed on the surfaces of the base electrode 1 and the semiconductor chip, and a metal emitter electrode 2 which comes into ohmic contact with the emitter region 22 via a contact hole formed in the interlayer insulating film 3 is formed on the surface of the interlayer insulating film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a current control type power bipolar device.

[0002]

2. Description of the Related Art A vertical bipolar transistor will be described as a first conventional example. 16 and 17 are diagrams showing an electrode structure of a conventional vertical bipolar transistor, and FIG. 17 is a plan view showing an electrode pattern of the entire chip,
FIG. 16 is a cross-sectional view taken along the line segment AA ′ in FIG.
In FIG. 16, 81 is a base electrode, 82 is an emitter electrode, and 83 is an interlayer insulating film. Reference numeral 84 denotes a base region, which is in ohmic contact with the base electrode 81 via the contact region 88. Reference numeral 85 denotes an emitter region, which is in ohmic contact with the emitter electrode 82. Further, 86 is a collector region which is a substrate,
87 is a collector electrode in ohmic contact with the collector region 86. Further, as shown in FIG. 17, in a normal vertical bipolar transistor, the base electrode 8
1 and the emitter electrode 82F have a comb-tooth-shaped structure in which they are intertwined with each other on the chip. The emitter electrode 8
Since 2F has a rod-like shape as shown in the drawing, it may be called an emitter finger. Also,
82P is an emitter pad region, which is a wide metal region. Also, 82A is an emitter finger 8
It is a region for collecting a current from 2F to the emitter pad 82P, and will be called an emitter arm. The shape of this emitter arm 82A is the emitter pad 8
In order to collect current in sequence from the emitter fingers 82F farther from 2P, the wedge shape is inevitably shown in FIG. The semiconductor region below the emitter arm 82A and the emitter pad 82P is an inactive region in which a transistor structure cannot be formed.

Next, as another conventional example, the structure of a vertical MOS transistor will be described. FIG. 18 is a sectional view of a vertical MOS transistor. In FIG. 18, 91 is a conductive polysilicon gate electrode, 92 is a source electrode made of a metal film, 93 is an interlayer insulating film, 94 is a p-type channel region, and 95 is an n-type source region, which is in ohmic contact with the source electrode 92. are doing. And the p-type channel region 94
Also makes ohmic contact with the source electrode 92 via the p + type contact region 99. Further, 96 is a gate insulating film, 97 is an n-type drain region which is a substrate, and 98 is a drain electrode which makes ohmic contact with the drain region 97. As described above, in the vertical MOS transistor, as shown in FIG. 18, the source electrode 92 and the gate electrode 9 are
1 has a two-layer electrode structure, and the outermost surface of the transistor structure is covered with a film-shaped source electrode 92. The gate electrode 91 is composed of the gate insulating film 96 and the interlayer insulating film 9
3, and is also insulated from the substrate 97 and the source electrode 92. Although not shown in FIG. 18,
The gate electrode 91 is connected to the electrode on the surface of the wire-bondable gate pad in another region. Among the vertical MOS transistors having such a structure, there is one in which a part of the source electrode on the transistor region is used as a pad region for wire bonding. The pad region is usually formed by providing a thick oxide film on the surface of the semiconductor substrate other than the active region and forming a metal film region on the thick oxide film. It is also possible to bond directly. By using this method, it is not necessary to separately provide the source pad region, so that the chip area can be effectively utilized.

Next, the metal forming the electrode is generally aluminum or its alloy, and the wire is also made of aluminum or its alloy. Hereinafter, these will be simply referred to as aluminum. For wire bonding, a method is used in which an aluminum wire is pressed against the aluminum film in the pad area on the chip surface, and pressure is applied while applying ultrasonic waves to bond. In the structure of the vertical MOS transistor as shown in FIG. 18, since the lower layer of the two-layer electrode is composed of a relatively hard other crystal semiconductor,
Even if an ultrasonic wave or pressure is applied during wire bonding, the insulation between layers can be processed without breaking.

By adopting such a wire bonding method also in the vertical bipolar transistor which is the first conventional example, the chip area can be effectively utilized. However, implementation in a bipolar transistor has the following problems. That is, in the MOS transistor, a conductive polycrystalline semiconductor is used for the lower electrode. Even if a polycrystalline semiconductor is made to have conductivity by introducing impurities, it does not have the same conductivity as metal, but the gate electrode only needs to transmit the "potential" as a control signal, and the resistance of the electrode itself is not so low. However, since it works well, no problem occurs. Further, since the polycrystalline semiconductor is relatively hard, it is not destroyed by impact or load during wire bonding. However, in a bipolar transistor, the base electrode must supply "almost the same current value" to every corner of the active region, and therefore the electrode material needs to be a material having high conductivity such as metal. is there. However, there is a problem here. FIG.
9 and 20 are cross-sectional views for explaining this problem. 19 and 20, reference numeral 51 is a lower layer electrode metal, 52 is an upper layer electrode metal, 53 is an interlayer insulating film, and a thick arrow indicates a load during wire bonding. As shown in FIG. 19, when a two-layer electrode structure such as a MOS transistor is formed by two metal films, the metal is relatively soft, and therefore, deformation or deformation occurs as shown in FIG. 20 due to impact or load during wire bonding. , Interlayer insulating film 5
3 is easy to tear. As a countermeasure against this, it is possible to take measures such as strengthening the interlayer insulating film 53 so as to withstand impact, but at least at the present time, there is no technique that is commercially available.

[0006]

As described above, in the conventional vertical bipolar transistor electrode structure, when a two-layer structure such as the vertical MOS transistor electrode structure is formed, and wire bonding is performed thereon, Since the metal that is the electrode is soft, there is a problem that the lower layer electrode is deformed by the impact or load during bonding, and the interlayer insulating film is damaged.Therefore, it is difficult to effectively use the chip area. It was

The present invention has been made in order to solve the problems of the prior art as described above. Metals are used for both upper and lower electrodes, and the interlayer insulating film is damaged even when shocked during wire bonding. It is an object of the present invention to provide a semiconductor device having a two-layer electrode structure which is not exposed.

[0008]

In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the invention according to claim 1, a bipolar semiconductor chip having a main current region (for example, an emitter region) through which a main current flows and a current control region (for example, a base region) for controlling the main current are provided near the surface. In, a metal for a control electrode (for example, a base electrode) having a groove provided on the surface of the current control region and having ohmic contact with the current control region inside the groove.
And an insulating film on the surface of the control electrode metal and the semiconductor chip, and the surface of the insulating film is in ohmic contact with the main current region through a contact hole formed in the insulating film. It is configured to have a film-shaped main electrode metal (for example, an emitter electrode). It should be noted that this configuration corresponds to, for example, the embodiment of FIGS. 1 and 2 described later.

According to the second aspect of the invention,
An insulator is provided at a part of the interface between the groove and the metal for the control electrode, and a part of the interface is not in contact. Note that this configuration corresponds to, for example, the embodiment shown in FIG. 4 described later. In the invention according to claim 3, a part of the interface between the groove and the metal for the control electrode forms a Schottky junction.
This configuration corresponds to, for example, the embodiment shown in FIG. 3 described later. In the invention according to claim 4, the groove is formed in a stripe shape or a mesh shape. Note that this configuration corresponds to, for example, the embodiment of FIG. 10 or FIG. 11 described later. In the invention according to claim 5, a polycrystalline silicon region having a high impurity concentration is provided along the inner surface of the groove, and the control electrode metal is provided therein. Note that this configuration corresponds to, for example, the embodiment shown in FIG. 6 described later.

[0010]

According to the present invention, a groove is formed in a region for forming an ohmic contact with a metal electrode in a current control region (for example, a base region) near the surface of a semiconductor substrate, and control is performed only inside this groove. A metal for the electrode (for example, a base electrode) is formed. Then, an interlayer insulating film is provided thereon, and a film-shaped metal for a main electrode (for example, an emitter electrode) is formed thereon. According to this structure, even if an impact is applied during wire bonding, the load caused by the impact is not applied to the metal for the control electrode in the groove. Therefore, the metal for the lower control electrode is not deformed, and therefore the interlayer insulating film is not destroyed.

The current control region and the control electrode metal do not necessarily have to make ohmic contact over the entire surface. Therefore, as described in claim 2, an insulator (for example, the insulator 101 in FIG. 4) is provided at a part of the interface between the groove and the control electrode metal, and the current control region and the control electrode metal are in contact with each other. A structure in which a non-forming portion is provided, or a structure in which a Schottky junction (for example, a joint surface between 1 and 11 in FIG. 3) is formed in a part of an interface between the groove and the control electrode metal as described in claim 3. By doing so, the degree of freedom in design can be improved. Further, as described in claim 4, by making the shape of the groove a stripe shape or a mesh shape, the area of the control electrode can be increased and its resistance value can be lowered. Further, as described in claim 5, the region for ohmic contact between the current control region and the control electrode metal (for example, the p + type region 111 in FIG. 1) is not provided outside the groove. As a region, a polycrystalline silicon region having a high impurity concentration (for example, 1A in FIG. 6) is provided along the inner surface of the groove, and a metal for a control electrode (for example, 1B in FIG. 6) is provided therein to form a multilayer structure. As a result, the diffusion depth of the region for making the ohmic contact can be reduced.

[0012]

EXAMPLES The present invention will be described in detail below based on examples. 1 and 2 are views showing a first embodiment of the present invention. FIG. 1 is a sectional view and FIG. 2 is a partial sectional perspective view. This embodiment is an example in which the present invention is applied to a vertical bipolar transistor. In FIG. 1 and FIG. 2, reference numeral 1 denotes a base electrode which serves as a lower layer electrode and is made of metal and has a base region
It is embedded in the groove 5 formed on the surface of the No. 1. Further, 2 is an emitter electrode which serves as an upper layer electrode and is made of metal. 3 is an interlayer insulating film, 4 is a collector region which is a semiconductor substrate, 5 is a groove formed in the vicinity of the surface of the semiconductor substrate, and 33 is an insulating film used as a mask during manufacturing.
Reference numeral 111 is a p + type region for making ohmic contact between the base region 11 and the base electrode 1. Reference numeral 22 denotes an n + type emitter region, which makes ohmic contact with the emitter electrode 2 through a contact hole provided in the interlayer insulating film 3. Further, 14 is a collector electrode.

Further, H is the width of the groove 5, D is the depth of the groove 5, and t
Is the thickness of the interlayer insulating film 3.

Further, as shown in FIG. 2, the base electrode 1
Is connected to the surface electrode 10 in a region different from the cross section of FIG. 1, and is connected to a pad region (not shown) for bonding the base electrode wire.

Next, the operation will be described. FIG. 7 is a cross-sectional view showing a load state during wire bonding in the structure of FIG. 1, and corresponds to FIG. In FIG. 7, thick arrows indicate how the load is applied. As shown in FIG. 7, in the structure of this embodiment, the load is not applied to the metal (base electrode 1) in the groove but is distributed to the semiconductor substrate sandwiching it. Therefore, the metal electrode in the lower layer is not deformed, and therefore the interlayer insulating film 3 is not destroyed, so that the active region (transistor formation region) can be safely bonded. In FIG. 7, the p + type region 111 is not shown.

Next, FIG. 3 is a second embodiment of the present invention and is a sectional view of the peripheral portion of the groove. In the structure of FIG. 3, the p + -type region 111 for making ohmic contact between the base region 11 and the base electrode 1 is not provided on the entire inner surface of the groove 5, but a part thereof (near the bottom surface of the groove in FIG. 3). It is provided only for. In this case, the base region 11 and the base electrode 1
Makes ohmic contact only with the portion of the p + type region 111, and the junction surface between the base region 11 and the base electrode 1 in the portion where the p + type region 111 is not provided forms a Schottky junction. Of course, the p + type region 111 may be provided in a part other than the bottom surface.

Next, FIG. 4 is a third embodiment of the present invention, showing a sectional view of the peripheral portion of the groove. The structure of Figure 4 is p +
The mold region 111 is provided only on the bottom surface of the groove 5, and the insulator 101 is provided on the other portions. In this case, the base region 11 and the base electrode 1 make ohmic contact only with the p + -type region 111 on the bottom surface of the groove, and the other portions are insulated. In the configuration of FIG. 1, the p + type region 111 is provided on the entire inner surface of the groove 5 so that the base region 11 and the base electrode 1 are in ohmic contact over the entire surface. As shown in FIG. 3 or FIG. 4, it may be configured such that only a part thereof makes ohmic contact and the other part forms an insulating or Schottky junction. By doing so, the degree of freedom in design can be improved.

Next, FIG. 5 is a fourth embodiment of the present invention and is a sectional view of the peripheral portion of the groove. The structure of FIG.
The metal inside (base electrode 1) does not fill the entire groove, and the metal surface is slightly recessed from the surface of the semiconductor substrate. Even with such a structure, there is no problem as long as the connection with the surface electrode 10 of FIG. 2 can be established.

Next, FIG. 6 is a fifth embodiment of the present invention and is a sectional view of the peripheral portion of the groove. The structure of FIG. 6 has a groove 5
It has a multi-layer structure inside. For example, if 1A is a high impurity concentration p + type polycrystalline silicon and 1B is a metal such as aluminum, the p + type polycrystalline silicon 1A can be used instead of the p + type region 111. With such a configuration, it is not necessary to provide the p + type region 111 outside the groove 5, so that the diffusion depth can be reduced. Further, in the same structure as in FIG. 6, in order to prevent physical interaction such as mutual diffusion between the substrate silicon and aluminum, 1A is titanium, titanium nitride, titanium silicide, etc., and 1B is aluminum or aluminum alloy. You can also do it. That is, in general, when depositing a metal such as aluminum on the silicon surface, the silicon surface is exposed to a high temperature and has a high solubility for the deposited metal, so that the substrate silicon is eluted into the metal film. The performance of the semiconductor device may be deteriorated. In order to prevent such a problem, an alloy containing a small amount of silicon in aluminum in advance may be used. However, even in that case, when the temperature returns to room temperature, another problem may occur such that silicon in the alloy is deposited on the silicon interface of the substrate to increase the contact resistance. In that respect, the above-mentioned configuration is used as a part of general planar technology as an effective method which does not cause either of the problems. It is also possible to provide a three-layer structure in which a p + type polycrystalline silicon film is provided inside the groove, a titanium film is provided inside the groove, and a metal such as aluminum is provided inside the titanium film.

Next, FIG. 8 is a sixth embodiment of the present invention and is a sectional view of the peripheral portion of the groove. In the structure shown in FIG. 8, the groove has a V-shaped cross section. FIG. 9 is a seventh embodiment of the present invention and shows a sectional view of the peripheral portion of the groove. In the structure shown in FIG. 9, the cross-sectional shape of the groove is semicircular. As shown in FIGS. 8 and 9, the cross-sectional shape of the groove is not limited to the box shape as shown in FIG. 1, but the same effect can be obtained with various shapes. There are naturally effective conditions for the depth D, the width H of the groove 5 and the thickness t of the interlayer insulating film 3 covering the groove 5 as described above. The optimum conditions are semiconductor substrate,
It is determined by the mechanical mechanical properties of the lower electrode metal 1 and the interlayer insulating film 3, and the thickness of the upper electrode metal 2.

Next, an example of a manufacturing process for realizing the structure of the present invention will be described. 12 to 15 are cross-sectional views showing the manufacturing process. First, on the surface of the semiconductor substrate 4,
The insulating film 33 is formed by oxidation, and a window for forming the groove 5 is formed in the insulating film 33. By using the insulating film 33 as a mask, the groove 5 is etched by anisotropic etching to form the shape shown in FIG. Next, the metal 1 is deposited on the surface of the substrate by the CVD method or the like so that the groove 5 is filled with the metal 1 (FIG. 13). At this time, the film thickness of the metal 1 to be deposited should ideally be half the width of the groove 5. FIG.
Shows a state in which the filling of the groove is ensured by depositing a little more than this. The metal 1 may be aluminum, titanium, tungsten, an alloy thereof, or metal silicide. Alternatively, a composite of a plurality of conductive materials may be used. Next, as shown in FIG. 14, etching back is performed so that the metal 1 remains only inside the groove 5. Next, as shown in FIG. 15, an insulating film 3 such as PSG is deposited on the surface by the CVD method or the like. Note that a TEOS film or the like may be applied to planarize the upper surface of the groove. Further, by depositing an upper metal film (not shown) thereon and patterning it, the structure of the groove and the electrode of FIG. 1 can be obtained. The base region 11
And p for making ohmic contact with the base electrode 1
Although the + type region 111 is not shown, in order to form the p + type region 111, p-type impurities are diffused into the inner wall of the groove by vapor phase diffusion or ion implantation in the state of FIG. It can be formed by

Next, the dimensions of the electrode wiring will be described.
In the base electrode of the bipolar transistor, it is necessary to reduce the wiring resistance in order to supply the base current with low resistance. As in the prior art, in a wiring forming method that does not use a groove, in order to reduce the wiring resistance, a method of increasing the sectional area of the wiring includes (1) a method of increasing the thickness of the wiring and (2) a method of forming the wiring. There is a method to widen the width. But,
These methods have the following problems. That is, (1) in the method of increasing the thickness of the wiring, the time for depositing the metal film increases, the time for shaping the metal film by etching increases, a resist that can withstand the long-time etching is required, etc. There is a disadvantage. (2) The method of widening the width of the wiring has a problem that the active area that can be used as a transistor on the chip is reduced.

In that respect, in the structure of the present invention, in order to embed a metal in a groove having a width H, in principle, a metal having a thickness H / 2 is formed on the chip surface regardless of the depth of the groove. It is sufficient to use the conditions for uniformly depositing. That is, the groove may be deepened in order to increase the cross-sectional area of the electrode. For example,
When forming a base electrode having a cross section of 4 μm × 8 μm, according to the conventional method, a metal film having a thickness of 4 μm is formed and shaped into a width of 8 μm. On the other hand, in the case of the present invention, a groove having a depth of 8 μm is formed in a region having a width of 4 μm,
The groove can be filled by uniformly depositing a metal film having a minimum thickness of 2 μm on the chip surface. In this case, the area used as the wiring is halved compared to the conventional one, and the thickness of the deposited metal film is also halved. Therefore, the chip area and the manufacturing cost can be significantly reduced. Further, when it is desired to reduce the resistance value of the electrode wiring, the number of grooves may be increased, but even in that case, the electrode area is significantly smaller than that of the planar electrode structure.

When increasing the number of grooves, for example,
The arrangement shown in FIG. 10 or FIG. 11 may be used. FIG. 10 is an eighth embodiment of the present invention and shows a plan view of the groove pattern. In FIG. 10, a plurality of grooves are provided in a stripe shape. FIG. 11 is a ninth embodiment of the present invention and shows a plan view of the groove pattern. In FIG. 11, a plurality of grooves are provided in a mesh shape. As described above, the resistance value of the electrode wiring can be significantly reduced by providing the plurality of grooves.

In the above description, the case where the present invention is applied to the surface electrode of the vertical bipolar transistor is illustrated, but other current control type devices such as a thyristor, a surface gate type SIT, or a unipolar JF is used.
It can be widely applied to ET and surface gate type electrostatic induction devices.

[0026]

As described above, according to the present invention, since no load is applied to the electrode metal in the groove during bonding, the lower electrode is not deformed, and the interlayer insulating film is damaged. There is no. Therefore, even if the wiring electrode is made of a soft metal, wire bonding can be directly performed on the active region, so that the chip area can be effectively utilized. Further, when the wiring cross-sectional area is increased for the purpose of reducing the wiring resistance, it can be realized with a narrower width as compared with the conventional method, and the amount of wasted wiring metal is reduced at the time of manufacturing, thus reducing the manufacturing cost. The effect that can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional perspective view of the first embodiment of the present invention.

FIG. 3 is a sectional view of a second embodiment of the present invention.

FIG. 4 is a sectional view of a third embodiment of the present invention.

FIG. 5 is a sectional view of a fourth embodiment of the present invention.

FIG. 6 is a sectional view of a fifth embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining an operation when a load is applied to the structure of FIG.

FIG. 8 is a sectional view of a sixth embodiment of the present invention.

FIG. 9 is a sectional view of a seventh embodiment of the present invention.

FIG. 10 is a plan view of the groove pattern according to the eighth embodiment of the present invention.

FIG. 11 is a plan view of a groove pattern according to a ninth embodiment of the present invention.

12 is a cross-sectional view showing a part of the manufacturing process for realizing the structure of FIG.

13 is a cross-sectional view showing another part of the manufacturing process for realizing the structure of FIG.

14 is a cross-sectional view showing another part of the manufacturing process for realizing the structure of FIG.

15 is a cross-sectional view showing another part of the manufacturing process for realizing the structure of FIG.

16 is a diagram showing an electrode structure of a conventional vertical bipolar transistor, which is a cross-sectional view taken along line AA ′ in FIG.

FIG. 17 is a diagram showing an electrode structure of a conventional vertical bipolar transistor, and a plan view showing an electrode pattern of the entire chip.

FIG. 18 is a sectional view of a conventional vertical MOS transistor.

FIG. 19 is a cross-sectional view for explaining the deformation of the electrode structure due to the load of wire bonding, showing a normal state.

FIG. 20 is a cross-sectional view for explaining the deformation of the electrode structure due to the load of wire bonding, showing a state of being deformed by the load.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Base electrode which becomes a lower layer electrode 11 ... Base region 2 ... Emitter electrode which becomes an upper layer electrode 14 ... Collector electrode 3 ... Interlayer insulating film 22 ... N + type emitter region 4 ... Collector region 33 ... Insulating film used as a mask during manufacturing 5 ... Groove 101 ... Insulator 10 ... Surface electrode 111 ... P + type region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/73 H01L 29/72

Claims (5)

[Claims] 1. A bipolar semiconductor chip having a main current region in which a main current flows and a current control region for controlling the main current in the vicinity of the surface, wherein a groove is formed on the surface of the current control region. Has a control electrode metal in ohmic contact with the current control region, has an insulating film on the surface of the control electrode metal and the semiconductor chip, on the surface of the insulating film, to the insulating film A semiconductor device, comprising: a film-shaped metal for a main electrode which makes ohmic contact with the main current region through the formed contact hole. 2. A semiconductor device according to claim 1, wherein an insulator is present at a part of an interface between the groove and the control electrode metal. 3. The semiconductor device according to claim 1, wherein a part of an interface between the groove and the control electrode metal forms a Schottky junction. 4. The semiconductor device according to claim 1, wherein the groove is provided in a stripe shape or a mesh shape. 5. A polycrystalline silicon region having a high impurity concentration is provided along the inner surface of the groove, and the control electrode metal is provided therein. The semiconductor device described.