JPH088398B2 - Low dielectric constant substrate - Google Patents

Low dielectric constant substrate

Info

Publication number
JPH088398B2
JPH088398B2 JP63262164A JP26216488A JPH088398B2 JP H088398 B2 JPH088398 B2 JP H088398B2 JP 63262164 A JP63262164 A JP 63262164A JP 26216488 A JP26216488 A JP 26216488A JP H088398 B2 JPH088398 B2 JP H088398B2
Authority
JP
Japan
Prior art keywords
dielectric constant
porous layer
substrate
low dielectric
dense
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63262164A
Other languages
Japanese (ja)
Other versions
JPH02106991A (en
Inventor
和吉 塚本
康信 米田
行雄 坂部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP63262164A priority Critical patent/JPH088398B2/en
Publication of JPH02106991A publication Critical patent/JPH02106991A/en
Publication of JPH088398B2 publication Critical patent/JPH088398B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、例えば電子回路用基板等に用いられる低
誘電率基板に関する。
Description: TECHNICAL FIELD The present invention relates to a low dielectric constant substrate used for, for example, an electronic circuit substrate.

〔従来の技術〕[Conventional technology]

電子回路の動作周波数の高周波化および高集積化に伴
い、低誘電率の基板が求められている。
As the operating frequency of electronic circuits increases and the degree of integration increases, a substrate having a low dielectric constant is required.

これは、当該基板中を進む信号の伝播遅延時間τは、
光速をcとすると、 で表され、誘電率εが大きいと、遅延時間が大きくなっ
て高速動作に支障を来たすようになるからである。ま
た、誘電率が大きいと、配線間の浮遊容量が大きくなる
ため、配線密度を高めることができなくなるからであ
る。
This is because the propagation delay time τ of the signal traveling in the substrate is
If the speed of light is c, This is because if the permittivity ε is large, the delay time becomes large and the high-speed operation is hindered. Further, if the dielectric constant is large, the stray capacitance between the wirings becomes large, so that the wiring density cannot be increased.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

しかしながら、従来の緻密なセラミックスでは、SiO2
系ガラスセラミックスのε=3.8が誘電率の下限であっ
た。
However, with conventional dense ceramics, SiO 2
The lower limit of the dielectric constant was ε = 3.8 for the glass ceramics.

そこでこの発明は、これよりも更に誘電率を小さくし
て、信号の伝播遅延時間の短縮および高密度配線化を可
能にした低誘電率基板を提供することを目的とする。
Therefore, an object of the present invention is to provide a low dielectric constant substrate which has a smaller dielectric constant than that of the present invention, which enables a reduction in signal propagation delay time and high density wiring.

〔課題を解決するための手段〕[Means for solving the problem]

この発明の低誘電率基板は、セラミックスから成り1
層以上に積層された多孔質層の上下主面および端面の全
てがセラミックスから成る緻密質層で覆われており、か
つ多孔質層の部分および緻密質層の表面に導体路が当該
各層に沿ってそれぞれ形成されていてしかも当該導体路
がスルーホールあるいはバイアホールを介して互いに電
気的に接続されていることを特徴とする。
The low dielectric constant substrate of the present invention is made of ceramics 1
All of the upper and lower main surfaces and end surfaces of the porous layer laminated in more than two layers are covered with the dense layer made of ceramics, and the conductor path is formed along the porous layer part and the surface of the dense layer. And the conductor paths are electrically connected to each other through a through hole or a via hole.

〔作用〕[Action]

多孔質層は、低誘電率である気孔を多く含むため、緻
密なセラミックスよりも誘電率が小さくなると共に、そ
のような低誘電率の多孔質層を含む基板全体としての誘
電率も小さくなる。
Since the porous layer contains a large number of pores having a low dielectric constant, the dielectric constant becomes smaller than that of dense ceramics, and the dielectric constant of the whole substrate including such a porous layer having a low dielectric constant also becomes small.

しかも、多孔質層の上下主面および端面の全てを緻密
質層で覆っていて多孔質層が露出していないので、多孔
質層を含んでいても基板の耐侯性が非常に高い。
Moreover, since the upper and lower main surfaces and the end surfaces of the porous layer are all covered with the dense layer and the porous layer is not exposed, the weather resistance of the substrate is very high even if the porous layer is included.

〔実施例〕〔Example〕

第1図は、この発明の一実施例に係る低誘電率基板を
示す縦断面図である。
FIG. 1 is a vertical sectional view showing a low dielectric constant substrate according to an embodiment of the present invention.

この低誘電率基板2は、複数の多孔質層4と、それら
の上下両側に1層ずつ設けられた緻密質層6とが互いに
積層されて成る。多孔質層4と緻密質層6は、いずれも
セラミックスから成る。
The low dielectric constant substrate 2 is formed by laminating a plurality of porous layers 4 and a dense layer 6 provided on each of the upper and lower sides of the porous layers 4 one by one. Both the porous layer 4 and the dense layer 6 are made of ceramics.

もっとも、多孔質層4の層数は1層以上であれば任意
であり、また上下の緻密質層6は必要に応じて複数層に
しても良い。上下の緻密質層6の厚みは等しいことが望
ましい。これは等しくないと焼成時の収縮による応力の
バランスがとれず、基板に反りが発生するからである。
However, the number of layers of the porous layer 4 is arbitrary as long as it is 1 or more, and the upper and lower dense layers 6 may be plural layers as necessary. It is desirable that the upper and lower dense layers 6 have the same thickness. This is because if they are not equal, the stress due to shrinkage during firing cannot be balanced, and the substrate warps.

そして、多孔質層4の層間や内部に導体路8aが、また
緻密質層6の表面に導体路8bが、各層4、6に沿ってそ
れぞれ形成されていて、両者がスルーホール10を介して
(即ちスルーホール10内に充填した導体によって)電気
的に接続されている。
Conductor paths 8a are formed between and inside the porous layer 4, and conductor paths 8b are formed on the surface of the dense layer 6 along the layers 4 and 6, respectively, and the conductor paths 8b are formed through the through holes 10. They are electrically connected (i.e. by the conductor filling the through holes 10).

この内部の導体路8aおよび表面の導体路8bのパターン
やスルーホールの位置等も任意であり、必要とする回路
構成等に応じて決めれば良い。
The pattern of the internal conductor path 8a and the surface conductor path 8b, the positions of the through holes, and the like are also arbitrary, and may be determined according to the required circuit configuration and the like.

また、上記多孔質層4の気孔率は、70体積%以下にす
るのが好ましい。これは、気孔率が70体積%を越える
と、多孔質層4の部分に形成された導体路8aが変形した
り断線したりして、伝送特性を損なう恐れが大になるか
らである。
The porosity of the porous layer 4 is preferably 70% by volume or less. This is because if the porosity exceeds 70% by volume, the conductor path 8a formed in the porous layer 4 may be deformed or broken, and the transmission characteristics may be impaired.

上記低誘電率基板2においては、多孔質層4は、低誘
電率である気孔を多く含むため、緻密なセラミックスよ
りも誘電率が小さくなる。
In the low dielectric constant substrate 2, since the porous layer 4 contains many pores having a low dielectric constant, the dielectric constant is smaller than that of dense ceramics.

また、そのような低誘電率の多孔質層4を含む基板全
体としての誘電率も小さくなる。
Further, the dielectric constant of the whole substrate including such a low dielectric constant porous layer 4 is also reduced.

その結果、内外の導体路8a、8b、特に内部の導体路8a
を伝わる信号の伝播遅延時間を短縮することができる。
As a result, the inner and outer conductor paths 8a, 8b, especially the inner conductor path 8a
It is possible to reduce the propagation delay time of the signal transmitted through the.

また、緻密質層だけから成る基板に比べて、誘電率が
小さいぶん浮遊容量を減らすことができるので、高密度
配線化が可能になる。
Further, since the stray capacitance can be reduced as much as the dielectric constant is smaller than that of the substrate including only the dense layer, high density wiring can be realized.

しかも、多孔質層4の上下両側には緻密質層6をそれ
ぞれ設けているので、全体が多孔質層である場合に比べ
て耐侯性(耐湿性)を高めることができる。また、表面
の導体路8bの形成や電子部品の半田付け等も容易にな
る。
Moreover, since the dense layers 6 are provided on both the upper and lower sides of the porous layer 4, the weather resistance (moisture resistance) can be enhanced as compared with the case where the entire porous layer is a porous layer. In addition, the formation of the conductor path 8b on the surface, the soldering of electronic components, and the like are facilitated.

更に、第1図中に2点鎖線で示すように、基板2の端
面にも緻密質層12を設けており、その結果、多孔質層4
の露出が完全に無くなるので、耐侯性が一層向上する。
Further, as shown by a chain double-dashed line in FIG. 1, a dense layer 12 is also provided on the end face of the substrate 2, and as a result, the porous layer 4 is formed.
Since the exposure of is completely eliminated, the weather resistance is further improved.

また、緻密質層6の表面に出たスルーホール10の部分
を緻密な絶縁体で覆っても良く、そのようにすれば、更
に耐侯性ひいては信頼性を高めることができる。
Further, the through-holes 10 exposed on the surface of the dense layer 6 may be covered with a dense insulator, which can further improve weather resistance and reliability.

次に、上記のような構造の低誘電率基板の製造方法の
一例を説明する。
Next, an example of a method of manufacturing the low dielectric constant substrate having the above structure will be described.

セラミック材料には、一例として、同一出願人が別途
提案している低温焼結可能なものを用いた。即ち、コー
ジェライト(例えば特開昭61−234128号公報参照)が50
〜95重量%、B2O3が5〜20重量%およびSiO2が1〜46重
量%から成る主成分に対して、NiOおよびCuOの少なくと
も一方を15重量%以下添加して混合した原料を準備し、
これを仮焼し、粉砕して粉末セラミックを得た。
As the ceramic material, as an example, a low temperature sinterable material which was separately proposed by the same applicant was used. That is, cordierite (see, for example, JP-A-61-234128) has a 50
~ 95 wt%, B 2 O 3 5 ~ 20 wt% and SiO 2 1 ~ 46 wt% to the main component, at least one of NiO and CuO was added by 15 wt% or less, and mixed raw material Prepare,
This was calcined and pulverized to obtain a powder ceramic.

そして、得られた粉末セラミックにアクリル系バイン
ダーを添加、混合し、ドクターブレード法により第1の
セラミックグリーンシートを作製した。このグリーンシ
ートは、焼成後に緻密質層となるものである。
Then, an acrylic binder was added to and mixed with the obtained powder ceramic, and a first ceramic green sheet was produced by the doctor blade method. This green sheet becomes a dense layer after firing.

また、上記粉末セラミックに、微粉末セルロースを体
積比で2.5倍加え、同じくアクリル系バインダーを添加
し、ドクターブレード法により第2のセラミックグリー
ンシートを作製した。このグリーンシートは、焼成後に
多孔質層になるものである。
Further, fine powder cellulose was added to the above powder ceramic in a volume ratio of 2.5 times, an acrylic binder was also added thereto, and a second ceramic green sheet was prepared by a doctor blade method. This green sheet becomes a porous layer after firing.

そして、上記のようにして得られた第1および第2の
セラミックグリーンシートの所要枚数の所要位置にスル
ーホールを形成した後、所要のセラミックグリーンシー
トの表面およびスルーホールの部分に導体ペーストとし
てAg−Pdペーストを印刷した。
Then, after forming through holes at the required positions of the required number of the first and second ceramic green sheets obtained as described above, Ag as a conductor paste is formed on the surfaces of the required ceramic green sheets and the through holes. -Printed Pd paste.

次いで、上記のようにな第2のセラミックグリーンシ
ートが間に、その上下に第1のセラミックグリーンシー
トが位置するように(即ち第1図のような配置になるよ
うに)積層し、圧着し、そして大気中で980℃前後の温
度で焼成を行った。その結果、第1図に示したような構
造の低誘電率基板が得られた。ちなみに、第2のセラミ
ックグリーンシートの焼成によって多孔質層が得られる
のは、当該グリーンシート中の微粉末セルロース等が焼
失してその後に気孔が残るからである。
Then, as described above, the second ceramic green sheets are laminated between them so that the first ceramic green sheets are located above and below (that is, arranged as shown in FIG. 1) and pressure-bonded. Then, firing was performed in the atmosphere at a temperature of around 980 ° C. As a result, a low dielectric constant substrate having the structure shown in FIG. 1 was obtained. By the way, the reason why the porous layer is obtained by firing the second ceramic green sheet is that the finely powdered cellulose or the like in the green sheet is burned and the pores remain after that.

更にこの例では、上記のようにして得られた基板の端
面に絶縁体ペーストを印刷し焼付けて、多孔質層の露出
を完全に防止した。この絶縁体ペーストは、上記と同様
の粉末セラミックにアクリル系バインダーを添加、混合
し、溶剤で粘度調整して作った。その焼付け温度は、基
板の焼成温度と殆ど同じである。
Further, in this example, an insulating paste was printed and baked on the end surface of the substrate obtained as described above to completely prevent the porous layer from being exposed. This insulator paste was prepared by adding and mixing an acrylic binder to the same powder ceramic as above and adjusting the viscosity with a solvent. The baking temperature is almost the same as the baking temperature of the substrate.

上記のようにして得られた多孔質層の気孔率は70体積
%であり、また多孔質層の部分に形成された回路(コン
デンサ部分)からその誘電率を求めるとε=2.0であ
り、緻密質である場合の半分以下であった。また、従来
のSiO2系ガラスセラミックスに比べても半分に近い値で
ある。
The porosity of the porous layer obtained as described above is 70% by volume, and the dielectric constant of the circuit (capacitor part) formed in the porous layer part is ε = 2.0, which is It was less than half that of quality. In addition, the value is almost half that of the conventional SiO 2 glass ceramics.

尚、更に信頼性を高めるために、緻密質層表面のスル
ーホール部に、上記のような絶縁体ペーストを塗布、焼
付けても良いのは前述の通りである。
As described above, the insulating paste as described above may be applied and baked on the through-hole portion on the surface of the dense layer in order to further enhance the reliability.

また、導体ペーストにはCuペーストを用いることもで
きるが、この場合はH2O/N2(即ち窒素中に水蒸気を含
む)雰囲気中で焼成するものとする。
A Cu paste can also be used as the conductor paste, but in this case, the firing is performed in an atmosphere of H 2 O / N 2 (that is, water vapor is contained in nitrogen).

また、端面封止には、熱膨張係数が基板のそれぞれに
近く、焼付け温度が基板の焼成温度以下のものであれ
ば、ガラスペーストを用いても良い。
Further, for the end face sealing, glass paste may be used as long as it has a thermal expansion coefficient close to that of each substrate and a baking temperature is equal to or lower than the baking temperature of the substrate.

〔発明の効果〕〔The invention's effect〕

以上のようにこの発明によれば、多孔質層の部分での
誘電率が緻密なセラミックスよりも小さくなり、ひいて
はそのような低誘電率の多孔質層を含む基板全体として
の誘電率も小さくなる。
As described above, according to the present invention, the dielectric constant of the porous layer portion is smaller than that of the dense ceramics, and the dielectric constant of the entire substrate including such a low dielectric constant porous layer is also reduced. .

その結果、内外の導体路、特に内部の導体路を伝わる
信号の伝播遅延時間を短縮することができる。
As a result, it is possible to reduce the propagation delay time of a signal transmitted through the inner and outer conductor paths, particularly the inner conductor path.

また、緻密質層だけから成る基板に比べて、誘電率が
小さぶん浮遊容量を減らすことができるので、高密度配
線化が可能になる。特に、内部の多孔質層の部分での浮
遊容量の低減効果が大きいので、内部配線の一層の高密
度配線化が可能になる。
In addition, since the dielectric constant is small and the stray capacitance can be reduced as compared with the substrate including only the dense layer, high density wiring can be realized. In particular, since the effect of reducing the stray capacitance in the internal porous layer portion is great, it is possible to further increase the internal wiring density.

しかも、多孔質層の上下主面および端面の全てを緻密
質層で覆っていて多孔質層が露出していないので、多孔
質層を含んでいても基板の耐侯性が非常に高い。
Moreover, since the upper and lower main surfaces and the end surfaces of the porous layer are all covered with the dense layer and the porous layer is not exposed, the weather resistance of the substrate is very high even if the porous layer is included.

また、多孔質層の表面を緻密質層で覆っていて表面が
緻密なので、表面の導体路の形成が容易になると共に、
表面に電子部品を載せて半田付けする場合に溶けた半田
が基板中に浸透するのを防ぐことができ、電子部品の半
田付けによる実装も容易になる。
Further, since the surface of the porous layer is covered with a dense layer and the surface is dense, it is easy to form the conductor path on the surface,
When an electronic component is placed on the surface and soldered, the melted solder can be prevented from penetrating into the substrate, and the electronic component can be easily mounted by soldering.

【図面の簡単な説明】[Brief description of drawings]

第1図は、この発明の一実施例に係る低誘電率基板を示
す縦断面図である。 2……実施例に係る低誘電率基板、4……多孔質層、6
……緻密質層、8a,8b……導体路、10……スルーホー
ル。
FIG. 1 is a vertical sectional view showing a low dielectric constant substrate according to an embodiment of the present invention. 2 ... Low dielectric constant substrate according to example, 4 ... Porous layer, 6
...... Dense layers, 8a, 8b …… Conductor paths, 10 …… Through holes.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】セラミックスから成り1層以上に積層され
た多孔質層の上下主面および端面の全てがセラミックス
から成る緻密質層で覆われており、かつ多孔質層の部分
および緻密質層の表面に導体路が当該各層に沿ってそれ
ぞれ形成されていてしかも当該導体路がスルーホールあ
るいはバイアホールを介して互いに電気的に接続されて
いる低誘電率基板。
1. A porous layer, which is made of ceramics and is laminated in one or more layers, has upper and lower main surfaces and end faces all covered with a dense layer made of ceramics, and the porous layer portion and the dense layer are A low dielectric constant substrate in which conductor tracks are formed on the surface along the respective layers, and the conductor tracks are electrically connected to each other through through holes or via holes.
JP63262164A 1988-10-17 1988-10-17 Low dielectric constant substrate Expired - Lifetime JPH088398B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63262164A JPH088398B2 (en) 1988-10-17 1988-10-17 Low dielectric constant substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63262164A JPH088398B2 (en) 1988-10-17 1988-10-17 Low dielectric constant substrate

Publications (2)

Publication Number Publication Date
JPH02106991A JPH02106991A (en) 1990-04-19
JPH088398B2 true JPH088398B2 (en) 1996-01-29

Family

ID=17371952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63262164A Expired - Lifetime JPH088398B2 (en) 1988-10-17 1988-10-17 Low dielectric constant substrate

Country Status (1)

Country Link
JP (1) JPH088398B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2587596B2 (en) * 1993-09-21 1997-03-05 松下電器産業株式会社 Circuit board connecting material and method for manufacturing multilayer circuit board using the same
JP2002265288A (en) * 2001-03-05 2002-09-18 Otsuka Chem Co Ltd Dielectric ceramic foamed body

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6317590A (en) * 1986-07-10 1988-01-25 旭硝子株式会社 Composite ceramic board
JPS63112473A (en) * 1986-10-28 1988-05-17 太陽誘電株式会社 Manufacture of ceramic substrate

Also Published As

Publication number Publication date
JPH02106991A (en) 1990-04-19

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