JPH05235550A - Low permittivity glass ceramic multilayer circuit board and manufacture thereof - Google Patents
Low permittivity glass ceramic multilayer circuit board and manufacture thereofInfo
- Publication number
- JPH05235550A JPH05235550A JP3354792A JP3354792A JPH05235550A JP H05235550 A JPH05235550 A JP H05235550A JP 3354792 A JP3354792 A JP 3354792A JP 3354792 A JP3354792 A JP 3354792A JP H05235550 A JPH05235550 A JP H05235550A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- dielectric constant
- ceramic
- wiring board
- low dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【従来の技術】従来、この種の低誘電率ガラスセラミッ
ク多層配線基板は、図２に示すような断面構造を有して
おり、低誘電率材料より成るセラミック層１１と、低抵
抗かつ低融点金属（例えば、金、銀、銀パラジウム、銅
等）によるヴィアホール部１２、および配線パターン１
３より構成されていた。2. Description of the Related Art Conventionally, a low dielectric constant glass ceramic multilayer wiring board of this type has a cross-sectional structure as shown in FIG. 2 and has a ceramic layer 11 made of a low dielectric constant material, a low resistance and a low melting point. Via hole portion 12 made of metal (for example, gold, silver, silver palladium, copper, etc.) and wiring pattern 1
It was composed of three.
【０００２】このような低誘電率ガラスセラミック多層
配線基板の製造方法は、まず、ホウケイ酸系ガラスを５
０〜７０ｗｔ％，コーディエライト系を１５〜３０ｗｔ
％，石英ガラスを１０〜２０ｗｔ％混合した粉末を、ブ
チラール系バインダー及び有機溶剤と共に混合攪拌して
スラリー状にし、これをキャリアフィルム上に、ドクタ
ーブレード法により所定の膜厚となるようキャスティン
グし、乾燥させてグリーンシートとなし、こうして得ら
れたグリーンシートに、パンチとダイスを使って、所定
のピッチにスルーホールを作孔して、ヴィアホール部１
２を形成し、次に、前記ヴィアホール部１２に、低融点
金属からなる導体ペーストをスクリーン印刷法により埋
め込み、また、このとき同様にして、配線パターン１３
を厚膜印刷し、以上のようにして、グリーンシート上に
メタライズを施した後、これらのシートを予め定められ
た順序に従って、所定の枚数を精度良く積層して熱圧着
後、約９００℃で焼成することにより低誘電率ガラスセ
ラミック多層配線基板を得た。In a method of manufacturing such a low dielectric constant glass-ceramic multilayer wiring board, first, a borosilicate glass is used to
0 ~ 70wt%, cordierite system 15 ~ 30wt%
%, Powder of 10 to 20 wt% of quartz glass is mixed and stirred with a butyral-based binder and an organic solvent to form a slurry, which is cast on a carrier film by a doctor blade method to have a predetermined film thickness, After being dried to form a green sheet, through holes are formed in the green sheet thus obtained at a predetermined pitch by using a punch and a die, and the via hole portion 1 is formed.
2, a conductor paste made of a low melting point metal is embedded in the via hole portion 12 by a screen printing method, and at the same time, the wiring pattern 13 is formed.
After thick film printing and metallizing on the green sheets as described above, a predetermined number of these sheets were precisely laminated in accordance with a predetermined order, and after thermocompression bonding, at about 900 ° C. A low dielectric constant glass-ceramic multilayer wiring board was obtained by firing.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の低誘電
率ガラスセラミック多層配線基板においては、半導体素
子を実装するための基板の材料としてのガラスセラミッ
クの誘電率が、信号の高速化に対して重要なパラメータ
となり、信号の伝搬速度νと材料の比誘電率εrとの間
に成り立つ次の関係 ν＝ｃ／（εr）1/2 （ここでｃは光速をあ
らわす）によって、比誘電率εr が小なるほど信号の伝
搬速度νが大となって有利であるが、他方基板の機械的
強度は図４に示すように、ガラスセラミック基板の比誘
電率が小なる程その機械的強度が低下して、アルミナを
主成分とした基板に対して２０〜７０％の強度を有する
に過ぎない。そのため、後工程で基板表面に高密度の微
細配線を形成したときに、メッキ応力によってクラック
が発生したり、基板裏面にろう付けするＩ／Ｏピンの接
着部の強度の劣下を招いて、基板の信頼性が低いという
欠点がある。In the above-mentioned conventional low dielectric constant glass-ceramic multilayer wiring board, the dielectric constant of the glass ceramic as a material of the board for mounting the semiconductor element is higher than that of the signal. It is an important parameter, and the relative dielectric constant is given by the following relationship ν = c / (ε r ) 1/2 (where c represents the speed of light), which is the relationship between the propagation velocity ν of the signal and the relative permittivity ε r of the material. The smaller the ratio ε r, the larger the signal propagation velocity ν, which is advantageous. On the other hand, as shown in FIG. 4, the mechanical strength of the substrate decreases as the relative permittivity of the glass ceramic substrate decreases. Is decreased, and the strength is only 20 to 70% with respect to the substrate containing alumina as a main component. Therefore, when high-density fine wiring is formed on the surface of the substrate in a later process, cracks may occur due to plating stress, or the strength of the bonding portion of the I / O pin to be brazed to the rear surface of the substrate may be deteriorated. There is a drawback that the reliability of the substrate is low.
【０００４】本発明の目的は、機械的強度がアルミナを
主成分としたセラミック多層配線基板と同等の強度を有
し、かつアルミナを主成分とする基板より比誘電率の低
い新規な低誘電率ガラスセラミック多層配線基板および
その製造方法を提供することにある。An object of the present invention is to provide a novel low dielectric constant having mechanical strength equivalent to that of a ceramic multilayer wiring board containing alumina as a main component and having a relative dielectric constant lower than that of a substrate containing alumina as a main component. A glass ceramic multilayer wiring board and a method for manufacturing the same are provided.
【０００５】[0005]
【課題を解決するための手段】本発明の低誘電率ガラス
セラミック多層配線基板は、少なくとも２種類以上の誘
電率の異なるセラミックグリーンシートからなるガラス
セラミック層を含むことを特徴とし、外層部に高誘電率
ガラスセラミック層を有し、内層部に複数の低誘電率ガ
ラスセラミック層が積層されてサンドイッチ構造をなす
ことが好ましい。The low dielectric constant glass-ceramic multilayer wiring board of the present invention is characterized by including a glass ceramic layer composed of at least two kinds of ceramic green sheets having different dielectric constants, and a high outer layer portion. It is preferable to have a dielectric constant glass ceramic layer and to form a sandwich structure by laminating a plurality of low dielectric constant glass ceramic layers on the inner layer portion.
【０００６】本発明の低誘電率ガラスセラミック多層配
線基板の製造方法は、アルミナ５５ｗｔ％，ホウケイ酸
系ガラス４５％ｗｔ％の混合粉末に、ブチラール系バイ
ンダーおよび有機溶剤を混合攪拌して得られるスラリー
を、キャスティングして所定の膜厚の高誘電率ガラスセ
ラミックグリーンシートとし、ホウケイ酸系ガラス５０
〜７０ｗｔ％，コーディエライト系１５〜３０ｗｔ％，
石英ガラス１５〜２０ｗｔ％の混合粉末に、ブチラール
系バインダーおよび有機溶剤を混合攪拌して得られるス
ラリーを、キャスティングして所定の膜厚の低誘電率ガ
ラスセラミックグリーンシートとし、前記高誘電率およ
び低誘電率ガラスセラミックグリーンシートに所定のピ
ッチでスルーホールを形成し、該スルーホールに銀粉８
５ｗｔ％，パラジウム粉１５ｗｔ％から成る導体ペース
トを充填し、かつ低誘電率ガラスセラミックグリーンシ
ートには、配線パターンを形成するため前記導体ペース
トを厚膜印刷し、これら誘電率の異なる各ガラスセラミ
ックグリーンシートからなるガラスセラミック層を、あ
らかじめ定められた順序および枚数で積層して多層化
し、該多層化されたガラスセラミック層を約１１０℃で
熱圧着し、さらに約５００℃の非還元性雰囲気中で約１
０時間保持し、約９００℃で１時間大気中で焼成してガ
ラスセラミック多層配線基板とし、該ガラスセラミック
多層配線基板の外形を所定の大きさに切断し、表裏両面
を研削加工して得られ、のぞましい態様としては、外層
部に高誘電率ガラスセラミック層を積層し、内層部に複
数の低誘電率ガラスセラミック層を積層してサンドイッ
チ構造とする。The method for producing a low dielectric constant glass-ceramic multilayer wiring board of the present invention is a slurry obtained by mixing and stirring a mixed powder of 55 wt% alumina and 45% wt% borosilicate glass with a butyral binder and an organic solvent. Is cast into a high-dielectric-constant glass-ceramic green sheet having a predetermined film thickness, and the borosilicate glass 50
~ 70wt%, cordierite type 15 ~ 30wt%,
A slurry obtained by mixing and stirring a butyral binder and an organic solvent in a mixed powder of 15 to 20 wt% of quartz glass is cast into a low dielectric constant glass ceramic green sheet having a predetermined film thickness, and the high dielectric constant and low Through holes are formed at a predetermined pitch in the dielectric constant glass ceramic green sheet, and silver powder 8 is formed in the through holes.
A low-dielectric-constant glass ceramic green sheet is filled with a conductive paste composed of 5 wt% and 15 wt% of palladium powder, and the conductive paste is thick-film printed to form a wiring pattern. Glass-ceramic layers made of sheets are laminated in a predetermined order and number of layers to form a multilayer, and the multilayered glass-ceramic layers are thermocompression bonded at about 110 ° C. and further in a non-reducing atmosphere at about 500 ° C. About 1
It is obtained by holding it for 0 hour, firing it at about 900 ° C. for 1 hour in the air to obtain a glass-ceramic multilayer wiring board, cutting the outer shape of the glass-ceramic multilayer wiring board to a predetermined size, and grinding both front and back surfaces. As a preferable mode, a high dielectric constant glass ceramic layer is laminated on the outer layer portion and a plurality of low dielectric constant glass ceramic layers are laminated on the inner layer portion to form a sandwich structure.
【０００７】[0007]
【作用】内層部に複数の低誘電率ガラスセラミック層を
積層し、その外層部に機械的強度の高いアルミナを主成
分とする高誘電率ガラスセラミック層を積層してサンド
イッチ構造としたため、内層部の低誘電率ガラスセラミ
ック層に設けられた回路の配線パターンが、信号の伝搬
速度を損われることなく、しかも機械的強度の勝れた外
層部によって、基板表面に形成された微細配線のメッキ
応力で発生するクラックや、基板表面にろう付けされる
Ｉ／Ｏピンの接着部の強度の劣下が防止される。[Function] A plurality of low dielectric constant glass ceramic layers are laminated on the inner layer portion, and a high dielectric constant glass ceramic layer mainly containing alumina having high mechanical strength is laminated on the outer layer portion to form a sandwich structure. The wiring pattern of the circuit provided on the low dielectric constant glass-ceramic layer of the circuit does not impair the signal propagation speed, and the plating stress of the fine wiring formed on the surface of the substrate is prevented by the outer layer that has excellent mechanical strength. It is possible to prevent the cracks generated in step S1 and the deterioration of the strength of the bonding portion of the I / O pin brazed to the substrate surface.
【０００８】[0008]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００９】図１は本発明のガラスセラミック多層配線
基板の一実施例の縦断面図である。このガラスセラミッ
ク多層配線基板は、内層部Ｂに３層よりなる低誘電率の
セラミック層１と、低融点かつ低抵抗の導体金属（例え
ば、金、銀、銀パラジウム、銅など）によるヴィアホー
ル部２および配線パターン部３により構成されている。
また、基板の外層部Ａは、機械的強度に優れた高誘電率
材料のセラミック層４、および内層部Ｂに使用したのと
同様の導体金属より成るヴィアホール部２から構成され
ている。ヴィアホール部２は各層に作孔されたスルーホ
ールで形成される。FIG. 1 is a vertical sectional view of an embodiment of the glass ceramic multilayer wiring board of the present invention. This glass-ceramic multilayer wiring board includes a ceramic layer 1 having a low dielectric constant consisting of three layers in an inner layer portion B, and a via hole portion made of a conductor metal having a low melting point and a low resistance (for example, gold, silver, silver palladium, copper, etc.). 2 and the wiring pattern portion 3.
The outer layer portion A of the substrate is composed of a ceramic layer 4 of a high dielectric constant material having excellent mechanical strength, and a via hole portion 2 made of the same conductive metal as that used for the inner layer portion B. The via hole portion 2 is formed by a through hole formed in each layer.
【００１０】次に、製造方法を詳細に説明する。図３
は、本発明のガラスセラミック多層配線基板の製造工程
を示す工程図である。このガラスセラミック多層配線基
板の製造工程は、グリーンシート成膜工程Ｐｌａ・Ｐｌ
ｂ，スルーホール形成工程Ｐ２，ヴィアホール及び配線
パターン印刷工程Ｐ３，積層工程Ｐ４，熱圧着工程Ｐ
５，焼成工程Ｐ６，外形切断工程Ｐ７，研削工程Ｐ８か
ら成っている。３層よりなる内層部の低誘電率のセラミ
ック材料には、従来の技術による基板と同様に、ホウケ
イ酸系ガラスを５０〜７０ｗｔ％，コーディエライト系
を１５〜３０ｗｔ％，石英ガラスを１５〜２０ｗｔ％混
合した粉末を使用する。これにブチラール系バインダー
および有機溶剤を混合攪拌してスラリー状にした後、こ
れをドクターブレード法によりキャスティングし、所定
の膜厚のグリーンシートを得る。Next, the manufacturing method will be described in detail. Figure 3
FIG. 4A is a process diagram showing a manufacturing process of a glass ceramic multilayer wiring substrate of the present invention. The manufacturing process of this glass-ceramic multilayer wiring board is the green sheet film forming process Pla.
b, through hole forming process P2, via hole and wiring pattern printing process P3, laminating process P4, thermocompression bonding process P
5, a firing process P6, an outer shape cutting process P7, and a grinding process P8. As for the low dielectric constant ceramic material of the inner layer portion consisting of three layers, borosilicate glass is 50 to 70 wt%, cordierite system is 15 to 30 wt%, and quartz glass is 15 to 30% as in the case of the conventional substrate. A powder mixed with 20 wt% is used. A butyral-based binder and an organic solvent are mixed and stirred into a slurry to form a slurry, which is cast by a doctor blade method to obtain a green sheet having a predetermined thickness.
【００１１】また別に、機械的強度の勝れた高誘電率の
セラミック材料としては、アルミナが５５ｗｔ％，ホウ
ケイ酸系ガラスを４５ｗｔ％の混合無機粉末を使用す
る。これにブチラール系バインダーおよび有機溶剤を混
合攪拌しスラリーを得る。これを低誘電率セラミック材
料の場合と同様に、ドクターブレード法によりキャステ
ィングして所定膜厚のグリーンシートを得る。Separately, as a high dielectric constant ceramic material having excellent mechanical strength, a mixed inorganic powder of 55 wt% alumina and 45 wt% borosilicate glass is used. A butyral-based binder and an organic solvent are mixed and stirred with this to obtain a slurry. Similar to the case of the low dielectric constant ceramic material, this is cast by a doctor blade method to obtain a green sheet having a predetermined film thickness.
【００１２】こうして得られた誘電率の異なる２種のグ
リーンシートに、それぞれパンチとダイスを使って、所
定のピッチに直径約３００μｍのスルーホールを形成す
る。次に、スクリーン印刷法により、前記スルーホール
に導体ペーストを充填する。また、同様のスクリーン印
刷法により、信号伝搬速度の勝れた低誘電率のグリーン
シートに、配線パターンを厚膜印刷し、低誘電率セラミ
ック層１をつくる。なお、導体ペーストには、銀粉８５
ｗｔ％およびパラジウム粉１５ｗｔ％の組成の銀パラジ
ウムペーストを使用する。Through holes and a diameter of about 300 μm are formed at a predetermined pitch on each of the two types of green sheets thus obtained having different permittivities by using a punch and a die respectively. Next, the conductor paste is filled in the through holes by a screen printing method. Also, by the same screen printing method, a wiring pattern is thickly printed on the low dielectric constant green sheet having a superior signal propagation speed to form the low dielectric constant ceramic layer 1. The conductor paste contains silver powder 85
A silver-palladium paste having a composition of wt% and palladium powder of 15 wt% is used.
【００１３】以上のようにメタライズされたグリーンシ
ートを所定の金型内に位置合わせをして積層し、多層化
する。このとき、低誘電率セラミック層１を内層部Ｂ
に、また高誘電率セラミック層４を基板外層部Ａに配置
したサンドイッチ構造をなすように、積層順序および積
層枚数をあらかじめ決めておき、さらに、後述する研削
工程に必要なとりしろを、外層部の高誘電率セラミック
層４に与えるように積層の全厚みを考慮しておく。The green sheets metallized as described above are aligned and laminated in a predetermined mold to form a multi-layer. At this time, the low dielectric constant ceramic layer 1 is formed on the inner layer portion B.
In order to form a sandwich structure in which the high-dielectric-constant ceramic layer 4 is arranged in the outer layer portion A of the substrate, the stacking order and the number of stacked layers are determined in advance, and the margin necessary for the grinding step described later is provided in the outer layer portion. The total thickness of the stack is taken into consideration as it is applied to the high dielectric constant ceramic layer 4.
【００１４】次に、これを約１１０℃で熱圧着する。そ
の後、約５００℃の非還元性雰囲気中で約１０時間保持
し、バインダーを十分に飛散させ、約９００℃で１時
間、大気中で焼成してガラスセラミック多層配線基板を
得る。Next, this is thermocompression bonded at about 110.degree. After that, the glass is held in a non-reducing atmosphere at about 500 ° C. for about 10 hours, the binder is sufficiently scattered, and baked at about 900 ° C. for 1 hour in the air to obtain a glass-ceramic multilayer wiring board.
【００１５】その後、所定の大きさに外形を切断し、ま
た、焼成により発生する反りを除去する為に、基板表裏
両面に研削加工を施して平坦にする。After that, the outer shape is cut into a predetermined size, and both sides of the substrate are ground to be flat in order to remove a warp generated by firing.
【００１６】以上の工程を経て、基板外層部Ａには機械
的強度の比較的高い比誘電率７〜８のガラスセラミック
層４が、また、内層部Ｂには信号伝搬速度が勝れた比誘
電率４〜５のガラスセラミック層１が積層されたガラス
セラミック多層配線基板が得られる。Through the above steps, the glass-ceramic layer 4 having a relatively high relative dielectric constant of 7 to 8 has a relatively high mechanical strength in the outer layer portion A of the substrate, and the inner layer portion B has a ratio superior in signal propagation speed. A glass ceramic multilayer wiring board in which the glass ceramic layers 1 having a dielectric constant of 4 to 5 are laminated is obtained.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、信号伝搬
速度を高速にするための低誘電率のガラスセラミック層
を基板の内層部に、また、基板の機械的強度を向上させ
るために比較的高誘電率のガラスセラミック層を基板の
外層部に配置させることにより、後工程で高密度微細配
線を形成する際のメッキ応力によって発生するクラック
等の欠陥を防ぎ、また基板裏面にろう付けするＩ／Ｏピ
ンの接着部の割れを防止し、信号伝搬特性を低下させる
こと無く、信頼性の高い低誘電率のガラスセラミック多
層配線基板が得られるという効果がある。As described above, according to the present invention, a glass ceramic layer having a low dielectric constant for increasing a signal propagation speed is used as an inner layer portion of a substrate, and a mechanical strength of the substrate is improved. By placing a glass-ceramic layer with a high dielectric constant on the outer layer of the substrate, defects such as cracks caused by plating stress when forming high-density fine wiring in a later process are prevented, and brazing is performed on the back surface of the substrate. There is an effect that a crack in the bonding portion of the I / O pin is prevented, and a highly reliable glass ceramic multilayer wiring board having a low dielectric constant can be obtained without deteriorating the signal propagation characteristic.
【図１】本発明による低誘電率ガラスセラミック多層配
線基板の一実施例の縦断面図である。FIG. 1 is a vertical sectional view of an example of a low dielectric constant glass-ceramic multilayer wiring board according to the present invention.
【図２】従来の低誘電率ガラスセラミック多層配線基板
の縦断面図である。FIG. 2 is a vertical cross-sectional view of a conventional low dielectric constant glass ceramic multilayer wiring board.
【図３】本発明のガラスセラミック多層配線基板製造工
程図である。FIG. 3 is a process drawing of the glass-ceramic multilayer wiring board manufacturing process of the present invention.
【図４】比誘電率と強度の関係を示す図である。FIG. 4 is a diagram showing a relationship between relative permittivity and strength.
１，１１ 低誘電率のセラミック層 ２，１２ ヴィアホール部 ３，１３ 配線パターン部 ４ 高誘電率のセラミック層 Ａ 外層部 Ｂ 内層部 Ｐ１ａ 低誘電率グリーンシート成膜工程 Ｐ１ｂ 高誘電率グリーンシート成膜工程 Ｐ２ スルーホール形成工程 Ｐ３ 印刷工程 Ｐ４ 積層工程 Ｐ５ 熱圧着工程 Ｐ６ 焼成工程 Ｐ７ 外形切断工程 Ｐ８ 研削工程 1,11 Low dielectric constant ceramic layer 2,12 Via hole part 3,13 Wiring pattern part 4 High dielectric constant ceramic layer A Outer layer part B Inner layer part P1a Low dielectric constant green sheet deposition process P1b High dielectric constant green sheet formation Film process P2 Through hole forming process P3 Printing process P4 Laminating process P5 Thermocompression bonding process P6 Firing process P7 External cutting process P8 Grinding process
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 1/03 Ｂ 7011−4Ｅ 3/46 Ｔ 6921−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication H05K 1/03 B 7011-4E 3/46 T 6921-4E
Claims (4)
て、少なくとも２種類以上の誘電率の異なるセラミック
グリーンシートからなるガラスセラミック層を含むこと
を特徴とする低誘電率ガラスセラミック多層配線基板。1. A low-dielectric-constant glass-ceramic multilayer wiring board comprising a glass-ceramic layer made of at least two kinds of ceramic green sheets having different dielectric constants.
基板が、外層部に高誘電率ガラスセラミック層を有し、
内層部に複数の低誘電率ガラスセラミック層を有する請
求項１に記載の低誘電率ガラスセラミック多層配線基
板。2. The low dielectric constant glass ceramic multilayer wiring board has a high dielectric constant glass ceramic layer in an outer layer portion,
The low dielectric constant glass ceramic multilayer wiring board according to claim 1, wherein a plurality of low dielectric constant glass ceramic layers are provided in the inner layer portion.
基板の製造方法であって、 アルミナ５５ｗｔ％，ホウケイ酸系ガラス４５％ｗｔ％
の混合粉末に、ブチラール系バインダーおよび有機溶剤
を混合攪拌して得られるスラリーを、キャスティングし
て所定の膜厚の高誘電率ガラスセラミックグリーンシー
トとし、 ホウケイ酸系ガラス５０〜７０ｗｔ％，コーディエライ
ト系１５〜３０ｗｔ％，石英ガラス１５〜２０ｗｔ％の
混合粉末に、ブチラール系バインダーおよび有機溶剤を
混合攪拌して得られるスラリーを、キャスティングして
所定の膜厚の低誘電率ガラスセラミックグリーンシート
とし、 前記高誘電率および低誘電率ガラスセラミックグリーン
シートに所定のピッチでスルーホールを形成し、 該スルーホールに銀粉８５ｗｔ％，パラジウム粉１５ｗ
ｔ％から成る導体ペーストを充填し、 かつ低誘電率ガラスセラミックグリーンシートには、配
線パターンを形成するため前記導体ペーストを厚膜印刷
し、 これら誘電率の異なる各ガラスセラミックグリーンシー
トからなるガラスセラミック層を、あらかじめ定められ
た順序および枚数で積層して多層化し、 該多層化されたガラスセラミック層を約１１０℃で熱圧
着し、 さらに約５００℃の非還元性雰囲気中で約１０時間保持
し、 約９００℃で１２時間大気中で焼成してガラスセラミッ
ク多層配線基板とし、 該ガラスセラミック多層配線基板の外形を所定の大きさ
に切断し、表裏両面を研削加工して得られる低誘電率ガ
ラスセラミック多層配線基板の製造方法。3. A method for manufacturing the low dielectric constant glass-ceramic multilayer wiring board, comprising 55% by weight of alumina and 45% by weight of borosilicate glass.
A slurry obtained by mixing and stirring a butyral-based binder and an organic solvent with the mixed powder of is a high dielectric constant glass ceramic green sheet with a predetermined film thickness, borosilicate glass 50-70 wt%, cordierite A slurry obtained by mixing and stirring a butyral-based binder and an organic solvent in a mixed powder of 15 to 30 wt% of silica glass and 15 to 20 wt% of quartz glass is cast to obtain a low dielectric constant glass ceramic green sheet having a predetermined film thickness, Through holes are formed at a predetermined pitch on the high-permittivity and low-permittivity glass ceramic green sheets, and silver powder 85 wt% and palladium powder 15 w are formed in the through holes.
A glass ceramic consisting of glass ceramic green sheets each of which has a different dielectric constant and which is filled with a conductor paste of t% and is printed with a thick film on the low dielectric constant glass ceramic green sheet to form a wiring pattern. The layers are laminated in a predetermined order and number of layers to form a multilayer, and the multilayered glass-ceramic layer is thermocompression-bonded at about 110 ° C., and further held in a non-reducing atmosphere at about 500 ° C. for about 10 hours. A low dielectric constant glass obtained by firing in the air at about 900 ° C. for 12 hours to obtain a glass-ceramic multilayer wiring board, cutting the outer shape of the glass-ceramic multilayer wiring board into a predetermined size, and grinding both front and back surfaces. Manufacturing method of ceramic multilayer wiring board.
基板の製造方法が、外層部に高誘電率ガラスセラミック
層を積層し、内層部に複数の低誘電率ガラスセラミック
層を積層した請求項３に記載の低誘電率ガラスセラミッ
ク多層配線基板の製造方法。4. The method for manufacturing a low dielectric constant glass ceramic multilayer wiring board according to claim 3, wherein a high dielectric constant glass ceramic layer is laminated on an outer layer portion and a plurality of low dielectric constant glass ceramic layers are laminated on an inner layer portion. A method for producing a low dielectric constant glass-ceramic multilayer wiring board according to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3354792A JPH05235550A (en) | 1992-02-20 | 1992-02-20 | Low permittivity glass ceramic multilayer circuit board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3354792A JPH05235550A (en) | 1992-02-20 | 1992-02-20 | Low permittivity glass ceramic multilayer circuit board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05235550A true JPH05235550A (en) | 1993-09-10 |
Family
ID=12389594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3354792A Pending JPH05235550A (en) | 1992-02-20 | 1992-02-20 | Low permittivity glass ceramic multilayer circuit board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05235550A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148832A (en) * | 1994-11-24 | 1996-06-07 | Canon Inc | Multilayered printed board |
| US6602616B2 (en) | 2000-12-19 | 2003-08-05 | Murata Manufacturing Co. Ltd | Composite multilayer ceramic electronic parts and method of manufacturing the same |
| US6699605B2 (en) | 2001-08-21 | 2004-03-02 | Nippon Electric Glass Co., Ltd | Glass ceramic laminate becoming relatively high in bending strength after fired |
| JP2011075313A (en) * | 2009-09-29 | 2011-04-14 | Three M Innovative Properties Co | Ic device testing socket |
-
1992
- 1992-02-20 JP JP3354792A patent/JPH05235550A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148832A (en) * | 1994-11-24 | 1996-06-07 | Canon Inc | Multilayered printed board |
| US6602616B2 (en) | 2000-12-19 | 2003-08-05 | Murata Manufacturing Co. Ltd | Composite multilayer ceramic electronic parts and method of manufacturing the same |
| US6699605B2 (en) | 2001-08-21 | 2004-03-02 | Nippon Electric Glass Co., Ltd | Glass ceramic laminate becoming relatively high in bending strength after fired |
| JP2011075313A (en) * | 2009-09-29 | 2011-04-14 | Three M Innovative Properties Co | Ic device testing socket |
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