JPH0883248A - Information processing system and its method - Google Patents

Abstract

PURPOSE: To make possivle synchronous operation between processors in different nodes by redistributing information to the respective nodes by a signal path for arbitration on the basis of information sent from the nodes. CONSTITUTION: In addition to a packet information management device 21 which manages packets, a path selection information management device 22 which manages path request information, an additional information management device 23 which temporarily stores additional information accompanied by data transfer such as addresses, and a synchronous information management device 24 which temporarily stores information required for an inter-CPU synchronizing mechanism in a packet and performs control for the redistribution of protocol information to the respective nodes are arranged in an arbiter 20 which arbitrates the use of a connection path 10. Then an arbitrating means redistributes the information sent from the nodes 100, 200, 300, and 400 to the respective nodes 100... on the basis of the sent information by using the signal path for arbitration and reflects the distributed information on the internal buses of the nodes 100... to perform the synchronous operation among the different processors 101....

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus mainly composed of a plurality of nodes each having one or more processors and memories, and a connection path connecting the plurality of nodes. is there.

[0002]

2. Description of the Related Art CP in a multiprocessor system
When trying to synchronize U, the exclusive use of the shared bus to which those CPUs are connected becomes a single CPU for a certain period.
The bus lock method, which realizes the synchronization mechanism by allowing it, has been often used. On the other hand, rese is accompanied by the load instruction.
An instruction that sets the rve flag (hereinafter, this instruction is Load Reserve
Instruction [LR]), which is one of the conditional store instructions, checks the reserve flag before executing the store instruction, executes the store instruction if the flag is valid, and then executes the reserve flag. By inactivating an instruction (hereinafter, this instruction is referred to as a Store Conditional instruction [SC]) and snooping the bus, another CPU can set itself to [L].
R] store at the same address where the instruction was executed
The function that disables the reserve flag when it detects that an instruction has been executed (this function will be referred to as the StoreSnoop function [S
S)), and these [LR], [SC], [S]
S] is used to implement the synchronization mechanism. The latter does not use the monopoly of the bus compared to the former,
This is intended to improve performance in a multi-CPU system.

On the other hand, when connecting a plurality of nodes each having one or more processors and memories for the purpose of exchanging data between the nodes, a method of connecting using various LANs,
There is a method of connecting the nodes at the address level of the memory regardless of the LAN. As an example of the latter, the applicant of the present application has filed an application for an information processing apparatus using an optical wavelength multiplexing system as Japanese Patent Application No. 5-286876. This system is characterized in that different data transfer can be realized simultaneously among a plurality of nodes by using a plurality of wavelengths.

As an example of improvement of the system, the applicant of the present application filed Japanese Patent Application No. 5-288271.
At the same time that each node requests a connection route prior to data transfer,
Additional information related to data transfer is sent to the arbiter, and when the arbiter sets the connection route, it sends that information to the connection destination node through the arbitration signal line, and the node that receives the connection request sets up the route and An information processing apparatus has been devised that improves the efficiency of data transfer after setting a connection path by overlapping the preparation of the data to be transmitted and received in the above.

[0005]

However, in the system using the above-mentioned optical wavelength multiplexing system, it is possible to simultaneously realize different data transfer between a plurality of nodes by using a plurality of wavelengths. It is impossible for each CPU in a node to snoop these plural data transfers at the same time, and therefore, the above-mentioned system cannot introduce the inter-CPU synchronization mechanism extending between the nodes. Therefore, the realization of the synchronization between the CPUs is limited to the inside of the node, and it has been impossible to perform the complicated processing such as utilizing the synchronization between the CPUs extending between the nodes.

Therefore, an object of the present invention is to realize a CPU synchronous operation across nodes.

[0007]

In order to solve the above-mentioned problems, according to the present invention, an internal bus is detected, and information required for a synchronous operation is detected by monitoring the bus, and based on the information, another processor is provided. In an information processing system including a plurality of nodes having a processor that executes a synchronous operation, a connection path capable of simultaneously connecting a plurality of sets between the plurality of nodes, and an arbitration unit for arbitrating a use request of the connection path, An arbitration signal path connecting between the arbitration means and each node, and a part or all of the information required for the synchronous operation in the node and between the nodes are transferred from the node to the arbitration means by the arbitration signal. Based on the information transmitted from the node by the transmission means for transmitting using the route, a part or all of the information is transmitted from the arbitration means to each node by using the arbitration signal path. Comprising a re-distribution means for distributing, the information distributed to each node by the distribution means, by reflecting on the internal bus of each node, to achieve a synchronous operation between the processors in different nodes.

According to another aspect of the present invention, an internal bus and a processor that monitors the bus to detect information required for a synchronous operation and executes a synchronous operation with another processor based on the information. In an information processing method in an information processing system having a plurality of nodes each including and having a connection path capable of simultaneously connecting a plurality of sets between the plurality of nodes, a part or all of information required for a synchronous operation in the nodes and between the nodes is provided. And a request to use the connection path, and a transmission step of transmitting from the node to the arbitration unit using an arbitration signal path that connects the arbitration unit and each node, and a request to use the connection path. An arbitration step of arbitrating the arbitration unit, and based on the information transmitted from the node in the transmission step, a part or all of the information is arbitrated by using the arbitration signal path. From each node to each node by reflecting the information distributed to each node on the internal bus of each node, thereby synchronizing between processors in different nodes. Realize the action.

[0009]

1 is a block diagram of an embodiment of a system for realizing the present invention.

Reference numerals 100, 200, 300, and 400 are nodes, and the nodes are connected by a connection path 10 formed of an optical fiber. Each node has a C in it
PU 101, 201, 301, 401, memory 102,
202, 302, 402, interface circuits 103, 20 for connecting the connection path 10 and the inside of each node
3, 303, 403, an arbitration interface circuit 104 for requesting the use of the connection path 10,
204, 304, 404, internal buses 105, 205, 305, 405 for interconnecting them inside the node
Is included.

Further, the arbitration interface circuits 104, 204, 304, 404 include synchronization realization devices 106, 206, 306, 406 for detecting synchronization-related instructions and emulating the synchronization-related instructions. However, the configuration is not limited to this.

Reference numeral 20 is an arbiter for arbitrating the use of the connection path 10. The arbiter 20 is connected to each node and the arbitration signal paths 110, 210, 3 respectively.
They are connected by 10, 410.

Further, inside the arbiter 20, in addition to the packet information management device 21 that manages the packets sent from each node, a route selection information management device that manages the route request information among the information included in the packets. 22, an additional information management device 23 that temporarily stores additional information associated with data transfer such as an address sent subsequently to the information,
Further, a synchronization information management device 24 is installed which temporarily stores information necessary for realizing the inter-CPU synchronization mechanism in the packet and performs control for redistributing protocol information to each node.

In the present embodiment, in the system having the configuration shown in FIG. 1, the synchronization information is centrally managed through the arbiter, and the information is broadcast from the arbiter to each node, whereby the bus snoops cannot be performed mutually. Below, an example of realizing an inter-CPU synchronization mechanism across nodes will be shown.

Specifically, the CPU 10 on the node 100
1 shows how the CPU-to-CPU synchronization holding operation is performed when 1 and the CPU 301 on the node 300 try to synchronize the data in the memory 202 on the node 200.

FIG. 2 is an address map of the entire system. In this embodiment, 4 gigabytes of the address space of the entire system is distributed to four nodes for use.

Now, the CPU 101 on the node 100 is
The data (4 bytes) at the address 41000000h on the RAM 202 of the node 200 is lo using the [LR] instruction.
After the ad has been added, and the reserve flag is valid, it is assumed that the [SC] instruction is issued to change it.

The processor 101 in the node 100
The process of loading the data of the RAM 41000000h inside the node 200 is described in Japanese Patent Application No. 5-288827.
This is realized by reading data between nodes as shown in No. 1.

The CPU 301 on the node 300 also
The data (4 bytes) at the address 41000000h on the RAM 201 of the node 200 is lo using the [LR] instruction.
It is assumed that it has been done after the ad and the reserve flag is valid.

FIG. 3 is a block diagram of the arbiter interface 104.

The address decoder 140 existing inside the arbiter interface 104 constantly monitors the internal bus 105 (composed of the data signal line 151, the control signal line 152, and the address signal line 153) of the node 101, and externally. When it is recognized that an access to the node (in this case, the node 200) (write operation to the address 41000000h) occurs on the bus, the node arbitration control processor 14 uses the external access detection signal 144 and the write request detection signal 150.
Pass control to the program running on 1. At the same time, in the address latch register 142, the address signal line 1
The address output on 53 is latched, and the control signal latch register 143 latches control information such as the read / write request type (write) and the number of transfer bytes (4 bytes).

Node Arbitration Processor 14
Although 1 uses a 1-chip microcontroller in the present embodiment, it is not limited to this configuration and may be configured by hardware logic or the like.

At this time, at the same time, the control signal decoder 180 existing inside the synchronization realizing device 106 incorporated in the arbiter interface 104 constantly monitors the control signal line 152, and the store
e instruction (in this case, address 4100 on node 200)
When the [SC] command to 0000h is recognized on the bus, the store request detection signal 181 notifies the program operating on the node arbitration control processor 141 that synchronization control is required.

Node arbitration control processor 141 notified by signals 144, 150, 181
Reads the address and control information latched from the address latch 142 and the control signal latch 143, determines the connection destination, creates an arbitration request packet as shown in FIG. 4, and writes it in the parallel / serial converter 161. The packet shown in FIG. 4 is a route request signal and also includes, as information, a portion for notifying the arbiter of the synchronization control request.

The parallel / serial converter 161 converts the written information into serial data, and the light emitting element 1
Output to 63. The light emitting element 163 photoelectrically converts the input signal and outputs it to the arbiter 20 as an optical signal of wavelength λ1 through the communication path 110 formed of an optical fiber. This configuration is common to all nodes.
Note that the light emitting element here is an element such as an LED or a laser, and the light receiving element is an element represented by a photodiode.

FIG. 5 shows a block diagram of the arbiter 20. Reference numerals 601, 603, 605, and 607 denote light receiving elements, each of which receives an optical signal having a wavelength of λ1 emitted by a node, that is, receives the arbitration request signal and converts it into an electric signal. Now, a request signal arrives from the node 100, When input to the serial / parallel converter 611, the serial / parallel converter 611 converts the input serial electric signal into a parallel signal, and at the same time, notifies the packet information management device 21 by a data reception detection signal 622. In this embodiment, the packet information management device 21 includes a micro controller 621 having a ROM storing a program and a RAM used for processing.
Composed by.

Further, this microcontroller 621
At the same time, it includes a part that plays a role of the route selection information management device 22, the additional information management device 23, and the synchronization control information management device 24. However, the configuration is not limited to this.

Upon receiving the data reception detection signal (1) 622, the packet information management device 21 selects the serial / parallel converter 611 by the device select signal 619, and the node 100 from the internal register through the data bus 620. Read out the sent request packet. Of the information contained in the request packet,
The information of the request source node number is the route selection information management device 22.
The part of the additional information which is transferred to the device and is related to the data transfer is stored in the part of the micro controller 621 which serves as the additional information management device 23. Further, when it is determined that this packet is accompanied by the CPU CPU synchronization holding operation, the CPU CPU synchronization holding operation in each node is required.
Information such as the requesting node number is displayed on the microcontroller 6
It is stored in a portion of the storage device 21 that functions as the synchronization control information management device 24.

The route selection information management device 22 analyzes the received data, and a request for using this transmission line is sent to the node 100.
It recognizes that it is a connection request to the node 200, checks the transmission path use status flag provided in the path selection information management device, and the wavelength in use, and uses the flag when it is in the usable status. Set to the medium state, and
The connection preparation request packet shown in FIG.
Write to 4 parallel / serial converter. This connection preparation packet also includes the information provided from the part that plays the role of the additional information management device 23 in the microcontroller and the wavelength information. These two connection preparation request packets use the optical signal of λ1 as in the case of the optical arbiter interface and are output to the node 100 and the node 200. Note that the four nodes can simultaneously perform two-system communication between the one-to-one nodes by using different wavelengths λ2 and λ3 for data communication.

Subsequently, the synchronization information management device 24 uses the information provided to the synchronization information management device 24 to control the CP in each node.
In order to maintain synchronization between U, nodes 300 and 400
On the other hand, when the reserve flag is set in correspondence with the address of 41000000h, it is instructed to invalidate it. Therefore, a synchronization flag invalidation packet as shown in FIG. Sequentially write to parallel / serial converter.

In this case, if these converters are used for the arbitration of the original connection path,
The synchronization flag invalidation packet is transferred after waiting for the end of use.

These two synchronization flag invalidation packets use the optical signal of λ1 as in the case of the optical arbiter interface, and the arbitration signal lines 310 and 410.
Through node 300 and node 400.

The reserve flag invalidation operation for maintaining the synchronization between the CPUs in the nodes 300 and 400 will be described by taking the operation in the node 300 as an example.

Since the configuration of the node 300 is the same as that of the node 100, FIG. 3 will be used for explanation. In the node 300, the optical signal input by the fiber 310 (110 in FIG. 3) is converted into an electrical signal by the light receiving element 164, and the optical arbiter interface 304 (1 in FIG. 3).
04) is input. Optical arbiter interface 3
At 04, the input signal is converted into a parallel signal by the serial / parallel converter 162 and, at the same time, is notified to the node arbitration control processor 141 by the data reception signal 148.

When this notification is detected, the node arbitration control processor 141 of the node 300 reads the synchronization flag invalidation packet from the serial / parallel converter 162 using the device select signal 147 and the data bus 145. , Requests the use permission of the internal bus 305 toward the inside of the node. When the use permission of the internal bus is given, the node arbitration control processor 141 uses the data transmission / reception request signal group 149 to associate with the connection route interface 303 the address 41000000h based on the contents of the packet of FIG. Instructing a CPU that sets a reserve flag on the internal bus 305 to invalidate the flag.

FIG. 8 shows the connection path interface unit 303.
An example is shown below. Here, the data transmission / reception request signal 149 sent from the arbiter interface causes the address driver 130 to receive the address (41000000h).
However, the data transfer sequencer 131 is instructed to invalidate the synchronization flag. In this case, specifically, the internal bus 3
05, the store of dummy data at address 41000000h is instructed.

The sequencer 131 receives the signal 134,
Address 410000 for the address driver 130
00h drive, then the control driver 132 is instructed to drive the transfer signal to the bus for the transfer size and control signal for executing the store instruction.
Instruct through 6. Further, the dummy data is driven onto the bus through the signal line 137 and the data buffer 1
Instruct 33.

The store process of this dummy data is performed by [S
The intra-node processor 301 snooped as
It checks the reserve flag that it holds and the register that holds the address that raised the flag. In the case of this embodiment, since the addresses match, the reserve flag is invalidated.

On the other hand, since there is no corresponding address in the memory 302, this store process is ignored.
The data transfer sequencer 131 instructs the control driver 132 to drive the acknowledge signal after a certain delay in order to prevent the bus from timing out.

A similar operation is performed in node 400.

The series of operations in the nodes 300 and 400 may be defined as an address only transaction in a system using a CPU in which the control of the address bus and the data bus is independent. In that case, these reserves
The e-flag invalidation process can be completed without the drive of dummy data onto the bus by completing the process only in the address phase.

On the other hand, in the node 200 which is the correct data transfer destination, the transfer is performed as shown in Japanese Patent Application No. 5-288271, and the data store process is performed. At that time, [SS] is executed similarly to the operation in the node 300, the synchronization flag of the CPU is checked, and the synchronization operation is guaranteed.

As a result, the synchronization holding operation between the CPUs is realized by executing the [SC] instruction of the node 100.

The same processing is performed in the transfer between other nodes.

In this embodiment, the arbitration signal paths 110, 210, 310 and 41 shown in FIG. 1 are used.
The light of wavelength λ1 is used for the optical signal above 0, and the connection path 1
The wavelengths λ2 and λ3 (λ2 and λ3 are different wavelengths) are used for the optical signal on 0, but there is no problem in the configuration even if λ1 = λ2 and λ1 = λ3.

Next, in the case of a synchronous instruction to the data on the memory inside the own node, specifically, the CP on the node 100.
U101 has RAM1 in its own node that can be used for synchronization commands
Data at address 01000000h on 02 (4 bytes)
Shows that how the synchronization holding operation is carried out when the command is loaded by using the [LR] instruction and is changed by issuing the [SC] instruction.

In FIG. 3, this time, the external access detection signal 144 does not react, and the write request detection signal 150 and the store request detection signal 181 pass control to the program operating on the node arbitration control processor 141. Address latch register 1 at the same time
42, the address output on the address signal line 153 at that time is latched to the control signal latch register 1
The control information such as the number of transfer bytes (4 bytes) is latched in 43.

The node arbitration control processor 141 reads the signals latched by the address latch 142 and the control signal latch 143, and
A synchronous maintenance request packet as shown in (1) is created and written in the parallel / serial converter 161. The parallel / serial converter 161 converts the written information into serial data and outputs it to the light emitting element 163. The light emitting element 163 photoelectrically converts the input signal,
The optical signal of wavelength λ1 is output to the arbiter 20 through the communication path 110 formed of an optical fiber.

In FIG. 5, when a cache maintenance request packet arrives from the node 100 and is input to the serial / parallel converter 611, the serial / parallel converter 611 converts the input serial electric signal into a parallel signal. , At the same time data reception detection signal 6
22 to notify the packet information management device 21.

Upon receiving the data reception detection signal (1) 622, the packet information management device 21 selects the serial / parallel converter 611 by the device select signal 619, and the node 100 from the internal register through the data bus 620. Read out the sent synchronous maintenance request packet. Then, information such as the address, the number of transfer bytes, and the requesting node number in the packet is stored in the portion of the microcontroller that functions as the synchronization information management device 24.

The synchronization information management device 24 holds the nodes 200, 300 and 400 in order to maintain the CPU synchronization among the nodes based on the information provided to itself.
On the other hand, in order to instruct to invalidate the reserve flag for the data at the address 01000000h, the cache memory invalidation packet as shown in FIG. 7 is created, and the parallel / serial converter is created. Data is sequentially written in 614, 616, and 618.

The operation after this is the same as that of the previous example, and therefore its explanation is omitted.

In the embodiment shown so far, FIG.
Arbitration signal paths 110, 21 in
0, 310, 410 and the connection path 10 were physically assumed to be different signal paths. However, if these lines can be logically separated, they may physically pass through the same signal path. It may be.

In this case, however, it is necessary that λ1, λ2 and λ3 have different wavelengths in order to prevent interference when wavelength multiplexing.

[Other Embodiments] In the previous embodiment, the invalidation processing for maintaining the synchronization between the CPUs in each node is realized by realizing all the processing requests notified from the arbiter in each node as dummy write processing. It was realized.

However, by improving the function of the synchronization realizing device in each node, it is possible to realize the CPU synchronization among the nodes more efficiently.

Such an example will be shown with reference to FIG.

FIG. 10 is a block diagram of a synchronization realizing device and an arbiter interface circuit (a part). Taking the node 100 as an example, the numbers in the figure refer to the numbers in the previous embodiment.

In the synchronization realizing device 106, in addition to the control signal decoder 180 and the store request detection signal 181, shown in FIG. 3, a synchronization address register 182, [L
R] An instruction detection signal 183, an address comparison device 184, a synchronous transaction request signal 185, etc. are present.

The control signal decoder 180 constantly monitors the control signal line 152, and when it recognizes that the [LR] instruction has occurred on the bus, it notifies the synchronous address register 182 by the [LR] instruction detection signal 183. . The synchronous address register 182 notified by the signal 183 stores the address at which the [LR] instruction currently flowing on the bus is executed and the CPU number executing the bus transaction.

The address stored in the synchronous address register 182 is given to the address bus snooper 186 and the address comparison device 184. When the address bus snooper 186 detects the same address as the address given from the synchronous address register 182 on the bus, it outputs the address match signal 187 to the synchronous address register 1
Drive for 82. Address match signal 187,
And both of the store request detection signal 181 are detected to be driven at one time, the synchronous address register 182 clears the held address.

On the other hand, the node arbitration control processor 141, which has detected that the reserve flag invalidation packet has been received from the arbiter 20, sends the address comparison device 184 the address indicated in the packet given from the arbiter 20 as data. Given via line 145, the address comparator 184 tests whether that address matches the address stored in the sync address register 182. If they match, there is a CPU that issues the [LR] command to the corresponding address inside the node and holds the reserve flag, so the flag invalidation process is necessary. Only then is the synchronous transaction request signal 185 driven to the arbitration processor 141. The arbitration processor 141 receiving this signal,
The processing for maintaining synchronization between CPUs as described above is executed.

By doing this, it is possible to prevent unnecessary bus transactions from occurring in the node,
It is possible to more efficiently realize inter-CPU synchronization across nodes.

[0064]

As described above, in the present invention, the internal bus and the processor that monitors the bus to detect the information required for the synchronous operation and execute the synchronous operation with the other processor based on the information. An information processing system including a plurality of nodes each having a connection path capable of simultaneously connecting a plurality of sets between the plurality of nodes, an arbitration means for arbitrating a use request of the connection path, the arbitration means and each node And a part or all of the information required for the synchronous operation in the node and between the nodes and the arbitration signal path connecting between the node and the node are transmitted to the arbitration means using the arbitration signal path. Based on the transmission means and the information transmitted from the node by the transmission means, a redistribution means for redistributing a part or all of the information from the arbitration means to each node using the arbitration signal path. The comprising, the information distributed to each node by the distribution means, by reflecting on the internal bus of each node, it becomes possible to realize a synchronous operation between the processors in different nodes.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a system for realizing the present invention.

FIG. 2 is an address map of the system of the embodiment.

FIG. 3 is a diagram illustrating an arbiter interface of a node according to an embodiment.

FIG. 4 is a diagram showing a structure of an arbitration request packet.

FIG. 5 is a diagram showing a configuration of an arbiter according to an embodiment.

FIG. 6 is a diagram showing a structure of a connection preparation request packet.

FIG. 7 is a diagram showing a structure of a synchronization flag invalidation packet.

FIG. 8 is a diagram showing a configuration of a connection path interface unit of the embodiment.

FIG. 9 is a diagram showing a structure of a synchronous maintenance request packet.

FIG. 10 is a diagram showing a partial configuration of a synchronization realization device and an arbiter interface of another embodiment.

[Explanation of symbols]

10 connection path between nodes 20 arbiter 21 packet information management device 22 route selection information management device 23 additional information management device 24 synchronization information management device 30 concentrator 100, 200, 300, 400 node 101, 201, 301, 401 processor 102, 202 , 302, 402 memory 103, 203, 303, 403 connection path interface circuit 104, 204, 304, 404 arbiter interface circuit 105, 205, 305, 405 node internal bus 106, 206, 306, 406 synchronization achievement device 107, 207, 307, 407 Wavelength multiplexer 110, 210, 310, 410 Arbitration signal path 130 Address driver 131 Data transfer sequencer 132 Control driver 133 Data Buffer 134 address drive signal 135 acknowledge signal 136 control driver control signal 137 data buffer control signal 138 data reception signal 139 parallel / serial converter control signal 140 address decoder 141 node arbitration control processor 142 address latch register 143 control signal latch register 144 external access Detection signal 145 Data signal line 146 Register select signal line 147 Device select signal line 148 Data reception signal 149 Data transmission / reception request signal group 150 Write request detection signal 151 Internal bus data signal line 152 Internal bus control signal line 153 Internal bus address Signal lines 161, 165, 612, 614, 616, 618 Parallel / serial conversion 162, 166, 611, 613, 615, 617 Serial / parallel converter 163, 167, 602, 604, 606, 608 Light emitting element 164, 168, 601, 603, 605, 607 Light receiving element 180 Control signal decoder 181 store Request detection Signal 182 Synchronous address register 183 [LR] instruction detection signal 184 Address comparison device 185 Synchronous transaction request signal 186 Address bus snooper 187 Address match signal 619 Device select signal 620 Data bus 621 Micro controller 622, 623, 624, 625 Data detection signal 626 control signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masato Kosugi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (6)

[Claims] 1. An information processing apparatus comprising a plurality of nodes each having an internal bus and a processor for monitoring the bus to detect information required for a synchronous operation and executing a synchronous operation with another processor based on the information. A system, wherein a plurality of connection paths capable of simultaneously connecting a plurality of sets between the plurality of nodes, arbitration means for arbitrating a use request of the connection paths, and arbitration means for respectively connecting the arbitration means and each node And a transmission means for transmitting a part or all of the information required for synchronous operation in the node and between the nodes from the node to the arbitration means using the arbitration signal path, and the transmission means. Based on the information transmitted from the node,
And a redistribution unit for redistributing a part or all of the information from the arbitration unit to each node by using the arbitration signal path. An information processing system characterized in that a synchronous operation is realized between processors in different nodes by reflecting on the internal bus of the node. 2. A means for the processor to load data using a first instruction that flags a corresponding address with a load instruction, and checks the flag for the corresponding address prior to executing the store. A means for executing a store if the flag is valid, and a data store using a second instruction for invalidating the flag, and an address at which the processor monitors the bus and executes the first instruction 2. The information processing system according to claim 1, further comprising: a bus monitoring unit that invalidates the corresponding flag when it detects that another processor has executed a store instruction at the same address. 3. The information processing system according to claim 1, wherein the arbitration signal path connects the arbitration means and each node in a one-to-one manner. 4. The information processing system according to claim 1, wherein the connection path is an optical wavelength-multiplexed connection path that connects using light of a plurality of wavelengths. 5. The information processing apparatus according to claim 1, wherein the connection path and the arbitration signal path are wavelength-division multiplexed and configured by a common optical fiber. 6. A plurality of nodes each having an internal bus and a processor for monitoring the bus to detect information required for a synchronous operation and executing a synchronous operation with another processor based on the information are provided, and the plurality of nodes are provided. An information processing method in an information processing system having a connection path capable of connecting a plurality of sets of nodes at the same time, wherein a part or all of the information required for the synchronous operation within the node and between the nodes is requested to use the connection path. Along with, a transmission step of transmitting from the node to the arbitration section using an arbitration signal path connecting between the arbitration section and each node, and an arbitration step of arbitrating a use request of the connection path by the arbitration section. And based on the information transmitted from the node in the transmitting step, a part or all of the information is redistributed from the arbitration unit to each node using the arbitration signal path. And a step of redistributing the information distributed to each node by the redistribution step.
An information processing method characterized in that a synchronous operation is realized between processors in different nodes by reflecting on the internal bus of each node.