JPH0916529A - Method and system for information processing - Google Patents

Abstract

PURPOSE: To provide an information processor capable of reducing processing according to a synchronous operation by a CPU spreading over nodes, reducing burden on the synchronous operation and improving the throughput of the whole system. CONSTITUTION: This system is an information processing system provided with plural nodes 100-400 equipped with one or more CPUs utilizing the snooping of a shared bus, respectively and in which each of the plural nodes 100-400 is disabled to snoop the information of a bus in the inside of the node and connected by a connection route 110, etc., and the system transmits the information required for the execution of the synchronous operation in the node or between the nodes via an optical fiber 31 that is a transmission line different from the connection route 100, etc., to an arbitor 20, and distributes a part of the information again to each of the nodes 100-400 based on the information. An operation to affect the information on its own node is performed based on re-distributed information in such way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing method and apparatus, for example, to an information processing method and apparatus which operate in synchronization with each other by referring to flags between a plurality of nodes.

[0002]

2. Description of the Related Art In a multiprocessor system, the following two types of methods have been generally adopted as a method of synchronizing CPUs.

1) A method for realizing a synchronization mechanism by allowing a single CPU to monopolize a shared bus to which the CPU is connected at a certain moment. 2) A load reserve instruction (LoadReserve instruction) that sets a reserve flag in accordance with the load instruction (hereinafter,
Called "LR". ) And one of the conditional store instructions, check the reserve flag before executing the store instruction, and execute the store instruction if the reserve flag is valid,
After that, a Store Conditional instruction (hereinafter, referred to as “SC”) that invalidates the reserve flag and the same address where another CPU executes the LR by snooping the bus. A store snoop function (hereinafter referred to as “SS”) that invalidates the reserve flag when it detects that a store instruction has been executed is provided with a synchronization mechanism by using these LR, SC, and SS. How to achieve.

The latter aims at further improving the performance in a multi-CPU system in that it does not use the monopoly of the bus as compared with the former.

On the other hand, when connecting a plurality of nodes each having one or more processors and memories for the purpose of exchanging data between the nodes, a method of connecting using various LANs,
A method has been adopted in which nodes are connected at the address level of memory regardless of LAN.

An example of the latter is an information processing apparatus using the optical wavelength multiplexing system of Japanese Patent Application No. 5-286876 filed by the present applicant. This system is characterized in that different data transfer can be realized simultaneously among a plurality of nodes by using a plurality of wavelengths.

Further, as an example of enabling the information processing apparatus using the optical wavelength division multiplexing method to perform complicated processing such as utilizing the synchronization between CPUs spanning nodes, the present applicant Japanese Patent Application No. Hei 6-21705
No. 3 and Japanese Patent Application No. 6-217054. In the systems in these examples, by collecting the information for realizing the synchronization between the CPUs spanning the nodes in the arbiter and redistributing it to each node, the CP spanning the nodes is expanded.
The synchronization between U is realized.

[0008]

However, as proposed in the above-described inter-CPU synchronization realization method,
In a system in which only the address and control information associated with the store instruction executed in each node is used as the information necessary for executing the synchronization operation, each time the synchronization information is received, that information is always sent to all nodes. Since information is exchanged even if the CPUs are not synchronized between the nodes, unnecessary processing and traffic are generated in the arbiter and each node.
It caused a decrease in performance.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to solve the above problems. Then, as one means for achieving the object, for example, the following configuration is provided.

That is, a plurality of nodes each having one or more CPUs that utilize snooping of a shared bus are provided, and each of the plurality of nodes is connected by a connection path that cannot snoop the information of the buses inside each other node. In the information processing system described above, an arbitration unit that arbitrates the use of the connection route, and a transmission route different from the connection route that connects the arbitration unit and the plurality of nodes to each other,
Transmission means for transmitting information necessary for executing a synchronous operation in the node and between the nodes to the arbitration means via the transmission path, and the transmission information of the transmission information based on the transmission information transmitted by the transmission means. Distributing means for redistributing a part of each from the arbitration means to each node, and reflecting means for reflecting the information distributed to each node by the distributing means to each node, the inter-CPU synchronous operation across the nodes The feature is that it is possible.

Then, for example, in order to realize the synchronous operation between the CPUs, if the reserve flag is checked by executing the load reserve instruction which sets the reserve flag in accordance with the load instruction and the store instruction and the reserve flag is valid. Executing a store instruction, and then executing a store instruction at the same address as the address at which the other CPU itself executed the store reserve instruction by disabling the reserve flag and the bus by snooping the bus. The store snoop function that invalidates the reserve flag when detecting
It is characterized in that it enables a synchronous operation between Us. Also,
For example, the CPU outputs the state of the reserve flag to the outside through a signal line so that the reserve flag can be recognized from the outside, and the information transmitted by the transmitting means includes address and control information associated with a store command executed in each node, and It is characterized by including information on the state of the reserve flag which has become recognizable.

Further, the distribution means controls distribution of the information from the arbitration means to each node based on the information on the state of the reserve flag in the information transmitted by the transmission means. . Alternatively, the reflecting means includes means for generating a store command inside the own node based on information transmitted from an external node, and the connection path is an optical transmission path connected via a star coupler, It is characterized by transmitting and receiving an optical signal obtained by wavelength-multiplexing an optical signal of the wavelength.

[0013]

In the above structure, the information necessary for executing the synchronous operation within the node or between the nodes is transmitted to the arbiter via the transmission route different from the connection route, and the arbiter transmits one of the information. Redistribute the copies to each node based on that information. Based on the information redistributed in this way, when performing the synchronization holding operation between the CPUs by operating to reflect the information in the own node, the processing accompanying the synchronization operation by the CPUs across the nodes is performed. It is possible to reduce the load in performing the synchronous operation and improve the processing capability of the entire system.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of an information processing apparatus system according to an embodiment of the present invention. In the figure, 100, 20
0, 300, 400 are nodes, and each node has a pair of optical fibers 31, 32, 3 up to the concentrator 30.
They are connected by a connection path constituted by 3, 34. The concentrator 30 includes optical fibers 31, 32,
It contains a star coupler 50 for redistributing the signal coming from the connection path constituted by 33, 34.

Each node has a CPU 101, 20 in it.
1, 301, 401, memories 102, 202, 302,
403, interface circuits 103, 203, 303, 40 for connecting a connection path formed by the optical fibers 31, 32, 33, 34 and the inside of each node
3. Arbitration interface circuits 104, 204, 304, 40 for requesting the use of the connection path constituted by the optical fibers 31, 32, 33, 34
4 and internal buses 105, 205, 305, 405 for interconnecting them inside the node, synchronization information receiving circuits 107, 207, 307, 407, wavelength division multiplexer 1
08, 208, 308, 408 are included.

Further, the arbitration interface circuit includes synchronization request detecting devices 106, 206, 306 and 406 for detecting a synchronization related instruction on the internal bus and notifying the arbiter 20 of the synchronization related instruction. There is. In addition, each CPU 101, 201, 301, 4
From 01, the RSRV signal reflecting the state of the internal reserve flag (driven to H when the reserve flag is valid (1)) 109, 209, 309, 409
Is output, and the synchronization request detection devices 106, 206,
306 and 406 and the synchronization information receiving circuits 107 and 207,
307 and 407 respectively.

The above description is an example of the configuration of the present embodiment, and the present invention is not limited to the above-mentioned example.

The arbiter 20 includes optical fibers 31, 32,
The arbiter 20 is for arbitrating the use of the connection path constituted by 33 and 34.
They are connected by 0,410.

In addition, inside the arbiter 20, a packet information management device 21 that manages packets sent from each node, a route selection information management device 22 that manages route request information among the information included in the packets, and those. An additional information management device 23 that temporarily stores additional information associated with data transfer such as an address sent following information, and information that is necessary to implement the inter-CPU synchronization mechanism in a packet. A synchronous information management device 24 is installed which controls the redistribute of protocol information to each node.

The synchronization information management device 24 connects the synchronization information notification optical signal path 35 to the star coupler 50 inside the concentrator 30.

In this embodiment, in the system having the configuration shown in FIG. 1, the state of the RSRV signal line is changed by the arbiter 20.
And centrally manage the synchronization information through the arbiter 20 and broadcast the synchronization information from the arbiter 20 to each node as needed based on the state of the RSRV signal line so that bus snoops cannot be performed mutually. An example of realizing an inter-CPU synchronization mechanism across nodes under a situation is shown.

Specifically, the CPU 10 on the node 100
1 and the CPU 201 on the node 200 and the CPU 301 on the node 300 try to synchronize the data in the memory 202 on the node 200, the CP associated therewith
It shows how the inter-U sync hold operation is implemented.

FIG. 2 is an address map of the entire system. In this embodiment, 4 gigabytes of the address space of the entire system is distributed to four nodes for use. As shown in FIG. 2, the memory space of the node 100 is “00000”.
From address 000h to address "3ffffffffh", memory space is similarly assigned to each node.

Now, when the CPU 101 on the node 100 loads the data (4 bytes) at the address 41000000h on the RAM 202 of the node 200 using the [LR] instruction, the reserve flag inside the CPU 101 becomes valid. Along with that, the state of the RSRV signal line 109 transits from L to H. At this time, the synchronization request detection device 106 that has detected the state transition generates a synchronization flag registration request packet as shown in FIG.

Next, the arbiter interface will be described. FIG. 4 shows the arbiter interface 10 shown in FIG.
4 is a block diagram showing a detailed configuration of No. 4. Although the following description will be given for the arbiter interface 104, the arbiter interfaces 104, 204, 304 of FIG.
All 404 have the same configuration, and description of other arbiter interfaces will be omitted.

As shown in FIG. 4, the arbiter interface 1
In 04, when the RSRV flag monitoring device 182 in the synchronization request detecting device 106 existing inside the arbiter interface 104 detects that the RSRV signal has changed from L to H, the result is set as the synchronization flag registration request signal 183. , Passes control to a program running on the node arbitration control processor 141.

Node Arbitration Processor 14
In the first embodiment, the 1-chip microcontroller is used in the present embodiment, but the configuration is not limited to the above.
Of course, it may be configured by hardware logic or the like.

The node arbitration processor 141 notified by the synchronization flag registration request signal 183.
Creates the synchronization flag registration packet shown in FIG. 3 and writes it in the parallel / serial converter 161. The parallel / serial converter 161 converts the written information into serial data and outputs it to the light emitting element 163.
The light emitting element 163 photoelectrically converts the input signal and outputs it to the arbiter 20 as an optical signal of wavelength λ1 through the communication path 110 formed of an optical fiber. The light emitting element here is an element such as an LED or a laser, and the light receiving element is an element represented by a photodiode.

Next, the details of the arbiter 20 described above will be described by temporarily suspending the description of FIG. FIG. 5 is a block diagram showing a detailed configuration of the arbiter unit 20. In FIG. 5, 60
Reference numerals 1, 603, 605, and 607 are light receiving elements. The light receiving elements 601, 603, 605, 607 receive the optical signals of the wavelength λ1 emitted by the respective nodes and convert them into corresponding electrical signals. Then, the converted electric signal is sent to the serial / parallel converter 611.

Now, when the synchronization flag registration request packet arrives from the node 100 and the light receiving element 601 receives it, the serial / parallel converter 61 after conversion into an electric signal.
1 is input. The serial / parallel converter 611 converts the input serial electric signal into a parallel signal. At the same time, the data reception detection signal 1 (62
By 2), the packet information management device 21 is notified of this.

In this embodiment, the packet information management device 21
ROM storing programs and RAM used for processing
It is composed of a micro controller 621 having a built-in. Further, the microcontroller 621 is assumed to include a part which plays a role of the route selection information management device 22, the additional information management device 23, and the synchronization control information management device 24 at the same time. However, this configuration is not limited to the above example.

Upon receiving the data reception detection signal 1 (622), the packet information management device 21 selects the serial / parallel converter 611 by the device select signal 619, and the internal register through the data bus 620.
The packet sent from the node 100 is read.

Since the received packet is a synchronization flag registration request packet, the content of this packet is passed to the part of the microcontroller which functions as the synchronization control information management device 24. Synchronization information management device 24
Registers the fact that the reserve flag is turned on in the node 100 in an internal table in order to maintain the synchronization between the CPUs spanning each node based on the information provided to itself.

The processor 101 in the node 100
The process of loading the data in the RAM 41000000h in the node 200 is described in Japanese Patent Application No. 5-28871.
This is realized by reading the data between the nodes as shown in No.

The CPU 201 on the node 200 and the CPU 301 on the node 300 are also RAs of the node 200.
It is assumed that the data (4 bytes) at the address 41000000h on the M201 has been loaded using the [LR] instruction and the reserve flag is enabled. This information is also sent to the synchronization information management device 24 inside the arbiter 20, and the node 200 and the node 300 also read R
The fact that the SRV flag is turned on is registered in the internal table.

Under this state, the CPU 101 in the node 100 now issues the [SC] command, and the node 200
The operation of the system in the case of disabling the reserve flag of the node 300 will be described below.

Returning to the explanation of FIG. Address decoder 140 existing inside the arbiter interface 104
Constantly monitors the internal bus 105 (105 is composed of a data signal line 151, a control signal line 152, and an address signal line 153) of the node 101, and accesses (address in this case, the node 200) to an external node (in this case, the node 200). (Write operation to 41000000h) has occurred on the bus, control is passed to the program operating on the node arbitration control processor 141 by the external access detection signal 144 and the write request detection signal 150.

At the same time, the address latch register 142
Then, the address output on the address signal line 153 at that time is latched, and the control signal latch register 143
The read / write request type (write) is latched in, and control information such as the number of transfer bytes (4 bytes) is latched.

At this time, the control signal decoder 180 existing inside the synchronization request detecting device 106 constantly monitors the control signal line 152 in parallel and stores a store instruction (in this case, the address 41000 on the node 200).
When the [SC] instruction to 000h) is recognized on the bus, the store request detection signal 181 notifies the program operating on the node arbitration control processor 141 that synchronization control is required.

The node arbitration processor 141 notified from the external access detection signal 144, the write request detection signal 150, and the store request detection signal 181.
Reads the signals latched by the address latch 142 and the control signal latch 143, determines the connection destination, creates an arbitration request packet as shown in FIG. 6, and writes it in the parallel / serial converter 161. The packet shown in FIG. 6 is a route request signal and also includes, as information, a portion for notifying the arbiter of the synchronization control request.

The parallel / serial converter 161 converts the written information into serial data, and the light emitting element 1
63. The light emitting element 163 photoelectrically converts the input signal and outputs it as an optical signal of wavelength λ1 to the arbiter 20 through the passage 110 formed of an optical fiber.

Referring again to FIG. 5, the arbitration request packet now arrives from the node 100 and is input to the serial / parallel converter 611. The serial-to-parallel converter 611 converts the input serial electric signal into a parallel signal and outputs the data reception detection signal 6
22 is used to notify the packet information management device 21.

Upon receiving the data reception detection signal 1 (622), the packet information management device 21 selects the serial / parallel converter 611 by the device select signal 619, and the internal register through the data bus 620.
The arbitration request packet sent from the node 100 is read.

Of the information included in the request packet, the information on the request source node number is the route selection information management device 2
The part of the additional information that is transferred to the second data storage unit 2 is stored in the part of the micro controller 621 that serves as the additional information management device 23. Further, when it is determined that this packet is associated with the inter-CPU synchronization holding operation, the inter-CPU synchronization holding operation in each node is necessary, so the information in the request packet and the request source node number is It is stored in a part that functions as the synchronization control information management device 24 in the microcontroller.

The route selection information management device 22 analyzes the received data, and the request to use this transmission line is sent to the node 100.
It recognizes that it is a connection request to the node 200, checks the transmission path use state flag provided in the route selection information management device 22 and the wavelength in use, and if the state is available, sets the flag. It is set to the in-use state, and the connection preparation request packet shown in FIG. 7 is created and written in the parallel / serial converters 612 and 614.

The connection preparation packet shown in FIG. 7 also includes information provided from a part of the additional information management device 23 in the microcontroller 621 and wavelength information. These two connection preparation request packets use the optical signal of λ1 as in the case of the optical arbiter interface and are output to the node 100 and the node 200.

Note that the four nodes can simultaneously perform two-system communication between the one-to-one nodes by using different wavelengths λ2 and λ3 for data communication.

Following this, the synchronization information management device 24 determines the CPU in each node based on the information provided to it.
In order to maintain the synchronization between them, first, it is checked whether the reserve flag is set in any of the current nodes. In this case, the nodes 100, 200, and 3
Since the notification from 00 has been received by the synchronization flag registration request packet, the existence of the node whose reserve flag is ON is recognized. So the address 410000
When the reserve flag is set in correspondence with the address 00h, an instruction to invalidate the reserve flag is made. Therefore, a synchronization flag invalidation packet as shown in FIG. 8 is created and written in the parallel / serial converter 627.

As a result of checking the internal table,
When the reserve flag is not valid in all the nodes, a series of operations for flag invalidation instruction is not performed.

The written packet is transmitted through the light emitting element 610 onto the synchronization information notification optical signal path 35 using the wavelength λc, and is input to the star coupler 50 inside the concentrator 30. At this time, λc is different from the wavelengths λ2 and λ3 used for data transmission in order to prevent interference. The synchronization flag invalidation packet input to the star coupler 50 is evenly demultiplexed by each node and output to each node through the optical fibers 31, 32, 33, 34.

The reserve flag invalidation operation for maintaining the synchronization between the CPUs in the nodes 200 and 300 will be described below by taking the operation in the node 300 as an example. FIG. 9 shows a detailed configuration diagram of the synchronization information receiving circuit 307 and the optical multiplexer 308.

In FIG. 9, the optical signal input through the fiber 33 is divided into light (λ2 and λ3) directed to the connection path interface 303 by the optical demultiplexer 176 and light (λc) directed to the synchronization information receiving circuit 307. To be separated.
The light of λc input to the synchronization information receiving circuit 307 is converted into an electric signal by the light receiving element 169, and further serial / serial
At the same time as being converted into a parallel signal by the parallel converter 170, it is notified to the synchronization control microcontroller 172 by the synchronization maintenance packet reception signal 171.

Upon receiving this signal, the microcontroller 172 checks the state of the RSRV signal line 109. When the RSRV signal line 109 is H (the reserve flag is valid), synchronous maintenance is required. In that case, when this notification is detected, the node 3
00 synchronous control micro controller 172 receives the device select signal 1 from the serial / parallel converter 170.
73, the data bus 175 is used to read the synchronization flag invalidation packet shown in FIG. 8 and request the use permission of the internal bus 305 toward the inside of the node.

The synchronous control microcontroller 172 is
When the use permission of the internal bus is given, the connection path interface 30 is used by using the synchronous maintenance request signal group 174.
3 to the address 41 based on the contents of the packet in FIG.
It instructs the CPU that sets the reserve flag in relation to the address of 000000h to issue the bus access for invalidating the flag on the internal bus 305.

FIG. 10 shows the connection path interface unit 303.
The detailed configuration example of is shown. Here, the address (130000000h) is sent to the data transfer sequencer 13 by the synchronous maintenance request signal group 174 sent from the synchronous control microcontroller 172.
At 1, an instruction to invalidate the synchronization flag is instructed. In this case, specifically, the address 4100 on the internal bus 305
Store of dummy data of 0000h is instructed.

The sequencer 131 instructs the address driver to drive the address 41000000h by the signal 134. Then, the control driver 132
For the transfer size and the driving of the control signal for executing the store instruction to the bus through the signal line 136. Further, through the signal line 137, the data buffer 133 is instructed to drive the dummy data onto the bus.

Store the dummy data in the [SS]
The in-node processor 301 snooped as is inspects the reserve flag held by itself and the register holding the address that has raised the flag. In the case of the present embodiment, since the addresses match, the reserve flag is invalidated.

When the reserve flag is invalidated, RSR
The V signal line 109 transits from H to L. R in the synchronization request detection device 106 in the arbiter interface 104
The SRV flag monitoring device 182 changes the RSRV signal from H to L.
When it is detected that the change has occurred, the result is used as a synchronization flag registration deletion request signal 184, and control is passed to the program operating on the node arbitration control processor 141.

The node arbitration processor 14 notified by the synchronization flag deregistration request signal 184.
1 creates a synchronization flag registration deletion request packet as shown in FIG. 11 and sends it to the arbiter 20. The arbiter 20, which has received the synchronization flag registration deletion request packet, transfers it to the synchronization control information management device 24. The synchronization control information management device 24 checks the information registered in the internal table based on the received information, and deletes the information that the reserve flag of the node 100 is valid.

On the other hand, since the relevant address does not exist in the memory 302, this store processing is ignored. The data transfer sequencer instructs the control driver 132 after a certain delay to drive the acknowledge signal in order to prevent the bus from timing out.

The synchronization flag invalidation packet is also sent to the nodes 100, 200 and 400, but in the node 400, the state of the RSRV signal line 409 is L (the reserve flag is not valid). Therefore, the processing on the internal bus 405 is not executed. Further, the requesting node 100 receives the synchronization flag invalidation packet, interprets the contents of the packet, and when the node number is found to be in the requesting source field inside the packet, the packet is executed by the packet. Subsequent processing that should have been done is ignored.

Further, the node 200 which is the data transfer destination
Then, when the synchronization flag invalidation packet is received, the received contents are interpreted, and the address of the own node is found inside the packet, the subsequent processing supposed to be performed by the packet is ignored.

The series of operations in the node 300 is performed in a system using a CPU in which the control of the address bus and the data bus is independent.
It is also possible to define it as an address-only transaction. In this case, these reserve flag invalidation processes can be completed only in the address phase and can be realized without driving dummy data onto the bus.

On the other hand, in the node 200 which is the correct data transfer destination, the transfer is performed as shown in Japanese Patent Application No. 5-288271, and the data storage process is performed.
This data store is a formal data transfer unlike the one in the node 300.
[SS] is executed in the same manner as the operation in 1. As a result, the synchronization flag of the CPU is checked and the reserve flag is invalidated, so that the synchronization operation is guaranteed. The synchronization flag deregistration packet is sent to the arbiter 20 when the synchronization flag is invalidated, as in the case of the node 300.

As a result, the synchronization holding operation between the CPUs is realized when the [SC] instruction of the node 100 is executed. The same processing as described above is performed for transfer between other nodes. A description of transfer processing between these other nodes is omitted.

In this embodiment, the arbitration signal paths 110, 210, 310 and 410 shown in FIG. 1 are used.
For the optical signal above, the light of wavelength λ1 is used, and the connection path 3
The wavelengths λ2 and λ3 are included in the optical signals on 1, 32, 33 and 34.
(Λ2 and λ3 are different wavelengths), but λ1 = λ
2. Even if λ1 = λ3, there is no problem in the structure.

Next, in the case of a synchronous instruction to the data on the memory inside the self node, specifically, the CP on the node 100.
010 on the RAM in its own node that U can use for the synchronization instruction
If the data at address 00000h (4 bytes) is loaded using the [LR] instruction and you try to change it by issuing the [SC] instruction, how will the synchronization holding operation be carried out accordingly? Will be explained.

In FIG. 4, in this case, the external access detection signal 144 does not react, and the write request detection signal 15
0, and control is passed to the program operating on the node arbitration control processor 141 by the store request detection signal 181. Address latch register 1 at the same time
42 latches the address output on the address signal line 153 at that time, and the control signal latch register 14
The control information such as the number of transfer bytes (4 bytes) is latched in 3.

Node Arbitration Processor 14
1 reads out the signals latched by the address latch 142 and the control signal latch 143, and FIG.
Create the synchronous maintenance request packet shown in
Write to the parallel / serial converter 161. The parallel / serial converter 161 converts the written information into serial data and outputs it to the light emitting element 163. The light emitting element 163 photoelectrically converts the input signal and uses the communication path 11 configured by an optical fiber as an optical signal of wavelength λ1.
Output to arbiter 20 through 0.

In FIG. 5, when a cache maintenance request packet arrives from the node 100, this packet is input to the serial / parallel converter 611. The serial / parallel converter 611 converts the input serial electric signal into a parallel signal, and at the same time, by the data reception detection signal 622, the packet information management device 21.
Notify.

Upon receipt of the data reception detection signal 1 (622), the packet information management device 21 selects the serial / parallel converter 611 by the device select signal 619 and sends it from the node 100 through the internal register through the data bus 620. Read the synchronized maintenance request packet. Then, the address, the number of transfer bytes, the requesting node number, and the like in the packet are stored in a portion of the microcontroller 621 that serves as the synchronization information management device 24.

The synchronization information management device 24 examines the internal table, and if any of the nodes has the reserve flag enabled, the synchronization information management device 24 sends the data to each node in order to maintain the CPU synchronization in each node. Address 0100
When the reserve flag is set for the data of 0000h, it is instructed to invalidate the reserve flag. Therefore, a synchronization flag invalidation packet as shown in FIG. 8 is created and written in the parallel / serial converter 627. The written packet is converted into an optical signal by the light emitting element 628 and distributed to all nodes through the star coupler 50.

Since the operation thereafter is the same as that of the previous example, description thereof will be omitted. As described above, according to the present embodiment, the information necessary for executing the synchronous operation within the node or between the nodes is transmitted to the arbiter through the transmission path different from the connection path, and the arbiter transmits the information. By redistributing a part of the information to each node based on the information, the information can be reflected in the own node based on the redistributed information, and the synchronization is maintained between the CPUs. When an operation is executed, it is possible to reduce the processing involved in the synchronous operation by the CPU across nodes, reduce the load in performing the synchronous operation, and improve the processing capacity of the entire system.

(Other Embodiments) In the above-described embodiment, when the synchronization related information is redistributed from the arbiter 20 to each node, the synchronization information notifying optical signal path 35 and the dedicated wavelength λc are used. It was done by broadcasting. However, the present invention is not limited to the above examples, and R
If the information based on the SRV signal line is used effectively, the same effect can be obtained without providing those devices. The method will be described below. The same parts as those in the first embodiment described above are designated by the same reference numerals and detailed description thereof will be omitted.

FIG. 13 is a block diagram of a system used in the second embodiment according to the present invention. The difference from FIG. 1 is that the wavelength multiplexing device and the synchronization information receiving circuit are not required in each node, and the synchronization information notification optical signal for broadcasting from the synchronization information management device 24 inside the arbiter 20. There is no route 35.

The difference between the first embodiment and this second embodiment lies essentially in how the synchronization information is distributed from the arbiter to each node. The description will be given below with reference to FIG. 14 showing the details of the arbiter 20 shown in FIG. 13 of the second embodiment.

Specifically, the CPU 10 on the node 100
1 and the CPU 201 on the node 200 and the CPU 301 on the node 300 are 4 on the memory 202 on the node 200.
The following shows how the arbiter distributes the synchronization information in the CPU-to-CPU synchronization holding operation when the synchronization is attempted with respect to the data (4 bytes) at the address 1000000h. Various items prior to the distribution of the synchronization information (execution of the [LR] instruction in each node, detection of the state change of the RSRV flag, notification to the arbiter and registration in a table, detection of the [SC] instruction, The notification to the arbiter) is the same as that in the first embodiment, and will be omitted.

FIG. 14 is a block diagram of the arbiter in the second embodiment. Now from node 100 [S
C] An arbitration request packet accompanying instruction detection arrives and is input to the serial / parallel converter 611. The serial / parallel converter 611 converts the input serial electric signal into a parallel signal and notifies the packet information management device 21 of the data reception detection signal 622.

Upon receiving the data reception detection signal 1 (622), the packet information management device 21 selects the serial / parallel converter 611 by the device select signal 619, and the internal register through the data bus 620.
The arbitration request packet sent from the node 100 is read. Of the information included in the request packet, the information of the request source node number is transferred to the route selection information management device 22, and the portion of the additional information related to the data transfer serves as the additional information management device 23 in the microcontroller 621. Is stored in the part that fulfills.

Further, when it is determined that this packet is accompanied by the CPU CPU synchronous holding operation, the CPU CPU synchronous holding operation at each node is required. Therefore, the address in the request packet, the request source node number, etc. The information is stored in the part of the microcontroller 621 that serves as the synchronization control information management device 24.

The route selection information management device 22 analyzes the received data, and the request to use this transmission line is sent to the node 100.
It recognizes that it is a connection request to the node 200, checks the transmission path use state flag provided in the route selection information management device 22 and the wavelength in use, and if the state is available, sets the flag. Set to the in-use state. Then, the connection preparation request packet shown in FIG. 7 is created and written in the parallel / serial converters 612 and 614.

This connection preparation packet also includes the information provided from the part of the additional information management device 23 in the microcontroller 621, and the wavelength information. These two connection preparation request packets are output to the node 100 and the node 200 using the optical signal of λ1 as in the case of the optical arbiter interface.

Following this, the synchronization information management device 24
C at each node based on the information provided to me
In order to maintain the synchronization between PUs, it is first checked whether any node currently has a reserve flag. In this case, the nodes 100, 200,
Since the notification is received from the synchronization flag registration packet from 300, the existence of three nodes whose reserve flags are ON is recognized.

Next, the synchronization information management device 24 determines the node that must perform the synchronization flag invalidation processing according to an instruction from the arbiter. In this case, node 10
For 0 and 200, the maintenance of the synchronization flag is executed by the actual data transfer, but in the node 300 that is not directly involved in the data transfer, the arbiter needs to instruct the synchronization flag to be invalidated. Therefore, the synchronization information management device 24 creates a synchronization flag invalidation packet as shown in FIG. 8 in order to instruct to invalidate the reserve flag when the reserve flag is set in correspondence with the address 41000000h. . Then, the packet information management device 21 is instructed to write to the parallel / serial converter 616 in order to send the synchronization flag invalidation packet through the arbitration path 310 connected to the node 300.

As a result of checking the internal table,
If the reserve flag is not valid in all nodes, and if the reserve flag is valid but the node is the direct target of data transfer, a series of operations for flag invalidation is performed. Absent.

The written packet is transmitted through the light emitting element 606 to the wavelength λ on the arbitration signal path 310.
It is sent using 1. In the above description, an example in which the number of nodes to which the synchronization flag invalidation packet is sent is one has been described. However, when there are a plurality of nodes, the packets are sequentially written to the respective parallel / serial converters in the same manner. It is sent to each node.

Next, the node 30 which receives this packet
The operation of 0 will be described below. The following description will be made with reference to FIG. 4 described above.

At node 300, fiber 310
The optical signal input by (110 in FIG. 4) is converted into an electrical signal by the light receiving element 164 and input into the optical arbiter interface 304 (104 in FIG. 4). In the optical arbiter interface 304, the input signal is converted into a parallel signal by the serial / parallel converter 162 and, at the same time, is notified to the node arbitration control processor 141 by the data reception signal 148.

When this notification is detected, the node arbitration processor of the node 300 reads out the above-mentioned synchronization flag invalidation packet from the serial / parallel converter 162 using the device select signal 147 and the data bus 145, and stores it in the node. To request permission to use the internal bus 305.

When the use permission of the internal bus is given, the node arbitration control processor uses the data transmission / reception request signal group 149 to establish the connection path interface 303.
On the other hand, based on the contents of the packet of FIG.
It instructs the CPU that sets the reserve flag in relation to the address of 000000h to issue the bus access for invalidating the flag on the internal bus 305. Since the dummy data store process can be performed in the same manner as in the first embodiment, the description thereof will be omitted here.

With the above arrangement, the same operational effect as that of the first embodiment can be obtained with a more simplified structure, and the synchronization related information can be multicast only to the necessary nodes. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device.

Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0094]

As described above, according to the present invention, C
When executing the synchronization holding operation between PUs, the processing associated with the synchronization operation by the CPU across the nodes is reduced, the load on performing the synchronization operation is reduced, and the processing capacity of the entire system is improved. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration of an embodiment according to the present invention.

FIG. 2 is a diagram showing an address map of the system of this embodiment.

FIG. 3 is a diagram showing a structure of a synchronization flag registration request packet used in this embodiment.

FIG. 4 is a diagram showing a detailed configuration of an arbiter interface in the node of this embodiment shown in FIG.

5 is a diagram showing a detailed configuration of an arbiter of the present embodiment shown in FIG.

FIG. 6 is a diagram showing the structure of an arbitration request packet used in this embodiment.

FIG. 7 is a diagram showing a structure of a connection preparation request packet used in this embodiment.

FIG. 8 is a diagram showing a structure of a synchronization flag invalidation packet used in this embodiment.

FIG. 9 is a diagram showing a detailed configuration of a synchronization information receiving circuit of the present embodiment.

FIG. 10 is a diagram showing a detailed configuration of a connection path interface unit of the present embodiment.

FIG. 11 is a diagram showing the configuration of a synchronization flag registration deletion request packet used in this embodiment.

FIG. 12 is a diagram showing the structure of a synchronous maintenance request packet used in this embodiment.

FIG. 13 is a diagram showing a system configuration of a second exemplary embodiment according to the present invention.

14 is a diagram showing a detailed configuration of the arbiter of the second embodiment shown in FIG.

[Explanation of symbols]

20 arbiter 21 packet information management device 22 route selection information management device 23 additional information management device 24 synchronization information management device 30 concentrator 31, 32, 33, 34 optical fiber 35 optical signal route for synchronization information notification 50 star coupler 100, 200, 300 , 400 nodes (a group of information processing devices having one or more processors and memories) 101, 201, 301, 401 CPUs (processors) 102, 202, 302, 402 memories 103, 203, 303, 403 connection path interface circuit 104 , 204, 304, 404 Arbiter interface circuit 105, 205, 305, 405 Node internal bus 106, 206, 306, 406 Synchronization implementation device 107, 207, 307, 407 Synchronization information receiving circuit 108, 208, 308, 4 08 wavelength multiplexer 109, 209, 309, 409 RSRV signal 110, 210, 310, 410 arbitration signal path 130 address driver 131 data transfer sequencer 132 control driver 133 data buffer 134 address drive signal 135 acknowledge signal 136 control driver control signal 137 data buffer control signal 138 data reception signal 139 parallel / serial converter control signal 140 address decoder 141 node arbitration control processor 142 address latch register 143 control signal latch register 144 external access detection signal 145 data signal line 146 register select signal line 147 device Select signal line 148 Data reception signal 149 Over data reception request signal group 150 write request detection signal 151 internal bus of the data signal lines 152 internal bus of the control signal line 153 an internal bus of the address signal lines 161,165,612,614,616,618,6
28 Parallel / serial converters 162, 166, 170, 611, 613, 615, 6
17 Serial / parallel converter 163, 167, 602, 604, 606, 608, 6
28 Light-Emitting Element 164, 168, 169, 601, 603, 605, 6
07 Light emitting element 171 Synchronous maintenance packet reception signal 172 Synchronous control microcontroller 173 Device select signal 174 Synchronous maintenance request signal group 175 Data signal line 176, 631, 632, 633, 634 Two wave demultiplexer 177, 641, 642, 643 644 2-wave multiplexer 178 3-wave demultiplexer 180 Control signal decoder 181 Store request detection signal 182 RSRV flag monitoring device 183 Sync flag registration request signal 184 Sync flag registration deletion request signal 619 Device select signal 620 Data bus 621 Microcontroller 622 , 623, 624, 625 data detection signal 1,
2,3,4 626 control signal

Claims (12)

[Claims] 1. A plurality of nodes, each comprising one or more CPUs that utilize snooping a shared bus,
An information processing system in which each of the plurality of nodes is connected by a connection path that cannot snoop the information of the bus inside each other node, and an arbitration unit that arbitrates the use of the connection path, the arbitration unit, and the plurality of nodes. A transmission path different from the connection path connecting the nodes to each other, and transmission means for transmitting information necessary for executing a synchronous operation in the node and between the nodes to the arbitration means via the transmission path, Distribution means for redistributing a part of the transmission information from the arbitration means to each node based on the transmission information transmitted by the transmission means, and reflecting the information distributed to each node by the distribution means to each node An information processing system comprising: a reflection unit, which enables a CPU synchronous operation across nodes. 2. A load reserve instruction for setting a reserve flag in accordance with a load instruction as an inter-CPU synchronization mechanism,
Before the store instruction is executed, the reserve flag is checked, and if the reserve flag is valid, the store instruction is executed, and after that, the store conditional instruction that invalidates the reserve flag and another CPU by snooping the bus A store snoop function that invalidates a reserve flag when it detects that it has executed a store instruction at the same address as the address at which it has executed the load reserve instruction is provided, thereby enabling a synchronous operation between the CPUs. The information processing system according to claim 1, which is characterized in that. 3. The CPU outputs the state of the reserve flag to the outside through a signal line, and the state of the reserve flag can be recognized from the outside by checking the signal line, and the information transmitted by the transmitting means. 3. The information processing system according to claim 2, wherein the information includes address and control information associated with a store instruction executed in each node, and information about the state of the recognizable reserve flag. 4. The distribution means controls distribution of the information from the arbitration means to each node based on information about a state of a reserve flag in information transmitted by the transmission means. The information processing system according to item 3. 5. The information processing according to claim 2, wherein the reflecting means includes means for generating a store instruction inside the own node based on information transmitted from an external node. system. 6. The information processing system according to claim 1, wherein the connection path is an optical transmission path connected via a star coupler. 7. The information processing system according to claim 1, wherein the connection path transmits and receives an optical signal in which optical signals of a plurality of wavelengths are wavelength-division multiplexed. 8. A plurality of nodes each comprising one or more CPUs utilizing snooping of a shared bus,
Each of the plurality of nodes is connected by a connection path that cannot snoop the bus information inside the other node, and an arbitration unit that arbitrates the use of the connection path and the arbitration unit and the plurality of nodes are connected to each other. A transmission path different from the connection path, transmission means for transmitting information necessary for executing a synchronous operation within a node and between nodes to the arbitration means, and transmission by the transmission means An information processing system that redistributes a part of the transmission information from the arbitration means to each node based on the transmitted transmission information, and reflects the information distributed to each node by the distribution means to each node. In the information processing method in, the reserve flag is set before the load reserve instruction that sets a reserve flag according to the load instruction and the store instruction are executed. Check the memory and execute a store instruction if the reserve flag is valid, and then use a store conditional instruction to invalidate the reserve flag. An information processing method characterized by enabling a synchronous operation between the CPUs by having a function of invalidating a reserve flag when detecting that a store instruction is executed at the same address as an instruction execution address. 9. The CPU outputs the state of the reserve flag to the outside through a signal line, and the state of the reserve flag can be recognized from the outside by checking the signal line, and the information transmitted by the transmission means. 9. The information processing method according to claim 8, wherein the information includes an address and control information associated with a store instruction executed in each node, and information about a state of the recognizable reserve flag. 10. The information according to claim 9, wherein distribution of the information from the arbitration means to each node is controlled based on information on a state of a reserve flag among information transmitted by the transmission means. Processing method. 11. The information distributed to each node is reflected in each node by generating a store instruction inside the self node based on the information transmitted from the external node. The information processing method according to any one. 12. The connection path is an optical transmission path connected via a star coupler, and transmits / receives an optical signal in which optical signals of a plurality of wavelengths are wavelength-division multiplexed. 11. The information processing method according to any one of 11.