JPH088260A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to eliminate soft errors due to a rays in a flip chip semiconductor device. CONSTITUTION:A first insulating layer 6, a wiring layer 7 and a second insulating layer 8 are formed on a semiconductor substrate 1 on which a plurality of transistors 14 are formed in a matrix pattern. Vias are formed in the first and second insulating layers 6, 8, and the transistors 14 are connected with solder bumps 11 formed on the second insulating layer 8 to form a semiconductor device. The vias are formed in such a pattern that the first vias formed in the first insulating layer 6, directly above each of the transistors 14 and the second vias 9 formed in the second insulating layer 8, directly under the solder bumps 11 are staggered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which soft errors due to α rays are reduced. Since information processing devices are required to process a large amount of information quickly, the capacity of information processing devices has been increased, and the semiconductor devices, which are the main components of the devices, have been increased in capacity by reducing the size of the unit elements.
Has been put to practical use, and further development of ULSI is underway.

As a packaging method for semiconductor devices, a flip chip structure is widely used along with a TAB (Tape Automated Bonding) structure. This structure is used for a transistor formed in a matrix on a semiconductor substrate. Insulate by providing a first insulating layer on top of this, and also provide a via to this first insulating layer to draw out the emitter, base, and collector wiring of the transistor, and then pattern a conductor line on this. Then, a first wiring layer is formed and circuit connection of a large number of transistors formed in a matrix is performed. Next, a second insulating layer is provided on the first wiring layer and a second insulating layer is formed. Vias are provided in the insulating layer and solder bumps for external connection are provided on the vias.

Here, lead (Pb) alloy is often used as a constituent material of solder bumps, but natural Pb is composed of four isotopes, namely ²⁰⁴ Pb, ²⁰⁶ Pb, ²⁰⁷ Pb, ^208.
Since it is a mixture of Pb and is the final product of the thorium (Th) decay series, uranium (U) decay series, and actium (Ac) decay series, it emits α rays with α decay and emits this α ray. However, there is a problem that the semiconductor device receives a soft error.

[0004]

2. Description of the Related Art FIG. 2 shows a conventional flip chip structure.
A partial sectional view (A) and a plan view (B) of a semiconductor device are shown.
For example, p-type silicon substrate (p-Si substrate)
In each of the multiple transistor formation positions above 1,
The buried region 2 (see FIG.
After forming the collector region), CVD (vapor phase) is formed on this substrate.
N-Si layer 3 is epitaxially grown by the growth method).
Then, ion implantation is selectively performed at the transistor formation position.
And p-Si area 4 (base area) and n ⁺Si
Region 5 (emitter region) is created and diffusion is performed to
Form a register.

Next, the silicon dioxide (S
A first insulating layer 6 made of, for example, iO ₂ ) or silicon nitride (Si ₃ N ₄ ) is formed, and a first via (for forming a circuit connection with the collector region, emitter region, and base region of each transistor) is formed on the first insulating layer 6. Via) is formed, and the wiring layer 7 made of a fine conductor line connecting the respective transistors is formed on the first insulating layer 6.

Next, on this wiring layer 7, SiO ₂ and Si _{3 are formed.}
After providing and insulating the second insulating layer 8 made of N ₄ , a second via 9 is formed in the second insulating layer 8 for external connection,
A semiconductor device in which solder bumps 11 are arranged in a matrix as shown in FIG. 1B by providing solder bumps 11 via pads 10 made of a nickel (Ni) / gold (Au) bonding layer or the like. Is completed.

However, since the α-ray is generated from Pb forming the solder bump 11 and the transistor malfunctions, the solder bump 11 cannot be formed right above the transistor. Therefore, the solder bump 11 is formed far away from the transistor as shown in FIG.

Specifically, as shown in FIG. 1B, transistors are formed in a matrix at the center of the Si substrate 1 to form an active region 13, and solder bumps are formed so as to surround the active region 13.
By setting 11, the occurrence of soft error was prevented.

However, from LSI to VLSI, further UL
At present, as the degree of integration increases to SI, a semiconductor device can be miniaturized if a solder bump can be formed on an active region in which a transistor is formed. Therefore, various structures have been proposed.

For example, in FIG. 3, the thickness of the second insulating layer 8 is about 50.
By increasing the thickness to μm, α rays are attenuated, thereby eliminating soft errors. (JP-A-5-23500
0) That is, the flight distance of α rays is several cm in air, several μm in metal materials, and 0 in insulating resins such as polyimide.
It is 1 to 0.7 μm. Therefore, the second insulating layer 8 is formed to a thickness of about 50 μm using a resin having a large attenuation of α rays such as polyimide, and the via 9 is formed of copper (Cu) having a large attenuation of α rays. This makes it possible to form the solder bump 11 directly on the transistor 14.

However, in order to realize the miniaturization of the semiconductor device, it is desirable that the second insulating layer 8 is not so thick and that the α ray can be cut.

[0012]

A solder bump is used in a semiconductor device having a flip chip structure.
Α rays are radiated from the solder bumps, which causes a soft error, so in order to prevent this, we have dealt with by providing the solder bumps away from the active region, but it is desirable from the viewpoint of high integration. Absent.

Therefore, recently, as shown in FIG. 3, a second layer has been provided on the wiring layer 7 for circuit-connecting each transistor.
There is proposed a method of forming a thick insulating layer 8 and forming a second via 9 so as to attenuate α-rays and eliminate a soft error.

However, forming the second insulating layer 8 as thick as about 50 μm significantly reduces the productivity of the second vias 9,
A decrease in yield is inevitable. Therefore, this measure is an issue.

[0015]

The above-mentioned problems are solved by the first via provided in the first insulating layer directly above each transistor and the second via provided in the second insulating layer directly below the solder bump. The problem can be solved by configuring the semiconductor device, which is characterized in that the vias and the vias are formed with their positions displaced from each other.

[0016]

According to the present invention, the solder bumps are provided so as to be bent from the transistor formation region, thereby increasing the distance between the solder bumps and the transistor and attenuating and absorbing the α ray.

As described above, the flight distance of α rays is several μm in a metal material, but attenuates by 0.1 to 0.7 μm in a resin such as polyimide. Therefore, the second insulating layer may be formed of an organic insulating material, but since the via needs to be formed of a metal having good conductivity, at least 10 μm is required.
A via having a length of m or more is required, and it is almost impossible to form a via by filling a metal hole by a sputtering method or a vacuum evaporation method.

Therefore, according to the present invention, as shown in FIG. 1 (A), the first via and the second insulating layer 8 formed in the first insulating layer 6 are formed.
The second via 9 to be formed on the first insulating layer is misaligned, the wiring layer 7 formed on the first insulating layer increases the distance, and the length is set to 10 μm or more, so that the obstacle due to the α ray is prevented. It is something to lose.

In this way, the first insulating layer 6 and the second insulating layer 6
The length of the via formed in the insulating layer 8 may be the same as the conventional one,
Therefore, a decrease in manufacturing yield can be eliminated. In the present invention, the solder bumps 11 are formed at the central positions of the four transistors 14 formed in a matrix as shown in FIG. 7B, or as shown in FIG. A conductor which is located at a position shifted by a half pitch in the vertical direction and has a pattern formed in the wiring layer 7 by providing vias for the emitter, base and collector in the first insulating layer 6 directly above each transistor 14. The circuit is connected to the line, and then the solder bump 11 is connected to the circuit through the via 9 provided at a position deviated from the line. By adopting such a method, it is possible to prevent an obstacle due to the α ray.

In order to prevent the soft error due to α rays, the distance between the solder bump 11 and the transistor 14 may be increased. In the present invention, the pad 10 is made of nickel (Ni).
) A soft error due to α-rays is suppressed by forming it with a bonding layer of a film and a metal film with a small α-ray radiation amount and increasing the thickness of the metal film with a small α-ray radiation amount.

That is, the thickness of the second insulating layer 8 is made thick as a method of increasing the distance between the solder bump 11 and the transistor 14 in the related art, but in the present invention, by making the pad 10 thick, The soft error due to α rays is suppressed without lowering the manufacturing yield. Here, the pad 10 is generally formed of a Ni film to prevent the solder constituting the solder bump 11 from diffusing into the via.
i is said to be a barrier metal because it has a remarkable diffusion blocking effect.

On the other hand, the α-ray radiation amount of metal (Count / hour.
cm ² ) is small in Ag, Cu and Ni as shown below. Ag, Cu, Ni ・ ・ ・ ・ ・ ・ ・ 0.005〜0.01 Count / hour ・ cm ² Sn 、 Sn-Ag 、 Au-Sn ・ ・ ・ ・ ・ ・ ・ 0.1〜1.0〃Sn-5% Pb・ ・ ・ ・ ・ ・ ・ 0.5 to 3.0 〃 Pb ・ ・ ・ ・ ・ ・ ・ ・ ・ 5.0 to 20.0 〃 Therefore, in the present invention, a Ni barrier film having a thickness of about 1000Å is formed by a sputtering method or a vacuum deposition method. Formed into
After forming a pad by photolithography (photolithography), Ag and C are formed on the pad by electroless plating.
u, Ni, a metal having a small amount of α-ray radiation is formed as a thick layer to form a bonding layer, and solder bumps are provided on the bonding layer. The first via and the second insulating layer are provided in the first insulating layer. The soft error due to α-rays can be reduced by forming the pad with a second via provided in the above-mentioned offset from each other, and forming the pad with a thick metal of a small α-ray radiation amount on the Ni film.

[0023]

【Example】

Example 1 (see FIG. 1B) After forming an n ⁺ buried layer at each transistor formation position on the p-Si substrate 1, an n type layer is epitaxially grown thereon, and then an ion implantation method is used. A p-type region is formed as a base region, and then, ion implantation is performed on the p-type region to form an n ⁺ region as an emitter region, and a collector region is formed by connecting with a buried layer by a diffusion method. Then, the transistors were patterned in a matrix.

Next, the thickness of 5000 Å is reduced to S by the sputtering method.
An iO ₂ layer is formed to form the first insulating layer 6, and holes for emitter, base and collector are formed right above the transistor by a photo-etching technique (photolithography) using RIE (reactive ion etching). After that, Cu is vacuum-deposited and the hole is filled to form the first via.
The film was selectively etched to pattern the wiring layer 7.

Next, a photosensitive polyimide precursor varnish was spin-coated on this so that the thickness after pre-baking would be 1 μm, heated at 90 ° C. for 1 hour to dry the solvent, and then subjected to ultraviolet mask exposure. The intermediate position of the four transistors is exposed to light, ultrasonic development is performed using N-methyl-2-pyrrolidone, rinsed with ethyl alcohol, and then heated at 350 ° C. for 30 minutes to perform imidization. Then, the second insulating layer 8 having a hole for forming a via was formed.

Next, Cu is vapor-deposited on this to fill the hole, and then selective etching is performed to form a second via 9. Next, an Au film is formed on the second insulating layer 8. After the Ni film and the Ni film were formed to a thickness of about 1000Å, a pattern was formed using a photo-etching technique to form a pad 10, and a solder bump 11 was formed thereon by a transfer method.

By adopting such a method, the solder bump 11 can be separated from the transistor 14 by a via distance of 100 μm or more, whereby the soft error of α ray can be reduced. Example 2: (see FIG. 1C) After forming transistors in a matrix on the p-Si substrate 1 in the same manner as in Example 1, the first insulating layer 6 was formed.
Is formed by using a SiO ₂ layer, and holes for emitters, bases, and collectors are formed right above each transistor 14, and then Cu is vacuum-deposited to fill the holes to form a first via. , Cu film was selectively etched to pattern the wiring layer 7.

Next, after similarly forming a second insulating layer 8 made of polyimide, a hole for forming a via is formed at an intermediate position of the transistor 14 in the vertical direction, and Cu is vapor-deposited on the hole to fill the hole. After that, selective etching is performed to form a second via 9, and then an Au film and a Ni film are formed on the via 9 by about 10 times.
After forming the film to a thickness of 00Å, a pattern was formed using a photo-etching technique to form a pad 10, and a solder bump 11 was formed on the pad 10 by a transfer method. By adopting such a method, the solder bump 11 can be separated from the transistor 14 by a via distance of 100 μm or more, which can reduce the soft error of α ray. Example 3: Five glass substrates were each spin-coated with a polyamic acid solution and solvent-dried, and then 450 ° C.
After curing for 3 hours, a polyimide film having a thickness of about 5 μm was formed to obtain a substrate. A SiO ₂ layer having a thickness of 5000 Å is formed on this by a sputtering method to form a first insulating layer, and RIE is performed.
After making a hole having a diameter of 10 μm by Cu, Cu was vacuum-deposited to fill the hole to form a first via, and the Cu film was selectively etched to form a wiring layer pattern.

Next, a layer of 5000 is again formed on the layer by the sputtering method.
A SiO ₂ layer is formed to a thickness of Å to form a second insulating layer, and the diameter is 10μ by RIE at a position offset by 50μm from the first via.
After making m 2 holes, Cu was vapor-deposited to fill the holes, and then selective etching was performed to form the second vias. Then, a Ni film was formed on the second insulating layer by sputtering to a thickness of about 1000 Å, and selective etching was performed to form a pad pattern.

Next, electroless plating of Ag, Cu and Ni was performed on the pads of 5 of the 5 glass substrates to a thickness of 5 μm, and 2 of the 5 glass substrates were used as before. Similarly, after Au was sputtered to a thickness of 1000Å, selective etching was performed to form a pad made of a bonding layer.

Then, after forming solder bumps on this pad by a transfer method, the polyimide layer on the glass substrate is dissolved by using hydrazine to expose the first via of the first insulating layer, The α dose emitted from the solder bump was measured using a Si semiconductor detector. as a result,
About 0.5 Count / hour ・ cm ² was measured for the sample in which the bonding layer of the pad was formed of 1000 Å Au film,
With respect to the samples on which the electroless plated films of g, Cu and Ni were formed, all were 0.1 <Count / hour · cm ² .

[0032]

By implementing the present invention, the effective distance to reach the solder bump from the transistor can be extended by a method that is almost the same as the conventional semiconductor device forming process, thereby reducing the manufacturing yield of via formation. Therefore, it is possible to eliminate the α-ray soft error.

[Brief description of drawings]

FIG. 1 is a partial sectional structure (A) and plan views (B) and (C) of a semiconductor device embodying the present invention.

FIG. 2 is a partial cross-sectional structure (A) and a plan view (B) of a flip-chip type semiconductor device.

FIG. 3 is a cross-sectional structure of a conventional semiconductor device having a soft error countermeasure.

[Explanation of symbols]

 1 p- Si Substrate 3 n- Si Layer 6 First Insulating Layer 7 Wiring Layer 8 Second Insulating Layer 9 Second Via 11 Solder Bump 14 Transistor

Claims (5)

[Claims] 1. A first insulating layer (6), a wiring layer (7), and a second insulating layer (8) on a semiconductor substrate (1) on which a plurality of transistors (14) are patterned in a matrix. Solder bumps (11) and circuits in which the transistors (14) are formed on the second insulating layer (8) by forming a layer and forming vias in the first and second insulating layers (6, 8). In the connected semiconductor device, the first via provided in the first insulating layer (6) above each transistor (14) and the second insulating layer (8) below the solder bump (11). A semiconductor device characterized in that the second vias (9) provided in (1) and (2) are misaligned and patterned. 2. Four transistors (14) in which the first vias are directly above a transistor (14) formed in a semiconductor substrate and the second vias (9) are arranged in a matrix. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed at a center position of (1). 3. The first via is directly above the transistor (14) formed in the semiconductor substrate, and the second via (9).
2. The semiconductor device according to claim 1, wherein the transistors are formed by being shifted by a half pitch in the vertical direction from the transistors (14) arranged in a matrix. 4. A pad (10) for mounting a solder bump (11) on a second via (9) provided in the second insulating layer (8) is formed by a nickel film and a plating method. The semiconductor device according to claim 1, wherein the semiconductor device comprises a bonding layer with a metal film having a small amount of α-ray radiation. 5. The metal film having a small α-ray radiation amount is silver,
The semiconductor device according to claim 4, wherein the semiconductor device is formed of at least one of copper and nickel.