JPH0879254A - Signal system selection and output device - Google Patents

Abstract

PURPOSE: To shorten delay at the normal time and to perform switching without interruption. CONSTITUTION: Detection parts 104 and 105 detect user cells and supply detection signals to a control part 109. A selector 106 selects the signals of a system whose phase is leading among '0' and '1' system signals by the system selection signals of the control part 109 and outputs them to a buffer 108 and the selector 107 selects the signals of the system of phase lag among the '0' and '1' system signals by the system selection signals of the control part 109 and outputs them to a comparison part 110. The buffer 108 records the signals of the system of phase leading selected in the selector 106 and read control is performed by the control part 109. The comparison part 110 compares output signals from the buffer 108 with the output signals from the selector 107 by a cell unit and supplies a result to the control part 109. A generation part 111 generates free cells and supplies them to the selector 112 and the selector 112 selects the signals to be outputted as an active system among input signals P1 to P4 by selection signals from the control part 109 and outputs them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal system selection output device, for example, B (Broad band).
-ATM (Asyncro), which is an elemental technology of ISDN
The present invention can be applied to the switching of a transmission path or a path (virtual path VP) without interruption in a transmission / switching device or the like according to the nose transfer mode (asynchronous transfer mode).

[0002]

2. Description of the Related Art In recent years, various technical developments have been carried out in order to realize ATM communication in B-ISDN. For example, as a technique for switching the signal system without interruption, it is disclosed in the following documents.

Reference 1: IEICE Technical Report,
In 1992, VOL. 92, NO. 287, CS
92-48, "Instantaneous Transmission Line Switching Method in ATM Network".

Reference 2: Proceedings of the 1992 Autumn Conference of the Institute of Electronics, Information and Communication Engineers, Volume 3, B-526, page 3-19
2, "A study of the non-instantaneous double switching method in ATM transmission equipment".

"Outline without interruption": In a communication network, a transmission device is required to have high reliability.
Conventionally, the main signal system has been duplicated in the transmission path and in the main part of the device to increase the reliability by taking a redundant configuration.

Since there are two systems of signals in the latter stage of the duplexed portion, either system must be selected. For this reason, a transmission path selection switching circuit is incorporated in the input section at the latter stage.

Normally, when one of the systems is selected, it is sufficient to continue selecting the system as it is, but it is necessary to switch to the other system due to the wiring work of the transmission line or the maintenance of the device. There are things that must be done.

In this case, since the transmission path is in operation (the user is actually communicating), it is desirable to switch without interruption.

Here, "no interruption" means that there is no loss of signals, the order is guaranteed, and the signals do not overlap. In the ATM transmission system in which signals are transmitted in packets called fixed-length cells. Means that loss / reversal of cell order and double feeding of cells do not occur.

Regarding the configuration of such a switching system,
It is described in Section 2.1 of Page 2 of Document 1 mentioned above.
Further, the purpose of making the transmission path switching non-interruptive is described in the above-mentioned Document 1, pages 2 to 3, item 3.

"Instantaneous-interruption switching method": Three methods have been proposed as the method for instantaneous-interruption switching in the ATM transmission system, as shown in the above-mentioned document 1, pages 3 to 4, item 4. There is. Among them, the cell sequence synchronization method of Method 3 (this method will be referred to as a constant synchronization method in the following) depends on the difference in the delay insertion method for establishing synchronization.
Two methods, a batch insertion method and a sequential insertion method as described in the above-mentioned document 2, have been proposed.

The sequential insertion method has an advantage over the batch insertion method in that the synchronization state can be maintained even when the cell flow of the active system and the cell flow of the standby system differ due to the insertion of empty cells. Further, in the constant synchronization method, the phase difference between the two systems is always absorbed, so that there is an advantage that the time from when a switching instruction is issued to when the systems are actually switched is short.

[0013]

In the above-described sequential insertion method, even when an empty cell is inserted and the cell flow of the active system and the cell flow of the standby system are different, the system is switched without interruption while maintaining the synchronization of both systems. It was possible.

(A) However, in the above-described constant synchronization method, when the phase of the active system is advanced, a semi-fixed delay is inserted in the active system after the synchronization is established. In other words, although the length of the transmission path of the working system is shorter than the length of the transmission path of the standby system, no delay is added originally, and communication can be performed only with the delay of the transmission path length. Since the synchronization method is always used and the delay is added, the same delay as that in the case of selecting the backup system with a long transmission path length occurs.

From the viewpoint of the entire network, the same large delay as in the case where the long transmission line system is selected occurs in the duplicated section of all transmission lines.

(B) Further, in the above-mentioned document 2, cell delay fluctuation (CDV: Cell Delay) at the time of switching.
It is stated that the constant synchronization method is effective because no variation occurs. However, since cell delay fluctuations occur when synchronization is pulled in, frequent switching between the active system and the standby system is performed while maintaining synchronization. If such an operation is not required, it is not particularly advantageous compared to the problem that the absolute delay of the entire network becomes large.

Therefore, the cell delay fluctuation CDV for adjusting the phase difference is generated at the time of switching by utilizing the feature of ATM that allows the cell delay fluctuation CDV to some extent. And the absolute delay of the entire network is reduced by only causing the transmission delay due to the pure working transmission path length.

At the same time, by inserting an empty cell of the always synchronous system, the synchronous state can be maintained even when the cell flows of the active system and the standby system are different from each other until the system is actually switched after the switching instruction is issued. Virtually always synchronizes (absorption of phase difference) so that the advantage of short time is not impaired, and it is possible to switch immediately when switching is requested. It is desired to be able to switch.

Furthermore, there is a possibility that cells other than the vacant cell may be inserted at different positions in the 0-system cell flow and the 1-system cell flow.
peration administration a
ndMaintenance (maintenance operation) Even if a cell / resource management cell or the like is inserted in the cell flow, it is desired that the virtual always-synchronizing unit can maintain the synchronization state during the normal operation.

From the above, a signal system selection output device which has a simple structure and which can shorten the delay time of the selection output of the active system during normal operation other than switching and can perform switching without interruption. Offer is requested.

[0021]

In view of the above, the present invention provides a signal system selecting and outputting apparatus which receives at least two or more signal systems and selectively outputs any one of the input signal systems as an output of the working system. The above-mentioned problems are solved by a typical configuration.

That is, a user packet detecting means for detecting a user packet from each input signal system, a delay means for delaying an input signal system whose phase is ahead of other input signal systems, and the undelayed input. The coincidence comparison means for performing coincidence comparison between the user packet of the signal system and the user packet of the input signal system delayed by the delay means, and the phase of the packet of the input signal system whose phase is advanced from the result of the coincidence comparison means. A delay amount control means for controlling a delay amount to be delayed.

Further, at least two systems or more are provided, the matching means for searching the matching packet by the matching and comparing means, the synchronizing means for constantly synchronizing the phase difference after the search, and the empty packet generating means for generating and outputting the empty packet. Each input signal system, input signal system delayed by the delay means,
Signal selection means for selectively outputting the active system output from any one of the empty packet signal systems generated by the empty packet generation means.

[0024]

According to the present invention, no delay is inserted in the active system during normal operation without switching,
It is possible to reduce the delay in the entire network. Further, even if the packet flow between the active system and the non-active system differs due to the insertion of the non-user packet, it is possible to maintain the synchronization state, and shorten the time from when the switching request is given until the actual switching. be able to.

The delay is inserted only at the time of switching. In other words, during normal operation, no delay is inserted in the active system to maintain synchronization with other systems, and if the phase of the active system is ahead of other signal systems, only the transmission delay for the transmission path length Can be passed through the signal selection means.

Therefore, unlike the constant synchronization method, the delay amount of the phase difference of each signal system is not always added, and the delay amount of the entire network can be reduced.

Further, since it is possible to virtually absorb the phase difference by the constant synchronization method, a packet inserted at a different position other than the empty packet during the period other than the switching time while obtaining the effect of the constant synchronization method. Keep in sync even if there is
It is also possible to switch without interruption.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described with reference to the drawings. Therefore, in this embodiment, in the transmission by the ATM transmission method, which is the elemental technology of B-ISDN, the switching device, etc., the switching of the transmission path or the virtual path (VP) is performed without interruption, and the virtual synchronization type is without interruption. The configuration is such that disconnection switching can be realized.

FIG. 1 is a functional block diagram of the hitless switching device. In FIG. 1, the hitless switching device includes a 0-system input terminal 101, a 1-system input terminal 102, and a switching signal 103.
, User cell detection units 104 and 105, and selector 10
6, 107, buffer 108, control unit 109, match comparison unit 110, empty cell generation unit 111, and selector 1
12 and an active system output terminal 113.

In FIG. 1, the signal input from the 0-system input terminal 101 is the input port P1 of the selector 112.
And to the input port 0 of the user cell detection unit 104, the selector 106, and the selector 107, respectively.

The signal inputted from the 1-system input terminal 102 is given to the input port P4 of the selector 112 and also to the input port 1 of the user cell detection section 105, the selector 106 and the selector 107, respectively.

The user cell detection units 104 and 105 monitor the input signals of the 0th system and the 1st system, respectively, detect only the user cell, and control the user cell detection signal indicating that the input signal is the user cell. It is given to the section 109. Also,
Selector 106 inputs 0, 1 to input ports 0, 1
Among the system signals, a system signal whose phase is advanced (or is assumed to be advanced) is selected by a system selection signal from the control unit 109 to the S1 port and is output to the buffer 108.

Further, the selector 107 has input ports 0, 1
A system selection signal (a selection signal to be given to the selector 106) from the control unit 109 to the S2 port is selected from signals of the 0 and 1 system signals input to the system 1 whose phase is delayed (or is assumed to be delayed). It is inverted.) And outputs it to the match comparison unit 110. Therefore, selectors 106 and 10
Signals of 7 are not selected simultaneously in the same system.

Furthermore, the buffer 108 is the selector 1
The signal of the system in which the selected phase is advanced (or is assumed to be advanced) is recorded in 06, and the read control is performed by the control unit 109. The signal read by the buffer 108 is given to the selector 112 and the match comparing section 110 in the same manner.

Further, in the match comparison unit 110, the buffer 1
The signal output from 08 and the signal output from the selector 107 are compared on a cell-by-cell basis, and a match / mismatch result is given to the control unit 109. Furthermore, the empty cell generation unit 1
At 11, an empty cell is generated and given to the input port P3 of the selector 112.

Furthermore, in the selector 112, the control unit 10
P1 to P depending on the selection signal from S9 to S3 port
Among the input signals up to 4, the signal output as the active system is selected and output to the active system output terminal 113. Further, the control unit 109 includes the user cell detection units 104 and 10
5 and input signals from the coincidence comparison unit 110, system selection of the selectors 106 and 107 and buffer read control are performed, and the selector 112 is controlled according to a switching request from the switching signal terminal 103.

(User cell detectors 104, 105):
The user cell detection units 104 and 105 are 0 system,
The input signal of 1 system is constantly monitored, and empty cells, OAM cells,
A user cell detection signal indicating that only the cell is detected and the input signal is a user cell, excluding cells that may be inserted at different positions in the 0-system and 1-system cell flows such as resource management cells. Is output.

(Selectors 106, 107): The selectors 106, 107 are 2-input 1-output selectors, and are instructed by the control unit 109 from the signals of 0 system and 1 system input to the input ports 0, 1. Select and output the system signal. The selector 106 and the selector 107 always select different systems and do not simultaneously output the same system.

(Buffer 108): Buffer 108
Then, all the cells of the system selected by the selector 106 are recorded including the empty cell, the OAM cell, the resource management cell, etc., and based on the control of the control unit 109, the cell reading, the reading stop, and the reading skip are performed. It is a thing.

(Match comparison unit 110): Match comparison unit 1
In 10, the cell read from the buffer 108 is compared with the cell of the system selected by the selector 107, and a signal indicating match / mismatch is output as the comparison result.

At this time, it is determined whether or not they match.
(A) Compare all bits, and if all match,
(A) All bits are compared, and when there is a match over a preset number, (c) The bits to be compared are limited and when all of them match, etc. The method of can also be applied.

(Empty Cell Generation Unit 111): The empty cell generation unit 111 always generates an empty cell and outputs it to the selector 112.

(Selector 112): Selector 112
Is a 4-input / 1-output selector, which determines which of the input ports P1 to P4 is selected according to an instruction from the control unit 109, and outputs a signal input to the selected port. .

(Control unit 110): In the control unit 110, the control system for virtually synchronizing the cell phase at all times (without performing any processing on the active system in operation) and the active system by the switching instruction. System switching control from the standby system to the standby system. The non-instantaneous interruption switching method of this embodiment will be described in detail below, including the virtual constant cell phase synchronization method and switching flow.

"Virtual Always Cell Phase Synchronization Method and Switching Flow": (Outline) During normal network operation, the input signal of the active system is directly output as it is, while at the same time virtually the active system and the standby system are constantly operated. Keep it in sync,
Absorb the phase difference between both systems. Virtually, when the synchronous state is always maintained, the system can be switched without interruption.

In order to create a virtual constant synchronization state, start from the search for the phase difference between both systems, and perform the phase difference search / synchronization confirmation /
Synchronization can be maintained by transitioning between three modes such as synchronization monitoring. The constant synchronization state refers to the time of being in the synchronization monitoring mode among the above three modes.

(Phase synchronization establishment method): FIG. 2 is an explanatory diagram showing state transitions of the above-mentioned three modes. The initial state is the phase difference search mode S1, and the phase difference is searched while comparing cells of both systems, and if even one cell is found, the mode shifts to the synchronization confirmation mode S2.

Further, in the synchronization confirmation mode S2, it is confirmed whether or not the synchronization is really established after the cell matched in the phase difference search mode S1, and the mode is returned to the phase difference search mode when M cells do not continuously match, and L cells are continuously connected. Upon coincidence, the synchronous monitoring mode S3 is entered.

Furthermore, in the synchronization monitoring mode S3, after the establishment of the synchronization is confirmed by the synchronization confirmation mode S2, it is monitored whether or not the synchronization is lost. here,
When the N cells do not continuously match, the synchronization is considered to be lost, and the initial phase difference search mode S1 is returned to.

Here, each value of L, M, and N is an integer value of 1 or more, and is required for the difference in the judgment method of the coincidence comparison in the above description of operation, the characteristics of the communication path, and the device. It is preferable to set an appropriate value depending on the reliability and the like.

The detailed operation flow in each mode will be described below with reference to FIG.

((Phase difference search mode)): FIG. 3 is an operation flow of the phase difference search mode. In FIG. 3, first, in the phase difference search mode (S100), the contents of the buffer 108 are cleared (S101). At the initial setting stage, it is not possible to determine which phase of the system is advanced. Therefore, it is assumed that the phase of the 0 system is advanced and the search is started.

In the buffer 108, of the 0-system cells selected by the selector 106, the writing of the user cell that has passed first is started at the beginning, and the leading user cell is read out (S102). In the operation of the buffer 108 in the phase difference search mode, input cells are sequentially written, and reading is performed only for the first recorded (stored) (leading) cell. Hereinafter, this is called "buffer continuous reading".

Next, the 0-system user cell read by the buffer continuous read and the 1-system cell selected by the selector 107 are compared in cell units (S103). If a match is detected in the cell match comparison in S103,
The process shifts to the synchronization confirmation mode (S109). Also, this S
When a mismatch is detected in the cell match comparison of 103, it is confirmed whether or not the buffer 108 is full (FULL) (S104), and when it is not full, S102 continues with the assumption that the 0 system is advanced. Return to read.

If it is full, the system which is assumed to have the advanced phase is changed to the one system and the phase difference search is continued.
This phase difference search method is exactly the same as that executed on the assumption that the 0-system phase is advanced. That is, first, the contents of the buffer 108 are cleared (S105), and the selector 10
Of the 1-system cells selected in 6, writing is started with the first passed user cell at the beginning, and the first user cell is read out (S106).

Next, the 1-system user cells read by the buffer continuous reading and the 0-system cells selected by the selector 107 are compared in cell units (S107). When a match is detected in S107, the process shifts to the synchronization confirmation mode (S109). If a mismatch is detected in S107, it is confirmed whether or not the buffer 108 is full (S108). If not, the process returns to S106 with the assumption that the 1st system is advanced. On the other hand, if it is full, the system that is assumed to have advanced phase is changed to the 0 system again, and the process returns to the buffer clear in S101.

After that, the above operation is repeated until a matching cell appears.

((Synchronization Confirmation Mode)): FIG. 4 is an operation flowchart of synchronization confirmation in one embodiment. This Figure 4
In the synchronization confirmation mode (S109), first, it is determined whether or not the cell to be next selected / output in the selector 107 is the user cell, based on the information from the user cell detection unit 104 or 105 (S110).

When it is determined in S110 that the cell is not the user cell, the reading of the buffer 108 is stopped (S111). As a result, even if fluctuation occurs due to an empty cell or the like in the system in which the phase is delayed, the user cell to be compared is not lost.

Next, after stopping the reading of the buffer, it is judged whether or not the next cell to be read from the buffer 108 is the user cell (S112). If it is determined that the cell is a user cell, the process directly returns to the determination in S110. If the cell is not the user cell, the cell is skipped (S113). Further, the process returns to the determination of S112 to determine whether or not the next cell is the user cell. As a result, the user cell to be compared is not lost even when fluctuation occurs due to an empty cell or the like in the system in which the phase is opposite to the preceding one.

In addition, in the determination of S110, even if the next cell to be selected / output is a user cell, or if fluctuation occurs due to an empty cell or the like in the system with advanced phase, the user cell to be compared. In order not to lose sight of it, it is determined whether or not the next cell read from the buffer 108 is a user cell (S114). If it is not the user cell, the cell is skipped (S115). If it is a user cell, the cells are sequentially read (S116). This will be referred to as "buffer sequential read" as opposed to buffer continuous read.

The user cells read by the "buffer sequential read" are compared with the user cells selectively output from the selector 107 in cell units (S117). As a result, if there is a mismatch, it is determined whether or not the mismatch has occurred consecutively in M cells (S11).
8). Here, when it is less than M cells, the process returns to the determination of S110 to compare the next user cell, and when it is M cells, it is determined that the phase synchronization cannot be drawn, and the process returns to the phase difference search mode (S100). This is repeated from the phase difference search.

If a match is detected in the cell match comparison in S117, it is determined whether the match has occurred continuously in L cells (S119). Here, when the number of cells is less than L cells, the process returns to the determination of S110 to compare the next user cell, and when the number of cells is L, it is assumed that the phase can be pulled into the synchronization state, and the synchronization monitoring mode (S1
The process is transferred to 20).

((Synchronous monitoring mode)): FIG. 5 is an operation flowchart of the synchronous monitoring mode of one embodiment. In FIG. 5, in the synchronous monitoring mode (S120), the flow is almost the same as in the synchronous confirmation mode, and S121 to S129 of the synchronous monitoring flow correspond to S110 to S118 of the synchronous confirmation flow, respectively, and perform exactly the same processing. It is something to do. The difference between the two modes is that the L-cell consecutive match detection unit for determining the synchronization establishment in S119 in the synchronization confirmation flow is not in the synchronization monitoring mode, and the cell match comparison unit S12
If they coincide with each other in 8, it is considered that the synchronization is maintained, and the characteristic is that the operation immediately shifts to the comparison operation of the next user cell.

(Example of establishing phase synchronization): FIG. 7 uses the phase synchronization establishing method described above, and actually uses 0 system and 1 system.
It shows an example in the case of operating assuming a signal input to the system.

In FIG. 7, the vertical direction represents time t, and the horizontal direction represents the state at that time t. Therefore, the meaning of each element is as follows. 0-system input: input cell from 0-system input terminal 101 at time t 1-system input: input cell from 1-system input terminal 102 at time t Buffer memory content: of cell stored in buffer 108 Content P1 ... Input cell to input port P1 of selector 112 P2 ... Input cell to input port P2 of selector 112 P3 ... Input cell to input port P3 of selector 112 P4 ... To input port P4 of selector 112 Input cell Working output ... Output cell of selector 112.

In the example of FIG. 7, the phase of the input cell of the 1-system is advanced and the active system is the 0-system. Furthermore, in order to distinguish 0-system cells and 1-system cells, cells having the same content are represented by capital letters for 0-system cells and lowercase letters for 1-system cells.

First, the phase difference search mode is started. In this phase difference search mode, the search is started on the assumption that the 0-system is advanced, but the buffer is full (FULL).
Since the same cell cannot be detected even if the coincidence comparison is performed until, the search is started again by assuming that the 1st system is advanced (S105 and later).

Next, at "time t = 0" in FIG. 7, the 0-system input cell is Y, the 1-system input cell is a, and the 1-system cell a, which is assumed to be advanced, is written in the buffer 108. At the same time, the data is read by the buffer continuous reading (S106). Here, the cell match comparison target is
The cell a (= input cell to P2) read from the buffer 108 and the output of the selector 107 (delayed system, that is, input of 0 system = input to P1) cell Y do not match, so the following Wait for input. In this case, the 0-system cell Y (= P) is used as the active system output (output of the selector 112).
(Input cell to 1) is output.

Next, at "time t = 1", the 0-system input is an empty cell, the 1-system input is an empty cell, the 1-system empty cell is written in the buffer 108, and at the time of t = 0 by the buffer continuous read. The written cell a is read (S106). Here, the cell match comparison target is the cell a (= input cell to P2) and the selector 1
Since it is an empty cell of the output of 07 and does not match, it waits for the next input. In addition, as an output of this working system, an empty cell of system 0 (=
The input cell to P1) is output.

Next, at "time t = 2", the 0-system input is the cell Z, the 1-system input is the cell b, the 1-system cell b is written in the buffer 108, and the buffer continuous reading is performed at t = 0. The written cell a is read (S106). Here, the cell match comparison target is the cell a (= input cell to P2) and the selector 1
It is the cell Z of the output of 07, and since it does not match, it waits for the next input. In this case, the 0-system cell Z (= input cell to P1) is output as the active system output.

Next, at "time t = 3" in FIG. 7, the 0-system input is an empty cell and the 1-system input is an empty cell, and the same processing as when t = 1 is performed. Therefore, since an empty cell is written in the buffer 108 and there is no match in the match comparison,
It outputs an empty cell of system 0 as an active system output and waits for the next input.

Next, at "time t = 4", the 0-system input is the cell A, the 1-system input is an empty cell, the 1-system empty cell is written in the buffer 108, and the buffer continuous reading is performed at t = 0. The written cell a is read (S106). Here, the cell match comparison target is the cell a (= input cell to P2) and the selector 1
Since it is the cell A having the output of 07 and coincides, the cell A of the 0 system (= input cell to P1) is output as the current system output, and the mode is shifted to the synchronization confirmation mode.

Next, at "time t = 5", the active system input is an empty cell, the standby system input is a cell c, and the system 1 cell c is written in the buffer 108 and the selector 107
Output (= 0 system input) is an empty cell (S10
7) The reading of the buffer is stopped, and since the cell to be read from the buffer is an empty cell (S112), the empty cell is skipped (S113) and the next input is awaited.

As a result of this operation, cell b becomes the head of the buffer. Also in this case, a 0-system empty cell (= input cell to P1) is output as the active system output.

Next, at "time t = 6", the 0-system input is the cell B, the 1-system input is an empty cell, the 1-system empty cell is written in the buffer 108, and the output of the selector is also the read cell of the buffer. Since both are user cells (S11
0, S114), the 1-system cell b is read by the buffer sequential read, and the 0-system cell B is coincident with and compared. here,
Although the comparison result shows a match, it does not mean that the match has occurred L times consecutively, and therefore the system waits for the next input.

Next, "after time t = 7", t = 5 and t =
The processing performed in 6 is repeated, and if the result of the match comparison is L times consecutive matches, the mode shifts to the synchronous monitoring mode. Further, when the disagreement is detected M times consecutively, the process is performed again from the phase difference search mode.

(Switching Flow): FIG. 6 is a flowchart of the switching operation of the embodiment. In FIG. 6, a switching request (S20
When 0) is given, it is first confirmed whether or not the mode is the synchronous monitoring mode capable of switching without interruption (S201).

If the synchronous monitoring mode is not set, the process waits until the synchronous monitoring mode is entered (phase synchronization is established) until a predetermined time.
201 is repeated (S202). If the synchronization monitoring mode is not entered even after waiting for the specified time, it is determined that phase synchronization cannot be achieved (cannot be achieved), and the system is forcibly switched from the active system to the standby system (S203). At this time, the selector 112 switches the input selection from the port P1 to the port P4 when the active system is the 0 system. When the active system is the 1 system, the input selection is switched from the port P4 to the port P1. Of course, at this time, there is no instantaneous interruption switching.

If it is determined in the synchronous monitoring mode in S201 that it is in the synchronous monitoring mode, it is next confirmed whether the phase of the active system is advanced or the phase of the standby system is advanced (S205). Here, when the phase of the active system is advanced, the cell stored in the buffer 108 is the active system cell, and the output to the active system output terminal 113 has already been completed. A cell that has not yet appeared in the input.

If the system is switched to the standby system as it is, the cells having the same contents are output in duplicate. Therefore, the already output cells, that is, the same contents as the cells stored in the buffer at the time of the switching request. The switching can be performed only after all the cells of have appeared in the input of the standby system.

Therefore, until all the cells having the same contents as the cells stored in the buffer appear in the spare input,
Insert an empty cell to adjust the timing (S20
6). At this time, the selector 112 uses the active input port (port P1 for 0 system, port P4 for 1 system).
To port P3 which is an input from the empty cell generation unit 111.

Thereafter, the synchronous monitoring (cell coincidence comparison) is continued to compare the input cell of the spare system and the buffer output (S207), and all the cells stored in the buffer at the time of the switching request appear in the input of the spare system. To wait for (S208). Until all appear, the process returns to S207 and the synchronization monitoring is continued.

Therefore, when all cells have appeared, the insertion of empty cells is stopped and the system is switched to the standby system (S209).
That is, the selector 112 switches from the input port P3 to the standby system input port (port P4 when the active system is the 0 system, and port P1 when the active system is the 1 system). This completes the non-instantaneous interruption switching (S214).

If it is determined in S205 that the active system is not advanced, that is, the phase of the standby system is advanced, the cell stored in the buffer 108 is the standby cell and is in the synchronous monitoring mode. That means,
This indicates that the synchronization between the input of the active system and the buffer output is established. Therefore, in this case, if there is a switching request, it is possible to immediately switch from the active system to the buffer output (S210). However, the switching timing is when both the output of the buffer 108 and the output of the selector 107 are user cells, and the operation in the synchronous monitoring mode is maintained until then.

At this time, the selector 112 switches from the active system input port (port P1 when the active system is the 0 system, port P4 when the active system is the 1 system) to the port P2 which is the input port from the buffer 108. is there.

It should be noted that if the buffer output is simply switched here, a delay corresponding to the number of cells stored in the buffer is added to the backup system. Therefore, this delay is actually gradually reduced to the final value. Specifically, it is necessary to change to the standby system input port P1 or P4 to which no delay is added. This reduction of delay is performed by discarding empty cells. However, if the empty cells are discarded unplanned, it is considered that the cell interval of the user is sharply shortened (the speed of the user cell is increased). Usage Parametermeter C
control: A function to monitor the speed of the user cell according to the value declared by the user (average speed, peak speed, etc.)
May cause user cells to be discarded in the network.

Therefore, in consideration of the effect on UPC, empty cells are discarded once for x cells, and the delay is gradually reduced so that the interval is not sharply shortened (S211). However, there is not always an empty cell for each x cell, so 1
After discarding one empty cell, wait for x cells to pass, and then discard the empty cell that appears for the first time. Where x
The value of is preferably set to a value that reduces the influence on UPC as described above.

In this way, the delay is gradually reduced, and it is confirmed whether or not the buffer has become empty (whether or not the delay has been reduced) (S212), and if not, S
Returning to the empty cell discard of 211, the delay is further reduced, and when it becomes empty, the backup system is selected (S213). At this time, the selector 112 switches from the input port P2 to the standby system input port (port P4 when the active system is the 0 system, and port P1 when the active system is the 1 system). This completes the non-instantaneous interruption switching (S214).

(Example of Switching Operation): FIG. 8 is an explanatory diagram of an example of the switching operation when the 0-system is the active system and the phase of the 1-system is advanced in one embodiment. The view of FIG. 8 is as described in the example of the phase synchronization establishment described above, but the item of switching request is increasing. The time indicated by 1 here is the time when the switching request is generated.

Further, it shows a state where the phase synchronization has already been taken, and further shows the operation when the value x of the empty cell discard in S211 of the switching flow is set to 2 for simplicity.

In FIG. 8, "time t = 0 to t =
3 ”is in the synchronous monitoring mode, the buffer 10
8 is in synchronization with the output of the selector 107, and the processing shown in the phase synchronization establishment example is performed. As the output of the active system at this time, the input of the active system 0 system (input to P1) is directly selected and output. However, since the switching request is generated at time t = 3, the switching operation is performed from the next “time t = 4”.

At this "time t = 4", the synchronous monitoring mode is set (S201), and the phase of the active system 0 is delayed (S205). Therefore, the input port of the selector 112 is immediately output from the buffers P1 to P2. Can be changed to. However, at time t = 4, the selector 107
Is an empty cell, switching is not performed until a user cell appears in the output of the selector 107.

Further, the synchronization confirmation mode is continued until a user cell appears in the output of the selector 107. At this time, as an active system output, an empty cell of the active system 0 system is output.

Next, at "time t = 5", the selector 1
The 0-system input cell, which is the output of 07, is cell B, which is a user cell. Further, since the head of the buffer memory is also the cell b which is the user cell, the operation of the synchronous monitoring mode is ended here, the read mode of the buffer is changed to the sequential read mode including the empty cell, and the Switch.

Actually, the selection of the input port of the selector 112 is changed from P1 to P2. As a result, as the active system output, the 1-system cell b stored in the buffer is selected and output. After that, in order to reduce the delay given by the buffer, a process of discarding (1 system) empty cells input to the buffer for each x (= 2) cells is performed.

Next, at "time t = 6", since the 1st system cell of the buffer input is an empty cell, it is not written in the buffer in order to discard the empty cell here. Since x = 2, the next empty cell discard timing is time t = 8.
Further, in the active system output at this time, since the read mode of the buffer is the sequential read mode including empty cells and the like, the empty cell stored next to the cell b is output.

Next, at "time t = 7", the 1-system cell of the buffer input is the cell d, which is written in the buffer, and at the same time, the empty cells are read by sequential reading and output as the active system output.

Next, at "time t = 8", the cell 1 of the buffer input is cell e, and although it is the empty cell discard timing, it cannot be discarded. Therefore, the cell e is written in the buffer, and the cell c is read by sequential reading and is output as the active system output. Discarding an empty cell is to wait until the next empty cell is input to the buffer.

Next, at "time t = 9", since the 1st cell of the buffer input is an empty cell, it is not written in the buffer in order to discard the empty cell here. Here, since discarding can be performed, the next empty cell discard timing is time t = 11.
Is. In addition, as the current system output at this time, the cells d sequentially read from the buffer are output.

Next, at "time t = 10", the cell 1 of the buffer input is the cell f, which is written in the buffer, and the cell e is read by sequential reading and output as the active output.

Next, at "time t = 11", the 1st cell of the buffer input is an empty cell, and it is the empty cell discard timing, so this empty cell is discarded without being written in the buffer. Since the cells are discarded here, only the cell f is stored in the buffer, and at the same time, the cells are read out as the current system output, so that the state becomes the buffer empty (Empty).

Therefore, at "time t = 12", the input port of the selector 112 is changed from P2 to P4 (S21).
3) The non-instantaneous interruption switching is completed by outputting the 1-system input cell g to the active system output (S214).

FIG. 9 is an explanatory view of an example of the switching operation when the 1-system of the embodiment is the active system and the phase of the 1-system is advanced. As in the case of FIG. 8, the view of FIG. 9 has an increasing number of items called switching requests. The time indicated by 1 here is the time when the switching request is generated. Further, like FIG. 8, it shows a state in which phase synchronization has already been taken, and further shows the operation when the value of x is set to 2 for simplicity.

First, since "time t = 0 to t = 3" is in the synchronization monitoring mode, the output of the buffer 108 and the output of the selector 107 are in synchronization with each other. I am performing such processing. At this time, as the output of the active system, the input of the active system 1 (input to P4) is directly selected and output. However, since a switching request is generated at time t = 3, the next time t
The switching operation is performed from = 4.

Then, at "time t = 4", the synchronous monitoring mode is set (S201), and the phase of the active system 1 is advanced (S205). Therefore, the input port of the selector 112 is immediately changed from P4 to P3. Change to the output of the empty cell generator and insert an empty cell as the active output. After that, the synchronization monitoring mode in which the comparison target cell is expanded to the valid cell is continued.

At time t = 3 when the switching request is issued,
Of the cells stored in the buffer, the last valid cell written is the cell b input at the time t = 3.
Therefore, empty cells are continuously inserted until a cell having the same contents as the cell b appears at the 0-system input (output of the selector 107) which is the backup system. Since the 0-system input at time t = 4 is an empty cell, it waits for the next input cell (S208).

Next, at "time t = 5", the 0-system input (output of the selector 107) is the cell B, which has the same content as the last valid cell b stored in the buffer at the time of the switching request. At this point, a cell that has already been output as the current system output has appeared in the standby system input (0 system input) (S208). Therefore, at time t = 5, the selector 112 still outputs an empty cell (port P3), but at the next cell input timing, that is, time t = 6.
Can be switched on.

Next, at "time t = 6", the switching operation is performed as described above. Then, in the selector 112, from the input (port P3) from the empty cell generation unit, the standby system (0
The selection is changed to the input (port P1) of the (system), and the empty cell of the system 0 is output to the active system output (S209). As a result, the non-instantaneous interruption switching is completed (S214), and thereafter, the 0 system is operated as the active system.

(Effect of One Embodiment): According to the hitless switching apparatus of the above one embodiment, during normal network operation, no delay is inserted in the active system to maintain the synchronization of both systems, and the active system is not inserted. If the transmission line of is shorter than the transmission line of the standby system, that is,
If the phase of the active system is ahead of the phase of the standby system,
The selector can be passed only by the transmission delay corresponding to the transmission path length.

Further, the selector has at least two or more respective input signal systems, a delayed input signal system, and an empty cell signal system generated by the empty cell generation unit 111 during the period other than the switching time. Among them, any one of the active system input signal system is selected and output as it is as the active system output signal system, and when the switching signal is given and the switching operation is started, the phase of the active system output signal system is advanced or delayed. Since either input signal system is selected and output depending on whether or not there is a request, it is possible to virtually constantly synchronize and immediately switch the output of the active system when a switching request is made.

Therefore, unlike the constant synchronization method, the delay of the phase difference between both systems is not always added, and the delay amount of the entire network can be reduced.

Further, virtually, the phase difference is absorbed by the constant synchronization method, so that the advantage of the constant synchronization method is not impaired, and the cell flow of both systems is not used during the period other than switching. Cells (OAM) inserted at different positions other than cells
Even if there is a cell / resource management cell, etc.), the synchronization can be maintained.

Since the device has a simple structure, the LS
It is also suitable for I-type, and can be made compact. Moreover, it is considered to be effective because there is no element that increases power consumption.

Therefore, it is considered to be very effective when applied to a transmission device or a switching device in an ATM communication system.

(Other Embodiments) (1) In the above-mentioned embodiment, although the input has two systems, a plurality of inputs are provided, one of which is the working system, and the other is the standby system. It is possible to deal with such a configuration. Also,
Although it has been described as the non-instantaneous interruption switching device, it can be generally applied as a signal system selection output device.

(2) Further, the present invention can be applied to the switching of the transmission line between the devices and the switching of the redundant configuration part in the device.
Further, it is applicable not only to the physical switching of the transmission path but also to the logical path (VP) switching.

(3) Further, in the above embodiment, the phase difference search is started on the assumption that the 0-system is advanced, but it may be started on the assumption that the 1-system is advanced.

(4) Furthermore, although a method using cells of the ATM transmission system has been described, fixed length packets,
The same applies to packet communication using variable-length packets.

(5) Also, the selectors 112, 106, 1
It is considered that it is preferable to implement 07 and the like with a gate circuit, a flip-flop circuit, a shift register circuit, a memory, a composite circuit thereof, or the like in terms of downsizing and low power consumption.

[0121]

As described above, the signal system selecting / outputting device of the present invention has the user packet detecting means for detecting a user packet from the input signal system and the input signal system having a phase advanced from other input signal systems. Delay means for delaying, the user packet of the input signal system which has not been delayed, the coincidence comparing means for performing coincidence comparison of the user packet of the input signal system delayed by the delay means, and the phase from the result of the coincidence comparing means. Delay amount control means for controlling the delay amount for delaying the phase of the packet of the input signal system that is advancing, and a synchronization means for always searching for a matching packet by the coincidence comparing means and maintaining a phase difference after the search. And an empty packet generating means for generating and outputting an empty packet,
At least two or more respective input signal systems, input signal systems delayed by the delay means, and empty packet signal systems generated by the empty packet generation means, and signal selection means for selectively outputting the active system output. Be prepared.

By adopting such a configuration, the delay time of the selection output of the active system can be shortened and switching can be performed without interruption during normal operation other than switching with a simple configuration.

Therefore, when the present invention is applied to a transmission device or a switching device in ATM communication, it is considered to be very effective.

[Brief description of drawings]

FIG. 1 is a functional configuration diagram of a hitless switching device according to an embodiment of the present invention.

FIG. 2 is a state transition diagram of phase synchronization establishment according to an embodiment.

FIG. 3 is a phase difference search flowchart of one embodiment.

FIG. 4 is a synchronization confirmation operation flowchart of one embodiment.

FIG. 5 is a flowchart of a synchronization monitoring operation according to an embodiment.

FIG. 6 is a flowchart of a switching operation according to an embodiment.

FIG. 7 is an explanatory diagram of an example of establishing phase synchronization (when one system is advanced) in one embodiment.

FIG. 8 is an explanatory diagram of a switching operation when the 0-system is the active system according to the embodiment.

FIG. 9 is an explanatory diagram of a switching operation when one system in one embodiment is a working system.

[Explanation of symbols]

101 ... 0 system input terminal, 102 ... 1 system input terminal, 103
... switching signal input terminal, 104, 105 ... user cell detection unit, 106, 107, 112 ... selector, 108 ... buffer, 109 ... control unit, 110 ... coincidence comparison unit, 111 ...
Empty cell generation unit, 113 ... Active output terminal.

Claims (2)

[Claims] 1. A signal packet selecting / outputting device for inputting at least two signal signals and selectively outputting any one of the input signal signals as an active signal output, the user packet detecting a user packet from each input signal signal. Detecting means, delay means for delaying an input signal system whose phase is ahead of other input signal systems, user packets for an undelayed input signal system, and a user for an input signal system delayed by the delay means The coincidence comparison means for performing coincidence comparison with the packet, the delay amount control means for controlling the delay amount for delaying the phase of the packet of the input signal system whose phase is advanced from the result of the coincidence comparison means, and the coincidence comparison means Search for matching packets,
A synchronizing means for constantly synchronizing the phase difference after the search, an empty packet generating means for generating and outputting an empty packet, at least two or more input signal systems, an input signal system delayed by the delay means, An empty packet signal system generated by the empty packet generating means,
And a signal selecting means for selectively outputting an active system output from any one of the above. 2. The signal selecting means is generated by at least two or more respective input signal systems, an input signal system delayed by the delay means, and an empty packet generating means during a period other than switching. Of the empty packet signal systems, the active system input signal system is selected and output as it is as the active system output signal system, and the phase of the active system output signal system advances when a switching request signal is given and the switching operation is started. 2. The signal system selection output device according to claim 1, wherein any one of the input signal systems is selectively output depending on whether it is delayed or delayed.