JPH0879019A - Gate pulse generating circuit - Google Patents

Gate pulse generating circuit

Info

Publication number
JPH0879019A
JPH0879019A JP6210864A JP21086494A JPH0879019A JP H0879019 A JPH0879019 A JP H0879019A JP 6210864 A JP6210864 A JP 6210864A JP 21086494 A JP21086494 A JP 21086494A JP H0879019 A JPH0879019 A JP H0879019A
Authority
JP
Japan
Prior art keywords
circuit
switch
pulse
shot
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6210864A
Other languages
Japanese (ja)
Inventor
Akihiko Sekine
彰彦 関根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6210864A priority Critical patent/JPH0879019A/en
Publication of JPH0879019A publication Critical patent/JPH0879019A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain the gate pulse generating circuit with simple circuit configuration, high accuracy in which a pulse width and a phase of an input pulse signal are converted optionally by providing a switch circuit to the circuit to use a pulse conversion circuit of one system partly in duplicate. CONSTITUTION: A switch 2 is provided between an input pulse signal source 1 and a pre-stage one-shot circuit 4, and a switch 3 is provided in parallel with the series circuit comprising the switch 2 and the one-shot circuit 4. In the case of the mode 1, the switch 2 is turned ON and the switch 3 is turned OFF a control signal. The phase of the input pulse signal is delayed by a time (t=x1) by the one-shot circuit 4. The resulting signal is fed to a one-shot circuit 5, in which the pulse width is converted into a width of t=x2, and from which the gate pulse signal whose phase and pulse width are changed is provided as an output. In the case of the mode 2, the switch 2 is turned OFF the switch 3 is turned ON and the input pulse signal is directly fed to the one-shot circuit 5, from which the pulse width is converted into a width of t=x2 and the resulting gate pulse is outputted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、入力パルス信号をある
任意のパルス幅、位相に変換させるゲートパルス発生回
路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate pulse generation circuit for converting an input pulse signal into a certain pulse width and phase.

【0002】[0002]

【従来の技術】従来、入力信号を一定のパルス幅に変換
するワンショット回路の例として、信号の入力を検出す
る検出回路と、前記検出回路の出力を入力とする遅延回
路と、前記検出回路の出力と前記の遅延回路の出力を入
力とする論理回路とを具備し、前記遅延回路の出力を前
記検出回路のリセット信号とし、前記論理回路の出力を
ワンショットパルスの出力として取り出すことを特徴と
するワンショット回路がある(特開平2−12151
8)。
2. Description of the Related Art Conventionally, as an example of a one-shot circuit for converting an input signal into a constant pulse width, a detection circuit for detecting a signal input, a delay circuit for receiving an output of the detection circuit, and the detection circuit. And a logic circuit having the output of the delay circuit as an input, the output of the delay circuit is used as a reset signal of the detection circuit, and the output of the logic circuit is taken out as an output of a one-shot pulse. There is a one-shot circuit that
8).

【0003】又、2つのモードにおいて異なるゲートパ
ルス信号を発生する時、入力パルス信号源側でパルスの
位相及びパルス幅を変化させて出力する従来技術を図2
に示す。図2において、6は入力パルス信号源、9、1
0、11はワンショット回路、7、8は制御信号により
制御されるスイッチである。
Further, when different gate pulse signals are generated in the two modes, a conventional technique in which the phase and the pulse width of the pulse are changed and output on the input pulse signal source side is shown in FIG.
Shown in In FIG. 2, 6 is an input pulse signal source, 9 and 1
Reference numerals 0 and 11 are one-shot circuits, and 7 and 8 are switches controlled by a control signal.

【0004】モード1の時、入力パルス信号源6からの
出力信号は制御信号によりスイッチ7がON、スイッチ
8がOFFし、ワンショット回路9に入力し、図3に示
すようにt=x1の位相遅延があるパルス信号になる。
次にこの信号はワンショット回路10に入力され、t=
x2のパルス幅となり、ゲートパルスとして出力され
る。次にモード2の時、制御信号によりスイッチ7がO
FF、スイッチ8がONして入力パルス信号源6からの
出力は、ワンショット回路11に入力され、図3に示す
ようにt=x2のパルス幅となり、ゲートパルスとして
出力される。
In mode 1, the output signal from the input pulse signal source 6 is input to the one-shot circuit 9 when the switch 7 is turned on and the switch 8 is turned off by the control signal, and t = x1 as shown in FIG. It becomes a pulse signal with a phase delay.
Next, this signal is input to the one-shot circuit 10 and t =
It has a pulse width of x2 and is output as a gate pulse. Next, in the mode 2, the switch 7 is turned off by the control signal.
When the FF and the switch 8 are turned on, the output from the input pulse signal source 6 is input to the one-shot circuit 11, has a pulse width of t = x2 as shown in FIG. 3, and is output as a gate pulse.

【0005】このように、出力側にモード1、モード2
のゲートパルスを出力する時、それぞれのモードに応じ
て入力パルス信号源側でパルスの位相、幅を変化させて
いる。
In this way, mode 1 and mode 2 are provided on the output side.
When the gate pulse is output, the phase and width of the pulse are changed on the input pulse signal source side according to each mode.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、前者で
は回路構成が複雑であり、又、後者では2つのモードに
おいて異なるゲートパルス信号を発生させたい時、入力
パルス信号源側でパルスの位相、及び、パルス幅を変化
させることが困難、もしくは不可能な場合が多い。又、
必要なゲートパルスを得たい時、モードに応じたパルス
の位相、パルス幅を変換するために、図2に示すように
ワンショット回路を3回路必要となる。従って、回路設
計上においてコスト、回路規模が増加し、又、回路性能
においてはワンショット回路を多数使用することによる
パルス変換の精度の低下という問題点を有している。
However, in the former case, the circuit configuration is complicated, and in the latter case, when it is desired to generate different gate pulse signals in the two modes, the pulse phase on the input pulse signal source side, and It is often difficult or impossible to change the pulse width. or,
To obtain the necessary gate pulse, three one-shot circuits are required as shown in FIG. 2 in order to convert the phase and pulse width of the pulse according to the mode. Therefore, there are problems that the cost and the circuit scale are increased in the circuit design, and the accuracy of the pulse conversion is lowered due to the use of many one-shot circuits in the circuit performance.

【0007】本発明の目的は従来例の問題点を解消し、
回路構成を簡潔にし、精度が高く、任意のパルス幅、位
相に変換させるゲートパルス発生回路を提供しようとす
るものである。
The object of the present invention is to solve the problems of the conventional example,
An object of the present invention is to provide a gate pulse generation circuit which has a simple circuit configuration, high accuracy, and can be converted into an arbitrary pulse width and phase.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
本発明では、ワンショット回路の2回路を直列接続した
パルス変換回路と、2つのモードに応じて制御信号によ
り制御されるスイッチの2回路とを備え、前記2回路の
スイッチの内、1回路は入力パルス信号源と前段のワン
ショット回路間に設け、他のスイッチ回路は入力パルス
信号源から前段のワンショット回路と並行に設けたゲー
トパルス発生回路とした。
In order to achieve the above object, according to the present invention, there are provided two circuits of a pulse conversion circuit in which two circuits of a one-shot circuit are connected in series and a switch controlled by a control signal according to two modes. Of the switches of the two circuits, one circuit is provided between the input pulse signal source and the preceding one-shot circuit, and the other switch circuit is provided in parallel with the preceding one-shot circuit from the input pulse signal source. It was a pulse generation circuit.

【0009】[0009]

【作用】本発明は上記の構成によって、2つの異なるモ
ードの時に従来技術と同様動作で、回路規模の縮小、及
びゲートパルス作成の精度向上が図られる。
With the above-described structure, the present invention operates in the same manner as in the prior art in two different modes, thereby reducing the circuit scale and improving the accuracy of gate pulse generation.

【0010】[0010]

【実施例】以下、図面に示したゲートパルス発生回路の
一実施例につき説明する。1は入力パルス信号源、2、
3は制御信号により制御されるスイッチ、4、5はワン
ショット回路で、入力パルス信号源1とゲートパルス出
力間に直列に接続されている。スイッチ2は入力パルス
信号源1と前段のワンショット回路4との間に設けら
れ、スイッチ3は入力パルス信号源1から前段のワンシ
ョット回路4と並行するように設けられている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the gate pulse generating circuit shown in the drawings will be described below. 1 is an input pulse signal source, 2,
3 is a switch controlled by a control signal, 4 and 5 are one-shot circuits, which are connected in series between the input pulse signal source 1 and the gate pulse output. The switch 2 is provided between the input pulse signal source 1 and the preceding one-shot circuit 4, and the switch 3 is provided in parallel with the input pulse signal source 1 and the preceding one-shot circuit 4.

【0011】以下に本発明の回路の動作説明をする。上
記のような構成において、モード1の時、制御信号によ
りスイッチ2がON、スイッチ3がOFFし、ワンショ
ット回路4に入力パルス信号を入力し、図3に示すよう
にt=x1の位相遅延があるパルス信号になる。次にこ
の信号はワンショット回路5に入力され、t=x2のパ
ルス幅となり、位相及びパルス幅を変化したゲートパル
ス信号として出力される。次にモード2の時、制御信号
によりスイッチ2がOFF、スイッチ3がONして入力
パルス信号源1からの出力はワンショット回路4を飛び
越してワンショット回路5に入力され、図3に示すよう
にt=x2のパルス幅となり、ゲートパルス信号として
出力される。
The operation of the circuit of the present invention will be described below. In the above configuration, in the mode 1, the switch 2 is turned on and the switch 3 is turned off by the control signal, the input pulse signal is input to the one-shot circuit 4, and the phase delay of t = x1 as shown in FIG. There will be a pulse signal. Next, this signal is input to the one-shot circuit 5, has a pulse width of t = x2, and is output as a gate pulse signal with a changed phase and pulse width. Next, in the mode 2, the switch 2 is turned off and the switch 3 is turned on by the control signal, and the output from the input pulse signal source 1 skips the one-shot circuit 4 and is input to the one-shot circuit 5, as shown in FIG. And has a pulse width of t = x2, and is output as a gate pulse signal.

【0012】[0012]

【発明の効果】上記のように本発明のゲートパルス発生
回路は、2つのモードで異なるゲートパルスを得るため
に2系統のパルス変換回路を設けることなく、1系統の
パルス変換回路を一部多重させて必要なゲートパルスを
出力することができ、回路設計上においてコストの削
減、回路規模の縮小、又、回路性能においてゲートパル
ス作成の精度の向上が得られる等の利点がある。
As described above, the gate pulse generation circuit of the present invention does not have two pulse conversion circuits to obtain different gate pulses in two modes, and one pulse conversion circuit is partially multiplexed. Then, the required gate pulse can be output, and there are advantages that the cost can be reduced in circuit design, the circuit scale can be reduced, and the precision of gate pulse creation can be improved in circuit performance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すゲートパルス発生回路
のブロック図
FIG. 1 is a block diagram of a gate pulse generation circuit showing an embodiment of the present invention.

【図2】従来のゲートパルス発生回路のブロック図FIG. 2 is a block diagram of a conventional gate pulse generation circuit.

【図3】2つのモードによるゲートパルスを得るタイミ
ングチャート図
FIG. 3 is a timing chart diagram for obtaining a gate pulse in two modes.

【符号の説明】[Explanation of symbols]

1 入力パルス信号源 2、3 スイッチ 4、5 ワンショット回路 1 Input pulse signal source 2, 3 Switch 4, 5 One shot circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ワンショット回路の2回路を直列接続し
たパルス変換回路と、2つのモードに応じて制御信号に
より制御されるスイッチの2回路とを備え、前記2回路
のスイッチの内、1回路は入力パルス信号源と前段のワ
ンショット回路間に設け、他のスイッチ回路は入力パル
ス信号源から前段のワンショット回路と並行に設けたこ
とを特徴とするゲートパルス発生回路。
1. A pulse conversion circuit in which two one-shot circuits are connected in series, and two circuits of switches controlled by control signals according to two modes, and one circuit of the switches of the two circuits is provided. Is a gate pulse generation circuit characterized in that it is provided between the input pulse signal source and the one-shot circuit of the preceding stage, and the other switch circuits are provided in parallel with the one-shot circuit of the preceding stage from the input pulse signal source.
JP6210864A 1994-09-05 1994-09-05 Gate pulse generating circuit Pending JPH0879019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6210864A JPH0879019A (en) 1994-09-05 1994-09-05 Gate pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6210864A JPH0879019A (en) 1994-09-05 1994-09-05 Gate pulse generating circuit

Publications (1)

Publication Number Publication Date
JPH0879019A true JPH0879019A (en) 1996-03-22

Family

ID=16596371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6210864A Pending JPH0879019A (en) 1994-09-05 1994-09-05 Gate pulse generating circuit

Country Status (1)

Country Link
JP (1) JPH0879019A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0799795A2 (en) 1996-04-01 1997-10-08 Nippon Shokubai Co., Ltd. Vanadium-phosphorus oxide, method for production thereof, catalyst for vapor phase oxidation formed of the oxide, and method for partial vapor phase oxidation of hydrocarbon

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0799795A2 (en) 1996-04-01 1997-10-08 Nippon Shokubai Co., Ltd. Vanadium-phosphorus oxide, method for production thereof, catalyst for vapor phase oxidation formed of the oxide, and method for partial vapor phase oxidation of hydrocarbon

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