JPH0878661A - Semiconductor element for power - Google Patents
Semiconductor element for powerInfo
- Publication number
- JPH0878661A JPH0878661A JP21414494A JP21414494A JPH0878661A JP H0878661 A JPH0878661 A JP H0878661A JP 21414494 A JP21414494 A JP 21414494A JP 21414494 A JP21414494 A JP 21414494A JP H0878661 A JPH0878661 A JP H0878661A
- Authority
- JP
- Japan
- Prior art keywords
- guard ring
- semiconductor device
- power semiconductor
- layer
- base layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000009792 diffusion process Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 12
- 230000007423 decrease Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 3
- 238000007373 indentation Methods 0.000 claims description 2
- 238000007363 ring formation reaction Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 9
- 235000009421 Myristica fragrans Nutrition 0.000 abstract 1
- 239000001115 mace Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、静電誘導型サイリス
タ等の電力用半導体の端面構造に係り、特に電力用半導
体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an end face structure of a power semiconductor such as an electrostatic induction type thyristor, and more particularly to a power semiconductor element.
【０００２】[0002]
【従来の技術】従来の静電誘導型サイリスタでは、オフ
時の素子端面の電界集中を緩和するには、素子端面を角
度を付けて切断するベベル法と、ゲート拡散層とは独立
したフローティングＰ型拡散層を素子の最外周に形成す
るガードリング法の２つに大別される。ベベル法は従来
より高耐圧の素子に適用されてきたが、精度の良い機械
加工が必要な事や、加工後のウエハ端面の保護など複雑
な工程が要求されるため、最近はプロセスが簡単なガー
ドリング法による高耐圧化が多用されている。2. Description of the Related Art In a conventional static induction thyristor, in order to reduce electric field concentration on the device end face when it is off, a bevel method of cutting the device end face at an angle and a floating P independent of a gate diffusion layer are used. It is roughly classified into two types, that is, a guard ring method of forming a mold diffusion layer on the outermost periphery of the device. The bevel method has been conventionally applied to high withstand voltage elements, but since it requires precise machining and complicated steps such as protection of the wafer end surface after processing, the process has recently become simpler. Higher breakdown voltage is often used by the guard ring method.
【０００３】[0003]
【発明が解決しようとする課題】現在の技術では図４に
示すようにガードリング部５はゲート部４と同時に作ら
れることが多く、ガードリングの拡散深さはゲート部４
と同じであり、他に変動できるパラメータはガードリン
グ自体の幅、ガードリングとガードリングとの間隔、ガ
ードリングの本数といったものである。尚図４において
１はアノード、２はｎベース層、３はカソード部であ
る。In the present technology, as shown in FIG. 4, the guard ring portion 5 is often formed at the same time as the gate portion 4, and the diffusion depth of the guard ring depends on the gate portion 4.
The other parameters that can be changed are the width of the guard ring itself, the distance between the guard rings, and the number of guard rings. In FIG. 4, 1 is an anode, 2 is an n base layer, and 3 is a cathode part.
【０００４】素子設計では、素子端面で十分に電界が緩
和されることはもちろん、ゲート部とガードリング部で
の電界強度のバランスを考慮することで、素子に十分な
耐圧をもたせるためのガードリングの本数やその間隔が
決まる。この結果、ガードリングの本数やその間隔から
素子面積が大きくなるという欠点がある。またガードリ
ング部をゲート部と同時に作った場合、ガードリング部
の設計上のパラメータに制限が生じるという問題があ
る。In the element design, the electric field is sufficiently relaxed at the element end face, and in consideration of the balance of the electric field strengths at the gate portion and the guard ring portion, the guard ring for giving the element sufficient withstand voltage is provided. The number of and the intervals are determined. As a result, there is a drawback in that the element area becomes large due to the number of guard rings and their intervals. Further, when the guard ring part is formed at the same time as the gate part, there is a problem that the design parameters of the guard ring part are limited.
【０００５】本発明は上記の点に鑑みてなされたもので
その目的は、素子面積を増やすことなく素子端面で十分
に電界が緩和される電力用半導体素子を提供することに
ある。The present invention has been made in view of the above points, and an object thereof is to provide a power semiconductor element in which the electric field is sufficiently relaxed at the element end face without increasing the element area.
【０００６】[0006]
【課題を解決するための手段】本発明は、ベース層とア
ノード層を積層し、前記ベース層の中央部表面に、前記
積層方向に直交する方向にゲート層とカソード層を所定
間隔で交互に複数個形成した電力用半導体素子におい
て、（１）前記ゲート層およびカソード層の外周のベー
ス層表面に、内周から外周に向けて深さが段階的に浅く
なるｎ個のガードリングを有したガードリング部を形成
したことを特徴とし、（２）前記ゲート層およびカソー
ド層の外周のベース層表面に、内周から外周に向けて濃
度が段階的に低くなるｎ個のガードリングを有したガー
ドリング部を形成したことを特徴とし、（３）前記ガー
ドリング部は、ガードリング形成位置に不純物を注入し
た後当該ガードリングの押し込み拡散を行う工程を最内
周のガードリングから最外周のガードリングまで順次行
って形成したことを特徴とし、（４）前記ガードリング
部は、最内周のガードリングから最外周のガードリング
に向けて濃度が段階的に低くなるように不純物を注入し
た後、押し込み拡散を行って形成したことを特徴とし、
（５）前記ガードリング部は、ｎ個のガードリングを同
一濃度で不純物の拡散を行い、その後最内周のガードリ
ングから最外周のガードリングに向けてエッチング量が
段階的に増大するようにエッチングを行い、その後押し
込み拡散を行って形成したことを特徴とし、（６）前記
ガードリング部の最内周のガードリングは、前記ゲート
層およびカソード層よりも深く拡散されていることを特
徴としている。According to the present invention, a base layer and an anode layer are laminated, and a gate layer and a cathode layer are alternately arranged at a predetermined interval on a surface of a central portion of the base layer in a direction orthogonal to the laminating direction. In a plurality of power semiconductor elements formed, (1) n guard rings having a depth gradually decreasing from the inner circumference to the outer circumference are provided on the surface of the base layer on the outer circumference of the gate layer and the cathode layer. A guard ring portion is formed, and (2) n guard rings having a concentration gradually decreasing from the inner circumference to the outer circumference are provided on the surface of the base layer on the outer circumference of the gate layer and the cathode layer. The guard ring portion is formed, and (3) the guard ring portion is formed by performing an injecting diffusion of the guard ring at the guard ring forming position and then performing a diffusion process by pushing the guard ring. It is characterized in that it is formed by sequentially performing steps up to the outermost guard ring. (4) The guard ring portion is formed of impurities so that the concentration gradually decreases from the innermost guard ring to the outermost guard ring. Is formed by injecting and diffusing,
(5) The guard ring portion diffuses impurities in the n guard rings at the same concentration, and thereafter the etching amount is increased stepwise from the innermost guard ring to the outermost guard ring. It is characterized in that it is formed by performing etching and then indenting diffusion. (6) The innermost guard ring of the guard ring portion is diffused deeper than the gate layer and the cathode layer. There is.
【０００７】[0007]
【作用】ガードリングはゲート層およびカソード層より
も深く形成されるので、電界の集中がより深いところで
起こるため、放熱性が向上し耐圧の向上が期待できる。
また表面の電荷の影響を受けにくく、安定した耐圧がえ
られる。Since the guard ring is formed deeper than the gate layer and the cathode layer, the concentration of the electric field occurs at a deeper place, so that the heat dissipation is improved and the breakdown voltage can be expected to be improved.
Further, it is not easily affected by surface charges, and a stable breakdown voltage can be obtained.
【０００８】[0008]
【実施例】以下、本発明の一実施例を図面を参照しなが
ら説明する。本発明では図１に示すようにガードリング
が外周へいくほど深さと濃度が段階的に小さくなるよう
に構成した。図１において１０はｎベース層、１５はガ
ードリング部である。このとき、となり同士のガードリ
ングの接合深さの比が適切であることと、一番深いガー
ドリング（最内周のガードリング）でもその直下のｎベ
ース層１０の厚さが耐圧を確保するのに十分である必要
がある。その作製方法として以下の３つの方法を用い
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the present invention, as shown in FIG. 1, the depth and concentration are gradually reduced toward the outer periphery of the guard ring. In FIG. 1, 10 is an n base layer, and 15 is a guard ring portion. At this time, the ratio of the junction depths of adjacent guard rings is appropriate, and the thickness of the n base layer 10 immediately below the guard ring at the deepest guard ring (guard ring at the innermost circumference) ensures the breakdown voltage. Need to be enough. The following three methods are used as the manufacturing method.
【０００９】（１）図２（ａ）に示すように、まずイオ
ン注入装置で一番深くなるガードリングであるＡ部だけ
に不純物の注入を行う。それを図２（ｂ）に示すように
押し込み拡散を行う。次に図２（ｃ）に示すように、２
番目に深くなるＢ部にだけ不純物の注入を行う。それを
同様に押し込み拡散を行うことで、図２（ｄ）に示すよ
うにＢ部はもちろんＡ部も押し込まれるため、Ａ部とＢ
部の深さの差が生まれる。この要領で必要な本数だけ、
前記不純物注入と押し込み拡散を繰り返す。ゲート領域
は、これらの工程中の適切なところで行うことになる。
また、外周に行くほど濃度が小さくなるようにするた
め、総拡散深さを考慮して不純物の注入量を制御する必
要がある。(1) As shown in FIG. 2A, first, impurities are implanted only in the portion A, which is the guard ring that is the deepest in the ion implanter. It is pushed and diffused as shown in FIG. Next, as shown in FIG.
Impurities are implanted only in the B portion which becomes the second deepest. By pressing and diffusing it in the same manner, as shown in FIG. 2D, not only the B portion but also the A portion is pushed in.
The difference in depth of the part is born. As many as necessary in this way,
The impurity implantation and the indentation diffusion are repeated. The gate region will be done at an appropriate point during these steps.
Further, in order to reduce the concentration toward the outer periphery, it is necessary to control the impurity implantation amount in consideration of the total diffusion depth.
【００１０】（２）図３（ａ）に示すように、Ａ，Ｂ，
Ｃ，Ｄ部の濃度がＡ＞Ｂ＞Ｃ＞Ｄになるようにイオン注
入装置で不純物を注入する。それを図３（ｂ）に示すよ
うに押し込み拡散を行う。このとき拡散係数の関係から
濃度が濃いものほど深く拡散されるため前記（１）と同
様な結果が得られる。(2) As shown in FIG. 3 (a), A, B,
Impurities are implanted by an ion implantation device so that the concentrations of C and D parts are A>B>C> D. It is pushed in and diffused as shown in FIG. At this time, from the relationship of the diffusion coefficient, the higher the concentration is, the deeper the diffusion is, so that the same result as the above (1) is obtained.
【００１１】（３）Ａ，Ｂ，Ｃ，Ｄ部に同一濃度で不純
物を拡散した後、ごく表面の濃度の濃い部分を必要量だ
けエッチングを行う。このときエッチング量がＡ＜Ｂ＜
Ｃ＜Ｄとなるようにすれば、前記（２）と同様の濃度差
が生まれ、これを押し込み拡散することで前記（１）、
（２）と同様な結果が得られる。またこの方法では不純
物の拡散を、イオン注入装置を用いなくても、通常の電
気炉による拡散で行うことができる。(3) After diffusing impurities at the same concentration in the A, B, C, and D portions, a necessary amount of etching is performed on a very dense portion of the surface. At this time, the etching amount is A <B <
By setting C <D, the same concentration difference as in the above (2) is generated, and by pushing this and diffusing, the above (1),
Similar results to (2) are obtained. Further, in this method, diffusion of impurities can be performed by diffusion in a normal electric furnace without using an ion implantation device.
【００１２】[0012]
【発明の効果】以上のように本発明によれば、ベース層
とアノード層を積層し、前記ベース層の中央部表面に、
前記積層方向に直交する方向にゲート層とカソード層を
所定間隔で交互に複数個形成した電力用半導体素子にお
いて、前記ゲート層およびカソード層の外周のベース層
表面に、内周から外周に向けて深さが段階的に浅くなる
とともに、濃度が段階的に低くなるｎ個のガードリング
を有したガードリング部を形成したので、次のような優
れた効果が得られる。As described above, according to the present invention, the base layer and the anode layer are laminated, and the central surface of the base layer is
In a power semiconductor device in which a plurality of gate layers and cathode layers are alternately formed at predetermined intervals in a direction orthogonal to the stacking direction, on the base layer surface of the outer periphery of the gate layer and the cathode layer, from the inner periphery to the outer periphery. Since the guard ring portion having n guard rings whose depth gradually decreases and the concentration gradually decreases is formed, the following excellent effects can be obtained.
【００１３】（１）シミュレーションなどの結果から、
電界の集中は表面に近い場所で起こっていることが分か
っている。本発明によればゲート部よりも深くガードリ
ングが形成されるので、電界の集中がより深いところで
起こるため、放熱性が向上し耐圧の向上が期待できる。
また表面の電荷の影響を受けにくく、安定した耐圧がえ
られる。(1) From the results of simulation and the like,
It is known that the electric field concentration occurs near the surface. According to the present invention, since the guard ring is formed deeper than the gate portion, the concentration of the electric field occurs at a deeper place, so that the heat dissipation is improved and the breakdown voltage can be expected to be improved.
Further, it is not easily affected by surface charges, and a stable breakdown voltage can be obtained.
【００１４】（２）ガードリング部が外周に行くほど深
さと濃度が段階的に小さくなるような構造であるため、
ＶＬＤ（Ｖａｒｉａｔｉｏｎ ｏｆ Ｌａｔｅｒａｌ
Ｄｏｐｉｎｇ）技術と同様の素子端面で電界の集中が緩
和される効果が期待できる。(2) Since the guard ring portion has a structure in which the depth and concentration gradually decrease toward the outer periphery,
VLD (Variation of Lateral)
The effect of alleviating the concentration of the electric field can be expected at the element end face similar to the Doping) technique.
【図１】本発明の一実施例を示す要部断面構成図。FIG. 1 is a cross-sectional configuration diagram of essential parts showing an embodiment of the present invention.
【図２】本発明の半導体素子の製造手順の一例を示す要
部断面構成図。FIG. 2 is a cross-sectional configuration diagram of an essential part showing an example of a manufacturing procedure of a semiconductor element of the present invention.
【図３】本発明の半導体素子の製造手順の他の例を示す
要部断面構成図。FIG. 3 is a cross-sectional configuration diagram of essential parts showing another example of the manufacturing procedure of the semiconductor element of the present invention.
【図４】従来の半導体素子の一例を示す断面構成図。FIG. 4 is a cross-sectional configuration diagram showing an example of a conventional semiconductor element.
１…アノード ２…ｎベース層 ３…カソード部 ４…ゲート部 ５，１５…ガードリング部 DESCRIPTION OF SYMBOLS 1 ... Anode 2 ... n Base layer 3 ... Cathode part 4 ... Gate part 5, 15 ... Guard ring part
Claims (6)
ース層の中央部表面に、前記積層方向に直交する方向に
ゲート層とカソード層を所定間隔で交互に複数個形成し
た電力用半導体素子において、前記ゲート層およびカソ
ード層の外周のベース層表面に、内周から外周に向けて
深さが段階的に浅くなるｎ個のガードリングを有したガ
ードリング部を形成したことを特徴とする電力用半導体
素子。1. A power semiconductor device in which a base layer and an anode layer are laminated, and a plurality of gate layers and cathode layers are alternately formed at predetermined intervals on a central surface of the base layer in a direction orthogonal to the laminating direction. In the above, a guard ring portion having n guard rings whose depth gradually decreases from the inner circumference to the outer circumference is formed on the surface of the base layer on the outer circumference of the gate layer and the cathode layer. Power semiconductor device.
ース層の中央部表面に、前記積層方向に直交する方向に
ゲート層とカソード層を所定間隔で交互に複数個形成し
た電力用半導体素子において、前記ゲート層およびカソ
ード層の外周のベース層表面に、内周から外周に向けて
濃度が段階的に低くなるｎ個のガードリングを有したガ
ードリング部を形成したことを特徴とする電力用半導体
素子。2. A power semiconductor device in which a base layer and an anode layer are laminated, and a plurality of gate layers and cathode layers are alternately formed at predetermined intervals on a surface of a central portion of the base layer in a direction orthogonal to the laminating direction. In Claim 1, a guard ring portion having n guard rings whose concentration gradually decreases from the inner circumference to the outer circumference is formed on the surface of the base layer on the outer circumference of the gate layer and the cathode layer. Semiconductor device.
成位置に不純物を注入した後当該ガードリングの押し込
み拡散を行う工程を最内周のガードリングから最外周の
ガードリングまで順次行って形成したことを特徴とする
請求項１又は２に記載の電力用半導体素子。3. The guard ring portion is formed by sequentially performing a step of injecting impurities into a guard ring formation position and then performing a push diffusion of the guard ring from the innermost guard ring to the outermost guard ring. The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device.
リングから最外周のガードリングに向けて濃度が段階的
に低くなるように不純物を注入した後、押し込み拡散を
行って形成したことを特徴とする請求項１又は２に記載
の電力用半導体素子。4. The guard ring portion is formed by implanting impurities so that the concentration gradually decreases from the innermost guard ring to the outermost guard ring, and then performing push diffusion. The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device.
ングを同一濃度で不純物の拡散を行い、その後最内周の
ガードリングから最外周のガードリングに向けてエッチ
ング量が段階的に増大するようにエッチングを行い、そ
の後押し込み拡散を行って形成したことを特徴とする請
求項１又は２に記載の電力用半導体素子。5. The guard ring portion diffuses impurities in the n guard rings at the same concentration, and then the etching amount increases stepwise from the innermost guard ring to the outermost guard ring. 3. The power semiconductor device according to claim 1, wherein the power semiconductor device is formed by performing etching as described above and then performing indentation diffusion.
ングは、前記ゲート層およびカソード層よりも深く拡散
されていることを特徴とする請求項１又は２又は３又は
４又は５に記載の電力用半導体素子。6. The guard ring at the innermost periphery of the guard ring portion is diffused deeper than the gate layer and the cathode layer, according to claim 1, 2 or 3 or 4 or 5. Power semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21414494A JPH0878661A (en) | 1994-09-08 | 1994-09-08 | Semiconductor element for power |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21414494A JPH0878661A (en) | 1994-09-08 | 1994-09-08 | Semiconductor element for power |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0878661A true JPH0878661A (en) | 1996-03-22 |
Family
ID=16650962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21414494A Pending JPH0878661A (en) | 1994-09-08 | 1994-09-08 | Semiconductor element for power |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0878661A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999023703A1 (en) * | 1997-11-03 | 1999-05-14 | Infineon Technologies Ag | High voltage resistant edge structure for semiconductor elements |
| EP1076364A2 (en) * | 1999-08-11 | 2001-02-14 | Dynex Semiconductor Limited | Power semiconductor device |
| US9530836B2 (en) | 2015-05-27 | 2016-12-27 | Toyota Jidosha Kabushiki Kaisha | Semiconductor apparatus |
-
1994
- 1994-09-08 JP JP21414494A patent/JPH0878661A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999023703A1 (en) * | 1997-11-03 | 1999-05-14 | Infineon Technologies Ag | High voltage resistant edge structure for semiconductor elements |
| EP1076364A2 (en) * | 1999-08-11 | 2001-02-14 | Dynex Semiconductor Limited | Power semiconductor device |
| EP1076364A3 (en) * | 1999-08-11 | 2003-07-30 | Dynex Semiconductor Limited | Power semiconductor device |
| US9530836B2 (en) | 2015-05-27 | 2016-12-27 | Toyota Jidosha Kabushiki Kaisha | Semiconductor apparatus |
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