JPH0877712A - Method and device for processing digital signal - Google Patents

Abstract

PURPOSE: To provide a method and a device for processing a digital signal, wherein a PR system is applied to a magnetic recording/reproducing system without using a precoder, error propagation is limited and data identification is made simple. CONSTITUTION: A recording signal is converted into a symbol NRZI, recorded in a magnetic medium 7 and reproduced. A reproducing signal is passed through a PR equalizer 41 and inputted to a data identification circuit 10. Here, when the minimum number of '0' symbols for continuous recording signals is (d) and the number of steps (n) for the PR equalizer 41 is 1<=n>=d, '1' of 1 bit in the recording signal is '1' of (n+1) bit sequence in the output signal of the data identification circuit. In a (n+2) state order circuit 42, when '1' of (n+1) bit sequence is detected, '1' is caused to be outputted by one bit and thereby a recording signal is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing method and apparatus for recording or transmitting a digital signal and reproducing or receiving the digital signal for decoding, and more particularly to an NRZI code for partial response class IV. The present invention relates to a digital signal processing method suitable for application to an apparatus for recording / reproducing or transmitting / receiving via a transmission path having characteristics, and the apparatus.

[0002]

2. Description of the Related Art The transfer characteristic of a magnetic recording system is a differential type,
Further, since the rotary transformer is used for exchanging the signal between the magnetic head and the recording / reproducing circuit, the low frequency component of the signal cannot be recorded / reproduced.

Therefore, an operation called modulation or recording coding for converting a signal to be recorded to reduce a low frequency component is performed, and up to now, various characteristic modulation systems have been proposed. It was

Among these, partial response (PR) class I
There is a modulation scheme called NRZI or PR (1, -1) belonging to V, and a modulation scheme called interleaved NRZI or PR (1, 0, -1) also belonging to PR class IV.

Regarding these codes, for example, "Digital Video Recording Technology" by Yoshizumi Eto et al. (August 1990)
Monthly Daily Kogyo Shimbun, pp. 46-48).

As described above, since the magnetic recording / reproducing system has a differential characteristic, when data is recorded / reproduced, the signal waveform spreads and intersymbol interference occurs.

The PR system can be said to be a system for positively utilizing this inter-code interference to shape the power spectrum of the code so as to be suitable for the transfer characteristics of the transmission line.

The impulse response characteristic f (D) of the partial response class IV is expressed by f (D) = (1-D) (1 + D) ** n (D: 1 bit delay operator; **: exponentiation) .

N is an integer value of 0 or more, and PR (1, -1) when n = 0, and PR (1,0, -1) when n = 1.
(Also simply called PR4), when n = 2, PR (1,
1, -1, -1) (extended PR4: called EPR4), and PR (1, 2, 0, -2,-) when n = 3.
1) (referred to as EEPR4), and so on.

Note that n used in this specification is
Unless otherwise specified, the order of the impulse response f (D) is represented.

The frequency characteristic of PR (1, -1) is suitable for limiting the low frequency component which is difficult to record and reproduce due to its small gain in the low frequency region.

Further, the frequency characteristic of n ≧ 1 has a band-pass type characteristic that suppresses high frequency components in addition to low frequency regions, and has an effect of attenuating high frequency components of noise.

[0013] Which of these methods is superior cannot be generally stated. For example, in the case of PR4 and EPR4, when the linear recording density is high, EPR4 has a smaller gain at high frequency, which is advantageous. , "Nikkei Electronics" (No. 599, January 17, 1994, published by Nikkei BP, pages 71 to 97).

FIG. 19 is a block diagram showing a schematic configuration of a conventional magnetic recording / reproducing system using PR class IV.

In FIG. 19, first, a digital signal represented by "0" or "1" to be recorded is input from a recording signal input terminal 1 and converted into an NRZI code in an NRZI encoder 2.

The NRZI code is a code whose polarity is inverted when "1" appears in the recording signal.

Here, the polarity inversion means that the signal value changes from "1" to "0" or from "0" to "1".

The NRZI encoder 2 comprises a 1-bit delay element 3 and a digital adder 4 (modulo 2 digital adder).

Further, the NRZI encoder 2 is 1 / (1+
It will have the characteristics expressed in D).

Next, the NRZI code is the precoder 121.
Is input to

In the PR system, the reproduced waveform includes intersymbol interference as described above, and it is necessary to remove the intersymbol interference in order to reproduce the original data.

The precoder 121 is for adding in advance to the NRZI code the intersymbol interference opposite to that given by the recording / reproducing system.

The precoder 121 is used by the NRZI encoder 2
The circuit has the same configuration as that of n stages connected in series, and its characteristic is represented by 1 / (1 + D) ** n.

In general, the NRZI encoder 2 and the precoder 121 may be collectively referred to as a precoder, but in this specification, they are distinguished and expressed.

The output signal of the precoder 121 is sent to the recording / reproducing system 5, recorded on the magnetic medium 7 by the magnetic head 6a, and reproduced by the magnetic head 6b.

In this case, it is known that the recording / reproducing system 5 has a (1-D) differential characteristic.

The reproduced signal is input to the PR equalizer 41.

The PR equalizer 41 is a circuit in which n stages of circuits having a characteristic of (1 + D) consisting of a 1-bit delay element 3 and an adder 9 are connected in series.

The characteristic of the PR equalizer 41 is (1 + D) ** n
In addition to the characteristics (1-D) of the recording / reproducing system 5, (1
-D) (1 + D) ** n, and the PR class IV impulse response f (D) is realized.

The output of the PR equalizer 41 is input to the data discrimination circuit 10.

Since the PR equalizer 41 uses the adder 9, its output is a multilevel signal, and when n = 0, "-"
Ternary signal of 1 ”,“ 0 ”, and“ 1 ”, or“ n ”when n ≧ 1
It becomes a (2 ** n + 1) value signal taking an integer value of -2 ** (n-1) "to" 2 ** (n-1) ".

The data discriminating circuit 10 converts the multi-valued output signal of the PR equalizer 41 into an output signal. When the addition in the PR equalizer 41 is modulo 2 addition, k
Where 0 ≦ k <n is an integer and the absolute value of the input signal is 2 **
If k, "0" is output, and if 2 ** k-1, "1" is output.

Since addition and subtraction are equivalent in the modulo 2 operation, the overall characteristic from the NRZI encoder 2 to the data discrimination circuit 10 is 1, and the recorded signal is obtained.

However, in the magnetic recording / reproducing system shown in FIG. 19, the signals recorded on the medium differ depending on the presence or absence of the precoder on the recording side, so that compatibility of the recording medium is required for the VTR (Video Tape Record).
er) and MT for computers (Magnetic Tape)
For example, the PR method not adopted in the standard cannot be used.

Therefore, as a conventional technique for applying the PR system without using a precoder, for example, Japanese Patent Laid-Open No. 5-325
No. 425, “Code detecting device”, “Digital signal recording / reproducing system and device”, Japanese Patent Application Laid-Open No. 5-221950, “Digital signal recording device”. A reproducing system and a digital signal recording / reproducing apparatus "are known.

[0036]

The frequency characteristic of PR class IV is close to that of the magnetic recording system, and the S / N ratio (Signal
This is a technology that is effective in improving al to Noise ratio.

However, as described above, the signals recorded on the recording medium differ depending on the presence or absence of the precoder on the recording side. Therefore, the VTR (Vi
Deo Tape Recorder) and computer MT
In (Magnetic Tape) and the like, there is a problem that a PR method that is not adopted in the standard cannot be used.

Since the magnetic recording / reproducing system shown in FIG. 19 is a linear system, the characteristics of the system do not change even if the order of blocks is changed.

Therefore, although it is possible to place the precoder 121 after the data discrimination circuit 10, if an error occurs even in one bit in the recording / reproducing system 5, there is a risk that the error will propagate infinitely due to the feedback loop in the precoder 121. Yes, it is not used in actual equipment.

Further, Japanese Patent Laid-Open No. 5-325425, which is known as a conventional technique for applying the PR system without using a precoder, is known.
In the "code detecting device" described in the publication, since the property of the interleaved NRZI code is used, PR
It is applicable only to (1, 0, -1), and the decoding circuit is complicated.

Further, in the "digital signal recording / reproducing system and apparatus" described in Japanese Patent Laid-Open No. 307837/1993, the output signal of the PR channel is processed as a multi-valued signal, so that it has a high-order response characteristic. When applied to the PR system, there is a problem in that the multi-level discrimination circuit and the arithmetic circuit become complicated.

In Japanese Patent Application No. Hei 5-221950, "Digital Signal Reproducing Method and Digital Signal Recording / Reproducing Apparatus", the reproducing side includes an NRZI encoding circuit, and therefore is applied to recording / reproducing of NRZI code. Then, the reproduction side will have an NRZI encoding circuit and a decoding circuit,
There is a problem that the device becomes complicated.

Further, only the application of PR (1, 0, -1) is taken into consideration, and the conditions required for the recording signal in the case of applying the high-order PR system which can be expected to further improve the S / N ratio, The operation of the multilevel signal identification circuit is not described.

That is, it is difficult to select the PR system having the optimum response characteristic for the recording / reproducing system in the conventional technique which applies the PR system without using the precoder, and the EPR is also adopted.
In the PR system in which the output of the equalizer such as 4 or EEPR4 is a multi-valued output, there is a problem that the data discrimination circuit becomes complicated.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a digital signal processing method and apparatus in which the PR system is magnetically recorded and reproduced without using a precoder. It is to provide a technique that can be applied to a system, can limit error propagation, and can simplify data discrimination.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0047]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) A signal reproduced from the recording medium by converting a digital signal in which the minimum number of consecutive "0" symbols between two "1" symbols is d into an NRZI code and recording the same on the recording medium. In the digital signal processing method for decoding the digital signal from the recording medium, the frequency characteristic is (1-D) (1 + D) with respect to the reproduction signal from the recording medium.
Signal processing represented by ** n (however, D is a 1-bit delay operator; ** is a power; n is an integer of 1 ≦ n ≦ d) is made into a multilevel signal, and a specific value is specified from the multilevel signal. It is characterized in that a signal pattern is detected and decoded into the digital signal.

(2) In the above-mentioned means (1), the multi-valued signal subjected to the signal processing is discriminated into a binary signal according to a signal value, and a specific symbol is (n + 1) in the binary signal by the sequential logic. ) It is characterized in that it is detected that the bits are continuous and is decoded into the digital signal.

(3) In the above-mentioned means (1), the multivalued signal subjected to the signal processing is discriminated into a ternary signal according to the signal value, and a specific symbol is (n + 1) in the ternary signal by the sequential logic. ) It is characterized in that it is detected that the bits are continuous and is decoded into the digital signal.

(4) The means of (1) is characterized in that a specific signal pattern is detected from the multi-valued signal subjected to the signal processing by a maximum likelihood decoding method and is decoded into the digital signal.

(5) A signal reproduced from the recording medium by converting a digital signal in which the minimum number of consecutive "0" symbols between two "1" symbols is d to an NRZI code and recording the same on the recording medium. In the digital signal processing device for decoding the digital signal from, the frequency characteristic is (1-D) (1 + D) with respect to the reproduced signal from the recording medium.
An equalization circuit that outputs a multilevel signal by performing signal processing represented by ** n (where D is a 1-bit delay operator; ** is a power; n is an integer of 0 ≦ n ≦ d); And a decoding circuit for detecting a specific signal pattern from the multilevel signal output from the equalization circuit and decoding the signal pattern into the digital signal.

(6) In the above-mentioned means (5), the decoding circuit discriminates a multilevel signal output from the equalization circuit into a binary signal according to a signal value, and a discriminator circuit outputs the discrimination signal. And a sequential circuit which detects that a specific symbol continues in (n + 1) bits in the value signal and decodes it into the digital signal.

(7) In the above-mentioned means (5), the decoding circuit discriminates a multi-valued signal output from the equalization circuit into a ternary signal according to a signal value, and a discriminating circuit outputs a three-valued signal. And a sequential circuit which detects that a specific symbol continues in (n + 1) bits in the value signal and decodes it into the digital signal.

(8) In the means of (5), the decoding circuit is a maximum likelihood decoding circuit which detects a specific signal pattern from the multi-valued signal output from the equalization circuit and decodes it into the digital signal. It is characterized by being done.

[0056]

According to each of the above means, N is used without using a precoder.
The output of the RZI encoder is directly recorded and reproduced on the recording medium, and the reproduced signal is input to the PR equalizer.

In this case, since the NRZI code is a code whose polarity is inverted when "1" appears in the recording signal, "1" of the recording signal rises or falls in the NRZI code. become.

Since the recording / reproducing system has a differential characteristic,
The reproduced signal becomes "1" at the rising edge of the NRZI code and becomes "-1" at the falling edge, and "1" of the recording signal corresponds to "1" or "-1" of the reproduced signal.

This reproduction signal is input to the PR equalizer and the operation of adding the signal delayed by 1 bit and the original signal is repeated n times, so that "1" of the reproduction signal is reproduced later "-1". Various output patterns are obtained by adding "" and "1".

Therefore, there is no one-to-one correspondence between the output signal of the PR equalizer and "1" of the recording signal.

Here, it is assumed that the minimum value d of the number of consecutive "0" s in the recording signal satisfies the property of d ≧ n.

In this case, the interval between "1" and "-1" of the reproduced signal is d bits or more, and the maximum delay in the PR equalizer is n bits, and d≥n. The delayed signal of "1" or "-1" reproduced at time is not added to the next reproduced "-1" or "1" across several bits of "0".

Considering the output of the PR equalizer, its characteristic is represented by (1 + D) ** n, so that the "
The signal value k bits after 1 "or" -1 "is a binomial constant nCk (the number of combinations for selecting k from n) or -nC.
k.

In response to this signal, the data discrimination circuit is "1".
If the above or "-1" or less is discriminated as "1" and "0" as "0", both "1" and "-1" of the reproduced signal become "1" of (n + 1) consecutive bits.

Therefore, since "1" of the recording signal corresponds to "1" of (n + 1) consecutive bits of the PR equalizer output, "1" of consecutive (n + 1) bits from the PR equalizer output.
If "1" is output when "1" is detected, a recording signal can be obtained.

As a result, the compatibility of the recording medium can be maintained, and the PR system which is not adopted in the standard is applied to the magnetic recording / reproducing apparatus such as the VTR or the computer MT which requires the compatibility of the recording medium. It becomes possible.

Further, the original PR class IV data discriminating circuit is "-2 ** (n-1)" to "when n≥1.
Input a (2 ** n + 1) value signal that takes an integer value of 2 ** (n-1) ", and let k be an integer of 0≤k <n, and if the absolute value of the input signal is 2 ** k" If "0" and 2 ** k-1, "1" is output.

Therefore, in the original PR class IV data discriminating circuit, (2 ** n + 1) kinds of signals must be discriminated. On the other hand, in the data discriminating circuit of the present invention, the input is also a multilevel signal. However, "1" or more, "
Only three types of discrimination, 0 "and" -1 "or less, are required, and it can be realized by a simple circuit.

[0069]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a diagram showing a schematic configuration of a digital signal recording / reproducing apparatus according to an embodiment (embodiment 1) of the present invention.

In FIG. 1, 1 is a recording signal input terminal, 2
Is an NRZI encoding circuit, 3 is a 1-bit delay element, 4 is an adder (modulo 2 adder), 5 is a magnetic recording / reproducing system, 6
Reference numerals a and 6b are magnetic heads, 7 is a magnetic medium, 8 is a PR equalizer, 9 is an adder, 10 is a data discrimination circuit, 11 is a three-state sequential circuit, and 12 is a reproduction signal output terminal.

FIG. 2 is a diagram showing an example of a time chart of the digital signal recording / reproducing circuit shown in FIG.

In FIG. 2, (2a) is a clock and (2a)
b) is a recording signal input from the recording signal input terminal 1,
(2c) is the NRZ output from the NRZI encoding circuit 2.
I signal, (2d) is a reproduced signal reproduced from the magnetic medium 7 by the magnetic head 6b, (2e) is an equalized signal output from the PR equalizer 8, and (2f) is output from the data discrimination circuit 10. The discrimination signal, (2g), is the output signal of the 3-state sequential circuit 11.

The operation of the first embodiment will be described below with reference to FIGS.

The recording signal (2b) input from the recording signal input terminal 1 is continuous between two "1" symbols.
It is assumed that the minimum number of 0 "symbols is a digital signal of 1.

The recording signal (2b) is input to the NRZI encoding circuit 2 and the NRZI signal (2c) is output.

The NRZI signal (2c) one bit before is "
When "1" of the recording signal (2b) is input when it is "0", "1" is output by the adder 4 (adder of modulo 2).

This "1" output is delayed by the 1-bit delay element 3 and added by the adder 4 of modulo 2 to "0" of the bit next to "1" of the recording signal (2b) to obtain "1". ”
Is output.

This "1" output is the next recording signal (2b).
Will continue until "1" appears.

Similarly, one bit before the NRZI signal (2
When "1" of the recording signal (2b) is input when c) is "1", "0" continues to be output until the next "1" of the recording signal (2b) is input. .

As described above, since the NRZI signal (2c) is a code whose polarity is inverted when "1" appears in the recording signal (2b), "1" of the recording signal (2b) becomes NRZ.
The I signal (2c) causes the signal to rise or fall, and "0" of the recording signal (2b) holds the output for the NRZI signal (2c).

The NRZI signal (2c) is sent to the magnetic head 6a.
Is recorded on the magnetic medium 7 and reproduced by the magnetic head 6b to form a reproduced signal (2d).

The response characteristic of the magnetic recording / reproducing system 5 is (1-D).
It is known that it is a differential characteristic expressed by.

Therefore, in the reproduced signal (2d), NR
The rising edge of the ZI signal (2c) is 1-bit "1",
The trailing edge is 1-bit "-1".

Here, the reproduced signal (2d) is actually an analog signal or a digital signal sampled by an analog / digital converter and does not have a waveform as shown in FIG. A signal close to is written as "1", and a signal whose signal value is close to -1 is written as "-1".

Hereinafter, the same applies to the equalized signal (2e).

From the above, "1" of the recording signal (2b) is
1-bit "1" or "-1" in the playback signal (2d)
Then, the "0" of the recording signal (2b) becomes the reproduction signal (2
It becomes "0" in d).

The reproduction signal (2d) is input to the PR equalizer 8.

The PR equalizer 8 has a response characteristic of (1 + D), and the response characteristic combined with the recording / reproducing system 5 is (1-D) (1
+ D), which is a partial response class IV channel.

The reproduction signal (2d) is supplied to the 1-bit delay element 3
The signal delayed by is added by the adder 9.

Therefore, the reproduction signal (2d) is "1".
Becomes "1, 1", and "-1" becomes "-1, -1".

Here, the recording signal (2b) has two "1" s.
The minimum number of consecutive "0" symbols between symbols is 1
Since it is a digital signal of, the reproduction signal (2d)
The interval between 1 "and" -1 "is 1 bit or more.

Since the delay of the reproduction signal (2d) is only 1 bit, "1" and "-1" of the reproduction signal (2d) will not be added to become "0".

From this, "1" of the recording signal (2b) is
The equalized signal (2e) becomes "1, 1" or "-1, -1" of two consecutive bits.

Further, "0" of the recording signal (2b) is "1" before the recording signal (2b) in the equalization signal (2e).
If it is 1 ", it becomes" 1 "or" -1 ", and if the recording signal (2b) one bit before is" 0 ", it becomes" 0 ".

The equalization signal (2e) is supplied to the data discrimination circuit 10
Is input to

The data discrimination circuit 10 has a threshold value T + having a value between 0 and 1 and a threshold value T- having a value between 0 and -1, and the signal value of the input signal is equal to or higher than T + or equal to or lower than T-. If it is larger than T- and smaller than T +, it is "0".
Is output.

This output signal is a binary digital signal of "0" or "1".

Therefore, the recording signal (2b) is "1".
Becomes "1, 1" of the discrimination signal (2f), and "0" of the recording signal (2b) is "1" if the recording signal (2b) one bit before in the discrimination signal (2f) is "1". If the recording signal (2b) one bit before is "0", it becomes "0".

The discrimination signal (2f) is the three-state sequential circuit 11
Is input to

The 3-state sequential circuit 11 outputs the discrimination signal (2f).
Is a circuit for obtaining the recording signal (2b) from

Since "1" of the recording signal (2b) corresponds to "1,1" of the discrimination signal (2f), the 3-state sequential circuit 11 outputs "1,1" to the discrimination signal (2f). If "1" is detected, "1" may be output.

FIG. 3 is a state transition diagram showing the operation of the 3-state sequential circuit 11 shown in FIG.

S0 is the initial state, S1 is the discrimination signal (2f).
Is detected, and S2 is a state in which "1, 1" is detected from the discrimination signal (2f).

When transitioning from state S1 to state S2
By outputting "1" and "0" at other times, a signal (2g) delayed by one clock from the recording signal (2b) is obtained from the discrimination signal (2f).

Since the three-state sequential circuit 11 has three states, it can be constituted by two flip-flop circuits and can be realized by a very simple circuit.

FIG. 4 is a diagram showing an example of the circuit configuration of the three-state sequential circuit 11 shown in FIG. 1. In FIG.
1, 202 is a D-type flip-flop circuit, 211 is an AN
The D circuit and 212 are 3-input AND circuits.

In the 3-state sequential circuit 11 shown in FIG.
When "0" is input following "0" as the discrimination signal (2f), the outputs of the AND circuits 211 and 212 are Low, the output of the 3-state sequential circuit 11 is "0", and
The Q-bar output of the D-type flip-flop circuit 201 is High.
becomes h.

Next, when "1" is input following "0", the AND circuit 211 becomes High because the Q-bar output (High) of the D-type flip-flop circuit 201 is input to the other. However, the D-type flip-flop circuit 20
Since 1 maintains the state of 1 clock before, Q output is L
The ow and Q bar outputs remain High, and the AND circuit 212 maintains the Low state.

Next, when "1" is input following "0" and "1", the Q output of the D-type flip-flop circuit 201 becomes High, the Q bar output becomes Low, and the AND circuit 211 becomes Low. Further, the D-type flip-flop circuit 20
Since the Q bar output of 2 is High, the AND circuit 21
2 becomes High, and the 3-state sequential circuit 11 outputs "1".

Next, "0", "1", and "1" are followed by "
When 1 ″ is input, the D-type flip-flop circuit 201
, The Q output of the D-type flip-flop circuit 202 is Low, and the AND circuit 211 is High.
become ow.

In the first embodiment, the recording signal (2b) is a digital signal in which the minimum number of consecutive "0" symbols between two "1" symbols is 1, but it is continuous.
PR equalizer 8 if the minimum number of 0 "symbols is 1 or more
At "1" and "-1" of the reproduction signal (2d) are not added to become "0", the data discrimination circuit 10 and the three-state sequential circuit 11 operate similarly.

Therefore, in the first embodiment, the continuous "0".
It is clear that the minimum number of symbols is applicable to more than one recorded signal.

According to the first embodiment, the partial response class IV can be realized without using a precoder on the recording side, and the PR system which is not yet adopted in the standard can be used even in the VTR and the computer MT which require medium compatibility. There is an effect.

(Embodiment 2) FIG. 5 is a diagram showing a schematic configuration of a digital signal recording / reproducing apparatus which is another embodiment (Embodiment 2) of the present invention.

In FIG. 5, 1 is a recording signal input terminal, 2
Is an NRZI encoding circuit, 3 is a 1-bit delay element, 4 is an adder (modulo 2 adder), 5 is a magnetic recording / reproducing system, 6
a and 6b are magnetic heads, 7 is a magnetic medium, 41 is a PR equalizer, 10 is a data discriminating circuit, and 42 is a (n + 2) state sequential circuit.

FIG. 6 is a diagram showing an example of a time chart of the digital signal recording / reproducing circuit shown in FIG.

In FIG. 6, (5a) is a clock and (5a)
b) is a recording signal input from the recording signal input terminal 1,
(5c) is the NRZ output from the NRZI encoding circuit 2.
I signal, (5d) reproduced signal reproduced from the magnetic medium 7 by the magnetic head 6b, (5e) equalized signal output from the PR equalizer 41, (5f) data discrimination circuit 10
(5g) is an output signal of the (n + 2) state sequential circuit 42.

In FIG. 6, the time is discontinuous in the wavy line portion.

The operation of the second embodiment will be described below with reference to FIGS. 5 and 6.

The recording signal (5b) inputted from the recording signal input terminal 1 is continuous between two "1" symbols.
It is assumed that the minimum number of 0 "symbols is a digital signal of d.

The process from the input of the recording signal (5b) to the recording signal input terminal 1 to the reproduction of the reproduction signal (5d) by the magnetic head 6b is the same as that of the first embodiment.

Therefore, the recording signal (5b) is "1".
Corresponds to "1" or "-1" of the reproduction signal (5d).

The reproduction signal (5d) is input to the PR equalizer 41.

The PR equalizer 41 is a PR having a (1 + D) response characteristic composed of the 1-bit delay element 3 and the adder 9.
The equalizer 8 is connected in n stages in series.

However, n is an integer satisfying 1 ≦ n ≦ d.

The response characteristic of the entire PR equalizer 41 is (1+
D) ** n, and since the response characteristic combined with the recording / reproducing system 5 is (1-D) (1 + D) ** n, it is a partial response class IV channel.

The response characteristic of the PR equalizer 41 is (1 + D) *
Since it is * n, "1" or "-" of the reproduction signal (5d)
The signal value k bits after 1 ”is input is a binomial constant nCk (the number of combinations for selecting k from n) or −
It becomes nCk.

The maximum delay in the PR equalizer 41 is n bits.

Here, since "1" of the reproduction signal (5e) is input until the next "-1" is input, there are more than d bits, and n satisfies 1≤n≤d. Signal (5
Only the signal obtained by delaying d) and "0" of the reproduction signal (5d) are not added.

From this, "1" of the recording signal (5b) is
The equalized signal (5e) becomes a (n + 1) -bit continuous signal, and the signal value of the k-th bit is "nCk" or "-n".
It becomes Ck ”.

The equalization signal (5e) is supplied to the data discrimination circuit 10
Is input to The data discrimination circuit 10 is the same as that in the first embodiment.

Therefore, the recording signal (5b) is "1".
Is "1" of (n + 1) consecutive bits of the discrimination signal (5f)
become.

The discrimination signal (5f) is input to the (n + 2) state sequential circuit 42.

The (n + 2) state sequential circuit 42 is a circuit for obtaining the recording signal (5b) from the discrimination signal (5f).

Since "1" of the recording signal (5b) corresponds to "1" of (n + 1) consecutive bits of the discrimination signal (5f), the (n + 2) state sequential circuit 42 discriminates the discrimination signal (5).
If "1" of (n + 1) -bit continuous is detected in f),
It is sufficient to output 1 ".

FIG. 7 is a state transition diagram showing the operation of the (n + 2) state sequential circuit 42 shown in FIG.

S0 is the initial state, S1 is the discrimination signal (5f).
In the state where the first "1" is detected from, Sk is the discrimination signal (5
The state in which "1" of consecutive k bits is detected from f), Sn +
1 is a "n + 1" continuous bit from the discrimination signal (5f) "
This is a state in which "1" is detected.

A signal (5g) delayed by n clocks from the recording signal (5b) is obtained by outputting "1" at the time of transition from the state Sn to the state Sn + 1 and outputting "0" at other times. .

FIG. 8 is a diagram showing an example of the circuit configuration of the (n + 2) state sequential circuit 42 shown in FIG. 5. In FIG. 8, 301 is (n + 1) D-type flip-flop circuits, and 311 is (n + 1). ) Input AND circuit 312 is an (n + 2) input AND circuit.

The (n + 2) state sequential circuit 42 shown in FIG.
Similarly to the three-state sequential circuit 11 shown in FIG. 4, when the "1" of (n + 1) consecutive bits is detected in the discrimination signal (5f), "1" is output.

The (n + 2) state sequential circuit 42 shown in FIG. 8 is a generalized circuit diagram and is not necessarily optimum in terms of circuit scale.

According to the second embodiment, the optimum n can be selected from n satisfying 1 ≦ n ≦ d according to the actual recording / reproducing system conditions such as the linear recording density. The N ratio can be further improved.

Further, the data discriminating circuit for multilevel signals need only have two threshold values, and has an effect that it can be realized by a simpler circuit than the data discriminating circuit of partial response class IV using a general precoder.

(Embodiment 3) FIG. 9 is a diagram showing a schematic configuration of a digital signal recording / reproducing apparatus which is another embodiment (Embodiment 3) of the present invention.

In FIG. 9, 1 is a recording signal input terminal, 2
Is an NRZI encoding circuit, 3 is a 1-bit delay element, 4 is an adder (modulo 2 adder), 5 is a magnetic recording / reproducing system, 6
a and 6b are magnetic heads, 7 is a magnetic medium, 41 is a PR equalizer, 10 is a data discrimination circuit, and 81 is error propagation prevention (n +).
2) State sequential circuit.

FIG. 10 shows the error propagation prevention (n +) shown in FIG.
2) A state transition diagram showing the operation of the state sequential circuit 81.

The operation of the third embodiment will be described below with reference to FIGS. 9 and 10.

In FIG. 9, the operation from the input of the recording signal to the recording signal input terminal 1 to the output of the discrimination signal from the data discrimination circuit 10 is exactly the same as that in the second embodiment.

Therefore, "1" of the recording signal corresponds to "1" of (n + 1) consecutive bits of the discrimination signal.

The state transition diagram of the (n + 2) state sequential circuit 42 in the second embodiment is as shown in FIG.

In the state transition diagram shown in FIG. 7, when "1" is once detected in the input signal, it is expected that (n + 1) bit "1" will continue, and "0" is input from state S1 to state Sn. Transition path does not exist.

However, an error may actually occur in the recording / reproducing system and "0" may be input which is not expected.

Therefore, the transition path can be determined in consideration of the case where an error occurs.

As shown in FIG. 7, the "0" input is predicted to be in two states S0 and Sn + 1, and in any case, the state is transited to the state S0.

Therefore, the error propagation prevention (n
+2) The operation of the state sequential circuit 81 is determined as shown in the state transition diagram of FIG.

By doing so, it is possible to immediately shift to the normal state S0 by the input of "0" which is not an error.

Therefore, if a recording signal having a pattern such that "0" is input to the error propagation prevention (n + 2) state sequential circuit 81 is prepared, even if an error occurs,
By inputting 0 ”, it is possible to make a transition to a normal state and never propagate an error infinitely.

On the contrary, a bit which is "1" is set to "1" due to an error.
If it is discriminated as "0", the state transits to the wrong state S0.

However, the data discriminating circuit 10 discriminates from "0" that the signal value of the input signal is the threshold value T-(-1 <T-.
This is the case where it is larger than <0) and smaller than the threshold value T + (0 <T + <1), and it is unlikely that the signal value ± nCk is lowered to this level due to an error.

11 and 12 are diagrams showing an example of the circuit configuration of the error propagation prevention (n + 2) state sequential circuit 81 shown in FIG.

FIG. 11 is a diagram showing an example of the error propagation preventing three-state sequential circuit corresponding to FIG. 4, and
FIG. 12 is a diagram showing an example of the circuit configuration of the error propagation prevention (n + 2) state sequential circuit corresponding to FIG.

The error propagation prevention (n + 2) state sequential circuit shown in FIGS. 11 and 12 is an AND circuit 401 in which the other terminal is connected to the input of the (n + 2) state sequential circuit shown in FIGS. 4 and 8. Is added, and when "0" is input, the state immediately transits to the normal state S0.

According to the third embodiment, it is possible to realize a partial response class IV channel which can prevent the error from propagating infinitely and which does not use a precoder.

(Embodiment 4) FIG. 13 is a block diagram of a digital signal recording / reproducing apparatus which is another embodiment (Embodiment 4) of the present invention.

In FIG. 13, 1 is a recording signal input terminal,
2 is an NRZI encoding circuit, 3 is a 1-bit delay element, 4 is an adder (modulo 2 adder), 5 is a magnetic recording / reproducing system,
6a and 6b are magnetic heads, 7 is a magnetic medium, 41 is a PR equalizer, 131 is a ternary discrimination circuit, and 132 is a (2n + 3) state sequential circuit.

FIG. 14 is a state transition diagram showing an operation of the (2n + 3) state sequential circuit 132 shown in FIG.

FIG. 15 is a diagram showing an example of a time chart of the digital signal recording / reproducing circuit shown in FIG.

In FIG. 15, (16a) is a clock,
(16b) is a recording signal input from the recording signal input terminal 1, (16c) is an NRZI signal output from the NRZI encoding circuit 2, (16d) is a reproduction signal reproduced from the magnetic medium 7 by the magnetic head 6b, (16e) is an equalization signal output from the PR equalizer 41, (16f) is a ternary discrimination signal output from the ternary discrimination circuit 131, (16g)
Is an output signal of the (2n + 3) state sequential circuit 132.

Further, (16h) is a ternary discrimination signal output from the ternary discrimination circuit 131 when an error occurs, (16h)
i) is a (2n + 3) state sequential circuit 1 when an error occurs
32 output signal.

The operation of the fourth embodiment will be described below with reference to FIGS. 13, 14 and 15.

In the second embodiment, error propagation may occur depending on the pattern of the recording signal. This will be described with reference to FIG.

FIG. 16 is a diagram showing an example of a time chart of the digital signal recording / reproducing circuit shown in FIG.

In FIG. 16, (14a) is a clock,
(14b) is a recording signal input from the recording signal input terminal 1, (14c) is an NRZI signal output from the NRZI encoding circuit 2, (14d) is a reproduction signal reproduced from the magnetic medium 7 by the magnetic head 6b, (14e) is an equalization signal output from the PR equalizer 41, (14f) is a discrimination signal output from the data discrimination circuit 10, and (14g) is an output signal of the (n + 2) state sequential circuit 42. .

Further, (14h) is a discrimination signal output from the data discrimination circuit 10 when an error occurs, (14i)
Is the output signal of the (n + 2) state sequential circuit 42 when an error occurs.

In the recording signal (14b), "1" appears in the (n + 1) -bit cycle, and the rest is "0".

In this case, the discrimination signal (14f) is always "
1 "signal.

Here, it is assumed that an error occurs due to noise or the like, and a certain 1 bit is discriminated from "1" as "0", resulting in (14h).

This signal is the (n + 1) state sequential circuit 42.
, The state transition starts with a delay of 1 bit, and the output signal (14i) continues to be delayed by 1 bit from the correct output signal (14g).

In this error propagation, the discrimination signal (14h) is "
It will continue as long as it is 1 ".

In FIG. 13, the operation from the input of the recording signal (16a) to the recording signal input terminal 1 to the output of the equalization signal (16e) from the PR equalizer 41 is the same as in the second embodiment. Exactly the same.

The equalized signal (16e) is supplied to the three-value discrimination circuit 13
Input to 1.

The ternary discrimination circuit 131 has a threshold value T + having a value between 0 and 1 and a threshold value T- having a value between 0 and -1, and the signal value of the input signal is not less than T +. If "1",
If it is less than T-, "-1" is output, and if it is larger than T- and smaller than T +, "0" is output.

This output signal is "0" or "1" or "-".
It is a ternary digital signal of "1".

The three-value discrimination circuit 131 obtains a three-value discrimination signal (16f).

The three-value discrimination signal (16f) is (2n + 3)
It is input to the state sequential circuit 132.

The (2n + 3) state sequential circuit 132 is shown in FIG.
This circuit operates in accordance with the state transition diagram of FIG. 4 and outputs 1-bit "1" when detecting "1" of (n + 1) -bit continuous or "-1" of (n + 1) -bit continuous.

An output signal (16g) is obtained by the (2n + 3) state sequential circuit 132.

Here, it is assumed that an error occurs due to noise or the like and 1-bit "1" is discriminated as "0", resulting in (16h).

This signal corresponds to the (2n + 1) state sequential circuit 1
When it is input to 32, the state transition starts with a delay of 1 bit, and transitions to state Sn by detecting "1" of consecutive n bits, but since "-1" is input next, it transits to state Sn + 2. , The output signal becomes "0".

After that, "-" of (n + 1) consecutive bits
"1" is detected and the state transits to S2n + 2, and the output signal is "
1 "will be output.

The output signal (16i) is the correct output signal (1
6g) and "1" of (n + 1) consecutive bits in which an error occurred
Or they match except for the period of "-1".

According to the fourth embodiment, the recording signal has (n +
1) It is possible to prevent error propagation even when a signal in which "1" appears in the bit cycle is input.

(Embodiment 5) FIG. 17 is a diagram showing a schematic configuration of a digital signal recording / reproducing apparatus which is another embodiment (Embodiment 5) of the present invention.

In FIG. 17, 1 is a recording signal input terminal,
2 is an NRZI encoding circuit, 3 is a 1-bit delay element, 4 is an adder (modulo 2 adder), 5 is a magnetic recording / reproducing system,
6a and 6b are magnetic heads, 7 is a magnetic medium, 41 is a PR equalizer, and 101 is a maximum likelihood decoding circuit.

FIG. 18 shows the maximum likelihood decoding circuit 10 shown in FIG.
3 is a state transition diagram showing the operation of No. 1 in FIG.

The operation of the fifth embodiment will be described below with reference to FIGS. 17 and 18.

In FIG. 17, the operation from the input of the recording signal to the recording signal input terminal 1 to the output of the equalized signal from the PR equalizer 41 is exactly the same as that in the second embodiment.

Therefore, "1" of the recording signal becomes a signal of (n + 1) -bit continuous of the equalization signal, and the signal value of the k-th bit becomes "nCk" or "-nCk".

This equalized signal is input to the maximum likelihood decoding circuit 101.

The maximum likelihood decoding circuit 101 performs data discrimination of the equalized signal and decoding into a recording code at the same time based on the maximum likelihood decoding method.

The maximum likelihood decoding method is generally called the Viterbi decoding method. This method is described, for example, in "Digital Video Recording Technology" by Yoshizumi Eto et al. (August 1990, published by Nikkan Kogyo Shimbun, page 75). To page 84).

By applying the maximum likelihood decoding method, in addition to the effect of the partial response channel, S / N
The ratio can be improved.

The inputs shown in the state transition diagram of FIG. 18 are ideal values.

The maximum likelihood decoding method selects a transition path that minimizes the accumulation (metric) of the error between the ideal value and the actual signal value.

Therefore, even if an error occurs in the recording / reproducing system 5, the metric after that is large in the wrong transition path, so that the correct transition path is eventually selected.

However, in the maximum likelihood decoding method, in general, if an incorrect transition path is selected for some reason, the error may propagate infinitely, so that decoding refresh is necessary.

In the case of a general partial response class IV (n ≧ 1) using a precoder, the number of states is 2 **
Since there are (n + 1) number of transition paths from one state to at least two states, a large number of metric operation circuits and memories for storing the metric are required, resulting in an enormous circuit scale. there were.

In the fifth embodiment, since the number of states is (n + 2) and the transition paths exist only between the limited states, the circuit scale of the maximum likelihood decoding circuit 101 is smaller than that of the conventional system. Can be made smaller.

In the fifth embodiment, the state where the equalized signal has a positive signal value and the state where the equalized signal has a negative signal value are degenerated, but of course these may be set in different states.

According to the fifth embodiment, since the maximum likelihood decoding method is applied, further improvement of the S / N ratio can be expected, and more than the general partial response class IV maximum likelihood decoding circuit using the precoder. This has the effect of reducing the circuit scale.

In each of the above embodiments, the minimum number d of consecutive "0" symbols between two "1" symbols is d.
A digital signal of ≧ 1 is NRZI encoded and recorded on a recording medium.

For example, when NRZI coding is performed on a digital signal that follows "1" symbol, "0" symbol, "1" symbol, magnetization reversal occurs every time "1" symbol appears.

In terms of the characteristics of the signal on the recording medium, this means that the minimum magnetization reversal interval is at least twice the shortest recording bit length, and even if the polarity of the signal is reversed, the same signal can be decoded. Is equivalent to

Therefore, it is obvious that the present invention can be applied to the case where the signal on the recording medium satisfies the above property.

Further, in each of the above-mentioned embodiments, the case where the present invention is applied to the magnetic recording / reproducing system 5 has been described, but it is obvious that the present invention is applicable to not only magnetic recording but also optical recording and magneto-optical recording. .

Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention.

[0219]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, the output of the NRZI encoder is directly recorded / reproduced on the recording medium without using a precoder, and the reproduced signal is input to the PR equalizer, and the PR equalizer outputs the signal. Since a specific signal pattern is detected from the output multilevel signal and decoded into a digital signal, the compatibility of the recording medium can be maintained.

As a result, it is possible to apply the PR system, which has not been adopted in the standard, to a magnetic recording / reproducing apparatus such as a VTR or a computer MT which requires recording medium compatibility.

(2) According to the present invention, the data discriminating circuit is only required to discriminate between three types of "1" or more, "0", and "-1" or less, and in the original PR class IV data discriminating circuit. While it is necessary to discriminate (2 ** n + 1) types of signals, it is possible to simplify the circuit configuration of the data discrimination circuit.

(3) According to the present invention, by selecting the value of n, it becomes possible to select the PR system having the optimum response characteristic for the recording / reproducing system.

(4) According to the present invention, since the error propagation preventing sequential circuit is used, it is possible to limit the propagation of the error generated in the recording / reproducing system.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a digital signal recording / reproducing apparatus which is an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a diagram showing an example of a time chart of the digital signal recording / reproducing circuit shown in FIG.

FIG. 3 is a state transition diagram showing an operation of the three-state sequential circuit shown in FIG.

4 is a diagram showing an example of a circuit configuration of a three-state sequential circuit shown in FIG.

FIG. 5 is a diagram showing a schematic configuration of a digital signal recording / reproducing device which is another embodiment (embodiment 2) of the present invention.

6 is a diagram showing an example of a time chart of the digital signal recording / reproducing circuit shown in FIG.

FIG. 7 is a state transition diagram showing an operation of the (n + 2) state sequential circuit shown in FIG.

8 is a diagram showing an example of a circuit configuration of the (n + 2) state sequential circuit shown in FIG.

FIG. 9 is a diagram showing a schematic configuration of a digital signal recording / reproducing apparatus which is another embodiment (Embodiment 3) of the present invention.

10 is a state transition diagram showing an operation of the error propagation prevention (n + 2) state sequential circuit shown in FIG.

11 is a diagram showing an example of a circuit configuration of the error propagation prevention (n + 2) state sequential circuit shown in FIG.

12 is a diagram showing an example of a circuit configuration of an error propagation prevention (n + 2) state sequential circuit shown in FIG.

FIG. 13 is a configuration diagram of a digital signal recording / reproducing apparatus which is another embodiment (Embodiment 4) of the present invention.

14 is a state transition diagram showing an operation of the (2n + 3) state sequential circuit shown in FIG.

15 is a diagram showing an example of a time chart of the digital signal recording / reproducing circuit shown in FIG.

16 is a diagram showing an example of a time chart of the digital signal recording / reproducing circuit shown in FIG.

FIG. 17 is a diagram showing a schematic configuration of a digital signal recording / reproducing apparatus which is another embodiment (embodiment 5) of the present invention.

18 is a state transition diagram showing an operation of the maximum likelihood decoding circuit 101 shown in FIG.

FIG. 19 is a block diagram showing a schematic configuration of a digital signal recording / reproducing apparatus using a conventional partial response class IV.

[Explanation of symbols]

1 ... Recording signal input terminal, 2 ... NRZI encoding circuit, 3 ...
1-bit delay element, 4 ... Modulo-2 adder, 5 ... Magnetic recording / reproducing system, 6a, 6b ... Magnetic head, 7 ... Magnetic medium,
8, 41 ... PR equalizer, 9 ... Adder, 10 ... Data discrimination circuit, 11 ... 3-state sequential circuit, 12 ... Reproduction signal output terminal, 42 ... (n + 2) state sequential circuit, 81 ... Error propagation prevention (n + 2) ) State sequential circuit, 101 ... Maximum likelihood decoding circuit, 1
21 ... Precoder, 131 ... Three-value discrimination circuit, 132 ...
(2n + 3) state sequential circuit, 201, 202, 301,
302 ... D-type flip-flop circuit, 211, 212,
311, 312, 411 ... AND circuits, (2a), (5
a), (14a), (16a) ... Clock, (2b),
(5b), (14b), (16b) ... Recording signals input from recording signal input terminals, (2c), (5c), (14
c), (16c) ... NRZI signal output from NRZI encoding circuit, (2d), (5d), (14d), (1
6d) ... Reproduced signals reproduced from the magnetic medium by the magnetic head, (2e), (5e), (14e), (16e) ...
The equalized signal output from the PR equalizer, (2f), (5
f), (14f), (16f) ... Discrimination signals output from the data discrimination circuit, (2g), (5g), (14g),
(16g) ... Output signal of the sequential circuit.

Claims (10)

[Claims] 1. Consecutive between two "1" symbols
A digital signal whose minimum number of 0 "symbols is d is N
In a digital signal processing method of converting into an RZI code, recording on a recording medium, and decoding the digital signal from a signal reproduced from the recording medium, a frequency characteristic is (1
-D) (1 + D) ** n (where D is a 1-bit delay operator; ** is a power; n is an integer of 1≤n≤d) to obtain a multilevel signal, A digital signal processing method characterized by detecting a specific signal pattern from a multi-valued signal and decoding it into the digital signal. 2. The digital signal processing method according to claim 1, wherein the multi-valued signal subjected to the signal processing is discriminated into a binary signal by a signal value, and the binary signal is specified in the binary signal by sequential logic. A digital signal processing method, characterized in that it is detected that symbols are consecutive (n + 1) bits and is decoded into the digital signal. 3. The digital signal processing method according to claim 1, wherein the multivalued signal subjected to the signal processing is discriminated into a ternary signal according to a signal value, and a specific value is specified in the ternary signal by sequential logic. A digital signal processing method, characterized in that it is detected that symbols are consecutive (n + 1) bits and is decoded into the digital signal. 4. The digital signal processing method according to claim 2, wherein the state transition of the sequential logic for processing the binary signal or the ternary signal is made when an input without a transition path is made. Is a digital signal processing method characterized by immediately transitioning to an initial state. 5. The digital signal processing method according to claim 1, wherein a specific signal pattern is detected from the multi-valued signal subjected to the signal processing by a maximum likelihood decoding method and is decoded into the digital signal. A characteristic digital signal processing method. 6. Consecutive between two "1" symbols
A digital signal whose minimum number of 0 "symbols is d is N
In a digital signal processing device for converting a signal into an RZI code, recording it on a recording medium, and decoding the digital signal from a signal reproduced from the recording medium, a frequency characteristic is (1
-D) (1 + D) ** n (where D is a 1-bit delay operator; ** is a power; n is an integer of 0 ≦ n ≦ d), and a multilevel signal is output. A digital signal processing device comprising: an equalization circuit; and a decoding circuit for detecting a specific signal pattern from a multilevel signal output from the equalization circuit and decoding the signal pattern into the digital signal. 7. The digital signal processing device according to claim 6, wherein the decoding circuit discriminates a multilevel signal output from the equalization circuit into a binary signal according to a signal value, and the discrimination circuit. A specific symbol is (n + 1) in the binary signal output by
A digital signal processing device comprising: a sequential circuit that detects that bits are continuous and decodes the digital signal. 8. The digital signal processing device according to claim 6, wherein the decoding circuit discriminates a multilevel signal output from the equalization circuit into a ternary signal based on a signal value, and the discrimination circuit. A specific symbol is (n + 1) in the ternary signal output by
A digital signal processing device comprising: a sequential circuit that detects that bits are continuous and decodes the digital signal. 9. The digital signal processing device according to claim 7, wherein the state transition of the sequential circuit immediately transits to an initial state when an input without a transition path is made. And a digital signal processing device. 10. The digital signal processing device according to claim 6, wherein the decoding circuit detects a specific signal pattern from a multilevel signal output from the equalization circuit and decodes the digital signal into the digital signal. A digital signal processing device comprising a decoding circuit.