JPH087740B2 - Communication control method of information processing device - Google Patents

Description

The present invention relates to a communication control system of an information processing apparatus, and in particular, whether to execute a command sent by an external processing device in a broad cast. The present invention relates to a communication control system of an information processing device, in which the information processing device that receives this command performs switching according to the state of the processing device.

[Conventional technology]

Send a command from the external control device to the information processing device,
Controlling the information processing device is disclosed in Japanese Patent Application Laid-Open No. 55-9202, "Common Control Method by Service Processor". This conventional technique controls a plurality of information processing devices by transmitting a command from an external processing device to the plurality of information processing devices by a broadcast cast. Therefore, according to this conventional technique, a plurality of information processing devices can be controlled by one command transmission from the external device, and the control load of the external control device can be reduced.

[Problems to be solved by the invention]

However, in the above-mentioned conventional technique, a command broadcast in a case where an information processing apparatus in a command executable state and an information processing apparatus in a command unexecutable state coexist in a plurality of information processing apparatuses. No consideration has been given to sending by.

The above-mentioned information processing apparatus in the command unexecutable state is, for example, an information processing apparatus in which the command receiving unit is normal and the command execution unit is in an obstacle to perform normal processing.

In the above-mentioned conventional technology, in order to start processing only in the information processing apparatus in the normally stopped state of the information processing apparatus in which the information processing apparatus having such a failure and the information processing apparatus in the normally stopped state are mixed. In addition, when the external processing device broadcasts the processing start command, the processing device in failure receives the start command and passes the command to the command execution unit. However, there was a problem that this command was executed and the processing could not be performed correctly.

An object of the present invention is to send a broadcast only to an information processing apparatus in a command executable state in the case where an information processing apparatus in a command executable state and an information processing apparatus in a command unexecutable state coexist. An object of the present invention is to provide a communication control system of an information processing device that enables control of a plurality of information processing devices so that commands can be executed.

[Means for solving problems]

According to the present invention, when the external processing device causes the information processing device to perform command processing, the external processing device is
Information indicating the command executable state of the information processing device is simultaneously broadcast and transmitted to all information processing devices,
Each information processing device compares the information indicating the command executable state received by the command accepting part with the state of its own information processing device which is the output from the state identifying part, and only when the states match, the command executing part This is accomplished by executing the command.

[Work]

When transmitting a command to be processed by the information processing device to the information processing device by the broadcast cast, the external processing device notifies each information processing device of a processing class indicating a command executability condition of the information processing device. Each information processing device compares the command executability condition with the state of its own device, and if the condition is satisfied, the command valid state is set, and if the condition is not satisfied, the command invalid state is set. When the external processing device issues a command to each information processing device by the broadcast cast, the information processing device in the command valid state executes the received command, and the information processing device in the command invalid state ignores the command. Do not execute.

With such an operation, the external processing device can substantially transmit the command by the broadcast cast only to the information processing device that satisfies the command executable condition.

〔Example〕

Hereinafter, a communication control system of an information processing apparatus according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a command receiving circuit in the information processing apparatus, FIG. 2 is a system configuration diagram showing the overall configuration of an embodiment of the present invention, and FIG. 3 is a connection command code in the command receiving circuit. FIG. 4 is a bit allocation diagram of the status register in the command receiving circuit. In FIGS. 1 and 2, 1 is a service processor (SVP) bus, 2 is a service processor (SVP) as an external processing device, 10 to 12 are information processing devices, 31 is a command register, and 32 is a parameter register. , 33 is a status register, 41 is a command decoder, 131 is a command valid flip-flop, 200 is a command receiving circuit, and 300 is
It is the CPU body.

As shown in FIG. 2, in the communication control system of the information processing apparatus according to the present invention, a plurality of information processing apparatuses 10 to 12 have a service processor (SVP) 2 as an external processing apparatus and an SVP bus 1.
It is configured to be connected via. The SVP2 controls the maintenance and diagnosis of each information processing device 10-12. The information processing devices 10 to 12 are
All have the same configuration, and the configuration of the command receiving circuit 200 in the information processing device 10 is shown in FIG. Information processing device 1
0 is composed of a CPU main body unit 300 which is a command executing unit and a command receiving circuit 200 which is a command receiving unit,
The command receiving circuit 200 uses the SVP bus 1 via the internal bus 21.
Connected with. The command receiving circuit 200 stores an 8-bit command register (CMD) 31 and an 8-bit parameter register (PARM) that accumulates a command issued by the SVP2 and information indicating a command executability state, which is a parameter indicating a command executability condition. 32, status of CPU body 300, that is, 8-bit status register (STS) 33 for storing status of own information processing device, command decoder 41, AND gate 91 for comparing parameter and status
~ 93, OR gate 101 of the output signals of the AND gates 91-93,
The AND gates 121 and 12 which determine whether the command is valid or not are determined by the output signal 111 of the OR gate 101 and the connection command signal 52.
2, a flip-flop 131 indicating a command valid state, an output signal 141 of the flip-flop 131 and a command decoder 41
And AND gates 61 to 63 that take a logical product with the output signal group 51 of.

In the command receiving circuit 200 in the information processing apparatus 10 thus configured, the command register 31 and the parameter register 32 receive and store the contents via the SVP bus 1 when the SVP2 issues a command. The contents of the command register 31 are decoded by the command decoder 41, and in the case of a command other than the connection command, the output signal group 51
One of the signals becomes High, and in case of connection command,
The connection command signal 52 goes high. The state of the CPU body 300 is given to the status register 33 as a signal group 310 and held therein. The contents of the parameter register 32 and the contents of the status register 33 are input to the AND gates 91 to 93 as signals 71 to 73 and signals 81 to 83, respectively, corresponding to the bits.
The AND output is input to the OR gate 101. The output signal 111 of the OR gate 101 becomes High when at least one bit in the status register 33 corresponding to the bit set in the parameter register 32 is High. OR gate 10
The inverted signal of the output signal 111 of 1 and the connection command signal 52 of the decoder 41 are input to the AND gate 121, and the output thereof is input to the set terminal S of the flip-flop 131 indicating the command valid state. The positive signal of the signal 111 and the connection command signal 52 are input to the AND gate 122, and the output thereof is input to the reset terminal of the flip-flop 131. Therefore, when the connection command signal 52 is High, that is, when the connection command is issued, if none of the status bits corresponding to the bit indicated by the parameter is High, the flip-flop 131 is set and the command valid state is set. If any one of the status bits corresponding to the bit indicated by the parameter is High, the flip-flop 131 is reset and indicates the command invalid state. The output signal 141 of the flip-flop 131 is supplied to each bit of the output signal group 51 of the command decoder 41 and the AND gate 61.
To 63, the AND output signal group 210 is input to the CPU main body section 300 together with the output signal group 220 of the parameter register 32. The output signal group 51 of the command decoder 41 is input to the CPU main body section 300 as the signal group 210 via the AND gates 61 to 63 only when the flip-flop 131 indicates the command valid state and the output signal 141 thereof is High. It
That is, the information processing apparatus in the same state as the state specified by the parameter by the connection command from SVP2 becomes the command invalid state, and does not execute the command until the next connection command is issued from SVP2. Further, the information processing apparatus in a state different from the state designated by the parameter by the connection command from the SVP enters the command valid state and can execute subsequent commands.

FIG. 3 shows the code assignment of the connection command, and the connection command code is (FF) ₁₆ . As for the parameter, each bit corresponds to each bit of the status register 33. If the bit of the parameter is "0", it does not work, but if it is "1", the bit of the status register 33 corresponding to that bit is If it is "1", flip-flop 131
Output signal 141 of "0" and through AND gates 61-63,
Prevents subsequent commands from being input to the CPU, and sets the information processing device to the command invalid state. This can be expressed by the following equation when expressed by a logical expression based on the parameter bit and the status bit.

However, CMDENB: Valid state of the command PARM (0) to 7: Bits 0 to 7 of parameters STS (0) to 7: Bits 0 to 7 of status FIG. 4 shows the contents of the bits of the status register 33. 0 indicates “1” when the information processing device 10 is disconnected from the system, and bit 1 indicates the information processing device.
It becomes "1" when 10 is in the failure status. Bit 2 becomes "1" when the information processing device 10 is in the maintenance state, and bit 3
Is “1” when the information processing device 10 is in the stopped state. Bits 4-7 are inverted signals of bits 0-3.

Next, an actual command procedure for simultaneously controlling a plurality of information processing devices 10 to 12 from SVP2 will be described. The condition of the information processing device that can be controlled by the SVP is that the information processing device is connected to the system and is not in a failure state.

First, the SVP2 issues a connection command (FF) ₁₆ with (CO) ₁₆ as a parameter indicating the command executable condition.
Upon receiving this connection command, the command receiving circuit 200 of each information processing device, the bit 0 of the status register 33,
When 1 is "1", the information processing apparatus is set to the command invalid state, and when bits 0 and 1 of the status register are "0", the information processing apparatus is set to the command valid state. That is, only the information processing apparatus that is connected to the system and is not in the failure state is in the valid state, and the information processing apparatus that is not connected to the system or is in the failure state is in the command invalid state.

Next, SVP2 issues a start command. The information processing apparatus which is in the command valid state by the above-mentioned connection command accepts and starts this command.

In the above-described embodiment of the present invention, the communication path indicating the command execution condition is also used as the command communication path, but a dedicated communication path indicating the command executability condition may be separately provided. In this case, although the amount of hardware increases, the notification of the command executability condition from the SVP2 and the issuing of the processing command can be performed in parallel, so the processing time can be shortened.

〔The invention's effect〕

As described above, according to the present invention, an external processing device can issue a command by a broadcast cast only to an information processing device that satisfies a command executable condition. Since the processing can be executed at one time, the time required for the processing can be shortened. Further, since the external processing device can execute the command processing in the same procedure regardless of the number of information processing devices to be controlled, the procedure for instructing the processing can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of a command receiving circuit of an embodiment of the present invention, FIG. 2 is a system configuration diagram of an embodiment of the present invention, FIG. 3 is a code explanation diagram of a connection command, and FIG. 4 is a status register. FIG. 1 …… SVP Bus, 2 …… Service Processor (SVP), 10
~ 12 …… Information processing device, 31 …… Command register, 32…
… Parameter register, 33… Status register, 41
...... Command decoder, 131 …… Command valid flip-flop, 200 …… Command receiving circuit, 300 …… CPU main unit.

Claims (1)

[Claims] 1. An external processing device, a command receiving unit from the external processing device, a status identification unit of the own information processing device, and
In a communication control method of an information processing device, which is configured by connecting a plurality of information processing devices having a command execution unit through a communication path, when the external processing device causes the information processing device to perform command processing, The information indicating the command-executable state of the device is simultaneously broadcast and transmitted to all information processing devices, and each information processing device receives information indicating the command-executable state received by the command accepting unit and the information from the state identifying unit. A communication control method for an information processing apparatus, wherein the command execution unit executes a command only when the output status of the information processing apparatus is compared with each other.