JPH0877282A - Analog arithmetic circuit - Google Patents

Analog arithmetic circuit

Info

Publication number
JPH0877282A
JPH0877282A JP21567794A JP21567794A JPH0877282A JP H0877282 A JPH0877282 A JP H0877282A JP 21567794 A JP21567794 A JP 21567794A JP 21567794 A JP21567794 A JP 21567794A JP H0877282 A JPH0877282 A JP H0877282A
Authority
JP
Japan
Prior art keywords
output
bit
converter
voltage
receives
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP21567794A
Other languages
Japanese (ja)
Inventor
Fumio Sakata
文男 坂田
Shinichi Endo
真一 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RADIC KK
Sakata Denki Co Ltd
Original Assignee
RADIC KK
Sakata Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RADIC KK, Sakata Denki Co Ltd filed Critical RADIC KK
Priority to JP21567794A priority Critical patent/JPH0877282A/en
Publication of JPH0877282A publication Critical patent/JPH0877282A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE: To provide the inexpensive, high-performance analog arithmetic circuit which does not require highly precise components. CONSTITUTION: This circuit consists of a 1st 1-bit D/A converter 11 which receives a DC voltage as the denominator of correction arithmetic, a subtracter 12 which receives the output of the 1-bit D/A converter 11 and a reference voltage and performs subtraction, an integrator 13 which receives and integrates the output of the subtracter 12, a comparator 14 which receives the output of the integrator 13 and decides the polarity, and a 2nd 1-bit D/A converter 15 which receives a DC voltage as the numerator of the correction arithmetic; and the output of the comparator 14 is used as a switching signal for the 1st and 2nd 1-bit D/A converters 11 and 15. The output of the 2nd 1-bit D/A converter 15 is used as a correction arithmetic output. Therefore, there is no place to be adjusted, so good precision and superior stability are obtained and neither special components nor severe selecting operation is required.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は差動トランスの検出信号
を補正するためのアナログ演算回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog arithmetic circuit for correcting a detection signal of a differential transformer.

【0002】[0002]

【従来の技術】差動トランスの信号検出回路は、差動ト
ランスにおけるコアの位置変位を電気信号に変換して取
り出す回路であり、その一例を図5を参照して説明す
る。図5において、差動トランス40の一次側に発振回
路41を接続し、2次側の両端にはそれぞれ、加算回路
42,減算回路43を接続している。加算回路42は、
差動トランス40のコア41の位置変位に応じて変化す
る2次側の電圧Va と電圧Vb とを加算し、減算回路4
3は電圧Va と電圧Vb との減算を行う。加算回路4
2,減算回路43にはそれぞれ、同期整流回路44,4
5が接続され、これらの和分信号電圧(Va +Vb ),
差分信号電圧(Va −Vb )がそれぞれ出力される。
2. Description of the Related Art A signal detection circuit of a differential transformer is a circuit for converting a positional displacement of a core in the differential transformer into an electric signal and taking out the electric signal. In FIG. 5, the oscillation circuit 41 is connected to the primary side of the differential transformer 40, and the addition circuit 42 and the subtraction circuit 43 are connected to both ends of the secondary side, respectively. The adder circuit 42
The voltage V a on the secondary side and the voltage V b that change according to the position displacement of the core 41 of the differential transformer 40 are added, and the subtraction circuit 4 is added.
3 subtracts the voltage V a and the voltage V b . Adder circuit 4
2, the subtraction circuit 43 includes synchronous rectification circuits 44 and 4 respectively.
5 is connected, and the summed signal voltage (V a + V b ),
Differential signal voltage (V a -V b) are output.

【0003】ところで、この信号検出回路では、差動ト
ランス40と発振回路41及び差動トランス40と加算
回路42、減算回路43とを接続しているケーブルの長
さや、差動トランス内部の抵抗値が温度等により変化し
た場合に誤差が生ずる。一般に、この誤差要因を補正す
るため、除算回路により差分の信号電圧(Va −Vb
を和分の信号電圧(Va +Vb )にて除算する方式が用
いられている。
By the way, in this signal detecting circuit, the length of the cable connecting the differential transformer 40 and the oscillating circuit 41 and the differential transformer 40, the adding circuit 42 and the subtracting circuit 43, and the resistance value inside the differential transformer. An error occurs when is changed by temperature or the like. Generally, in order to correct this error factor, the signal voltage (V a −V b ) of the difference is calculated by the divider circuit.
Is divided by the summed signal voltage (V a + V b ).

【0004】従来用いられている除算回路の一例を図6
に示す。この除算回路46は、乗算回路51,減算回路
52,増幅回路53から成り、半導体の指数関数特性を
利用したアナログ演算器を用いるものである。
FIG. 6 shows an example of a division circuit conventionally used.
Shown in The division circuit 46 is composed of a multiplication circuit 51, a subtraction circuit 52, and an amplification circuit 53, and uses an analog calculator that utilizes the exponential function characteristic of a semiconductor.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来例では半導体のダイオード順方向電流電圧特性が指数
関数に近似できる事を利用したアナログ演算器を用いて
おり、素子のばらつきによる特性誤差が大きい。このた
め、精度の高いものを得ようとすると、厳密な選定を行
った高価な部品を使用する必要がある。また、調整要素
も多く複雑で、多大な調整時間がかかるという欠点があ
った。
However, in the above-mentioned conventional example, an analog calculator utilizing the fact that the diode forward current-voltage characteristic of a semiconductor can be approximated to an exponential function is used, and the characteristic error due to element variation is large. For this reason, in order to obtain a highly accurate product, it is necessary to use expensive components that have been rigorously selected. In addition, there are many adjustment elements and they are complicated, and there is a drawback that it takes a lot of adjustment time.

【0006】そこで本発明の目的は、前記のような従来
のアナログ演算器の持つ問題を解決し、精度の高い部品
を必要としない安価で高性能なアナログ演算回路を提供
することにある。
Therefore, an object of the present invention is to solve the problems of the conventional analog arithmetic unit as described above and to provide an inexpensive and high-performance analog arithmetic circuit which does not require highly accurate parts.

【0007】[0007]

【課題を解決するための手段】本発明によれば、補正演
算の分母となる直流電圧を受ける第1の1ビットD/A
コンバータと、該1ビットD/Aコンバータの出力と基
準電圧を受けて減算を行う演算器と、該演算器の出力を
受けて積分を行う積分器と、該積分器の出力を受けて極
性判別を行う比較器と、補正演算の分子となる直流電圧
を受ける第2の1ビットD/Aコンバータとからなり、
前記比較器の出力を前記第1及び第2の1ビットD/A
コンバータの切り換え信号として用い、前記第2の1ビ
ットD/Aコンバータの出力を補正演算出力として得る
ことを特徴とするアナログ演算回路が得られる。
According to the present invention, a first 1-bit D / A for receiving a DC voltage serving as a denominator of a correction operation.
A converter, an arithmetic unit that receives the output of the 1-bit D / A converter and a reference voltage to perform subtraction, an integrator that receives the output of the arithmetic unit to perform integration, and a polarity determination that receives the output of the integrator. And a second 1-bit D / A converter that receives a DC voltage that is the numerator of the correction operation,
The output of the comparator is the first and second 1-bit D / A
An analog arithmetic circuit is obtained which is used as a converter switching signal to obtain the output of the second 1-bit D / A converter as a correction arithmetic output.

【0008】[0008]

【作用】本発明回路によるアナログ演算は、内部にデジ
タル信号を用いながら一巡回路内の積分器の効果によ
り、高精度の乗除算アナログ電圧を得る事ができる。ま
た、アナログの非直線性素子を用いていないため、特性
変化要因が少なく時間,温度等に対する安定性に優れた
演算が可能である。
In the analog operation by the circuit of the present invention, a highly accurate multiplication / division analog voltage can be obtained by the effect of the integrator in the loop circuit while using the digital signal internally. Further, since no analog non-linear element is used, it is possible to perform calculation with excellent stability with respect to time, temperature, etc., with few characteristic change factors.

【0009】[0009]

【実施例】次に、本発明の実施例を図面を参照して詳細
に説明する。図1を参照して、本発明によるアナログ演
算回路は、補正演算の分母となる入力信号電圧VB を受
ける第1の1ビットD/Aコンバータ11と、この1ビ
ットD/Aコンバータ11の出力V1 と基準電圧として
の入力信号電圧VA とを受けて減算を行う減算器12
と、この減算器12の出力V2 を受けて積分を行う積分
器13と、この積分器13の出力を受けて極性判別を行
う比較器14とから成る一巡回路10と、補正演算の分
子となる入力信号電圧VC を受ける第2の1ビットD/
Aコンバータ15とを有している。なお、入力信号電圧
A ,VB ,VC はいずれも直流電圧である。
Embodiments of the present invention will now be described in detail with reference to the drawings. With reference to FIG. 1, an analog operation circuit according to the present invention includes a first 1-bit D / A converter 11 that receives an input signal voltage V B that is a denominator of a correction operation, and an output of the 1-bit D / A converter 11. Subtractor 12 that receives V 1 and the input signal voltage V A as the reference voltage to perform subtraction
, A circuit 10 including an integrator 13 that receives the output V 2 of the subtractor 12 and performs integration, and a comparator 14 that receives the output of the integrator 13 to determine the polarity, and the numerator of the correction operation. Second 1-bit D / which receives the input signal voltage V C
It has an A converter 15. The input signal voltages V A , V B and V C are all DC voltages.

【0010】一般に、D/Aコンバータの出力は、基準
電圧としてのアナログ電圧入力とデジタル入力の積にな
る事は周知の通りである。図1の回路に、入力信号電圧
A,VB ,VC を加えた場合の各部波形は、図2に示
す様になる。すなわち、入力信号電圧VB が加わった1
ビットD/Aコンバータ11の出力V1 は、図2(a)
の比較器14のデジタル出力Dによって入力信号電圧V
B を正、負に振ることにより、図2(b)の様に時間T
2 において符号が反転する。これに負の入力信号電圧V
A を加えた減算器12の出力V2 の波形は、図2(c)
の様になる。
It is well known that the output of a D / A converter is generally the product of an analog voltage input as a reference voltage and a digital input. The waveform of each part when the input signal voltages V A , V B and V C are applied to the circuit of FIG. 1 is as shown in FIG. That is, 1 to which the input signal voltage V B is added
The output V 1 of the bit D / A converter 11 is shown in FIG.
Of the input signal voltage V by the digital output D of the comparator 14 of
By swinging B positively or negatively, the time T is changed as shown in Fig. 2 (b).
The sign is reversed at 2 . Negative input signal voltage V
The waveform of the output V 2 of the subtractor 12 to which A is added is shown in FIG.
It becomes like.

【0011】積分器13により出力V2 の平均電圧は0
(V)となるため、下式を得る。
The average voltage of the output V 2 is 0 by the integrator 13.
(V), the following equation is obtained.

【0012】 (VB −VA )×T1 −(VB +VA )×T2 =0 変形すると、 VB ×(T1 −T2 )=VA ×(T1 +T2 ) よって、下式を得る。(V B −V A ) × T 1 − (V B + V A ) × T 2 = 0 When deformed, V B × (T 1 −T 2 ) = V A × (T 1 + T 2 ) Therefore, Get the following formula.

【0013】 VA =VB ・(T1 −T2 )/(T1 +T2 ) 一方、デジタル出力DをT1 ,T2 を用いて下式のよ
うに表現する。
V A = V B · (T 1 −T 2 ) / (T 1 + T 2 ) On the other hand, the digital output D is represented by the following equation using T 1 and T 2 .

【0014】D=(T1 −T2 )/(T1 +T2 ) 上記式と式より下式を得る。D = (T 1 -T 2 ) / (T 1 + T 2 ) The following equation is obtained from the above equation and the equation.

【0015】VA =D×VB 変形すると下式となる。V A = D × V B When transformed, the following equation is obtained.

【0016】D=VA /VB 入力信号電圧VC を1ビットD/Aコンバータ15に通
した出力電圧VE は、入力信号電圧VC をデジタル出力
Dによって正、負に振ることにより、VE =D×VC
表され、式より次式を得る。このように、比較器14
のデジタル出力Dは、1ビットD/Aコンバータ11、
15の切り換え信号として作用する。
D = V A / V B The output voltage V E obtained by passing the input signal voltage V C through the 1-bit D / A converter 15 is obtained by swinging the input signal voltage V C positively or negatively by the digital output D. It is represented by V E = D × V C , and the following formula is obtained from the formula. In this way, the comparator 14
Digital output D of the 1-bit D / A converter 11,
Acts as a 15 switching signal.

【0017】VE =VC ・VA /VB つまり、出力電圧VE はVA とVC 間を乗算し、これを
B で除算した値が得られる。
V E = V C · V A / V B That is, the output voltage V E is obtained by multiplying between V A and V C and dividing it by V B.

【0018】図3に本発明による演算回路を差動トラン
ス信号検出回路に適用した場合の回路を示す。差動トラ
ンス信号検出回路10から出力される和信号である入力
信号電圧VB (=Va +Vb )の極性は常に正であるた
め、図1の1ビットD/Aコンバータ11,15はそれ
ぞれ、アナログスイッチ31,35により置き換えが可
能である。基準電圧発生器37からの基準電圧VA は負
電圧である。また、入力信号電圧VC は直流電圧である
が、アナログスイッチ35により脈流になっているの
で、このリップル分を除去するために低域通過フィルタ
ー36が用いられている。
FIG. 3 shows a circuit when the arithmetic circuit according to the present invention is applied to a differential transformer signal detection circuit. Since the polarity of the input signal voltage V B (= V a + V b ) which is the sum signal output from the differential transformer signal detection circuit 10 is always positive, the 1-bit D / A converters 11 and 15 of FIG. , And can be replaced by the analog switches 31 and 35. The reference voltage V A from the reference voltage generator 37 is a negative voltage. Further, the input signal voltage V C is a DC voltage, but since it has a pulsating flow due to the analog switch 35, a low pass filter 36 is used to remove this ripple component.

【0019】低域通過フィルター36の出力Vo は、前
出の説明によって、下式となる。
The output V o of the low-pass filter 36 is given by the following expression according to the above description.

【0020】 Vo =K・(Va −Vb )/(Va +Vb ) ここで、Kは任意の定数であり、前出の入力信号電圧V
A に対応する。
V o = K · (V a −V b ) / (V a + V b ), where K is an arbitrary constant and the above-mentioned input signal voltage V
Corresponds to A.

【0021】図1の減算器12は入力信号電圧VA ,V
B 間の極性が反対ならば、加算器32に置き換えられ
る。また、1ビットD/Aコンバータ11、15は、演
算する信号の極性,応答性により各種の方式が使用でき
ることは言うまでもない。すなわち、上記実施例では、
入力信号電圧VB (=Va +Vb )の極性が常に正であ
るので、1ビットD/Aコンバータ11、15をアナロ
グスイッチ31,35により置き換えることができた
が、極性が負をとるのであれば、図4(a)、(b)の
ような構成にする必要がある。
The subtractor 12 shown in FIG. 1 has input signal voltages V A and V
If the polarities between B are opposite, they are replaced by the adder 32. Needless to say, the 1-bit D / A converters 11 and 15 can use various methods depending on the polarity and responsiveness of the signal to be calculated. That is, in the above embodiment,
Since the polarity of the input signal voltage V B (= V a + V b ) is always positive, the 1-bit D / A converters 11 and 15 could be replaced by the analog switches 31 and 35, but the polarity is negative. If so, the configuration as shown in FIGS. 4A and 4B is required.

【0022】図4(a)では、入力信号電圧VB とこれ
を反転増幅器IA1により反転した電圧とを、比較器3
4の出力Dによりスイッチ回路S1で切り換えるように
している。図4(b)では、入力信号電圧VB をオペア
ンプOP1の反転入力端子に入力する。一方、オペアン
プOP1の非反転入力端子への入力信号電圧VB の入力
を、比較器34の出力Dによってオン、オフするスイッ
チS2により切り換えるようにしている。
In FIG. 4A, the input signal voltage V B and the voltage obtained by inverting the input signal voltage V B by the inverting amplifier IA1 are compared with each other by the comparator 3
The output D of 4 is used for switching by the switch circuit S1. In FIG. 4B, the input signal voltage V B is input to the inverting input terminal of the operational amplifier OP1. On the other hand, the input of the input signal voltage V B to the non-inverting input terminal of the operational amplifier OP1 is switched by the switch S2 which is turned on / off by the output D of the comparator 34.

【0023】[0023]

【発明の効果】以上の説明により明らかなように、本発
明によるアナログ演算回路は調整を要する箇所が無いた
め、精度が良く安定性に優れているのみならず、特種な
部品または厳格な選定作業を必要とせず、得られる経済
効果は大である。
As is apparent from the above description, since the analog arithmetic circuit according to the present invention has no portion requiring adjustment, it is not only accurate and excellent in stability, but also special parts or strict selection work. There is no need to pay, and the economic effect obtained is large.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による演算回路の実施例の構成を示す図
である。
FIG. 1 is a diagram showing a configuration of an embodiment of an arithmetic circuit according to the present invention.

【図2】図1の各部の電圧波形を示す図である。FIG. 2 is a diagram showing voltage waveforms of respective parts of FIG.

【図3】本発明による演算回路を差動トランス信号検出
回路の補正に適用した例を説明するための図である。
FIG. 3 is a diagram for explaining an example in which the arithmetic circuit according to the present invention is applied to correction of a differential transformer signal detection circuit.

【図4】図1に示された1ビットD/Aコンバータの具
体例を示した図である。
FIG. 4 is a diagram showing a specific example of the 1-bit D / A converter shown in FIG.

【図5】差動トランス信号検出回路の一例を示す図であ
る。
FIG. 5 is a diagram showing an example of a differential transformer signal detection circuit.

【図6】従来のアナログ演算回路の構成を示す図であ
る。
FIG. 6 is a diagram showing a configuration of a conventional analog arithmetic circuit.

【符号の説明】[Explanation of symbols]

31、35 アナログスイッチ IA1 反転増幅器 OP1 オペアンプ 31, 35 Analog switch IA1 Inverting amplifier OP1 Operational amplifier

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 補正演算の分母となる直流電圧を受ける
第1の1ビットD/Aコンバータと、該1ビットD/A
コンバータの出力と基準電圧とを受けて減算を行う演算
器と、該演算器の出力を受けて積分を行う積分器と、該
積分器の出力を受けて極性判別を行う比較器と、補正演
算の分子となる直流電圧を受ける第2の1ビットD/A
コンバータとからなり、前記比較器の出力を前記第1及
び第2の1ビットD/Aコンバータの切り換え信号とし
て用い、前記第2の1ビットD/Aコンバータの出力を
補正演算出力として得ることを特徴とするアナログ演算
回路。
1. A first 1-bit D / A converter for receiving a DC voltage serving as a denominator of a correction operation, and the 1-bit D / A.
An arithmetic unit that receives the output of the converter and the reference voltage to perform subtraction, an integrator that receives the output of the arithmetic unit to perform integration, a comparator that receives the output of the integrator to determine the polarity, and a correction operation Second 1-bit D / A that receives the DC voltage that becomes the numerator of
A converter, wherein the output of the comparator is used as a switching signal for the first and second 1-bit D / A converters, and the output of the second 1-bit D / A converter is obtained as a correction calculation output. Characteristic analog arithmetic circuit.
【請求項2】 請求項1記載のアナログ演算回路におい
て、前記1ビットD/Aコンバータとしてアナログスイ
ッチを用いることを特徴とするアナログ演算回路。
2. The analog arithmetic circuit according to claim 1, wherein an analog switch is used as the 1-bit D / A converter.
JP21567794A 1994-09-09 1994-09-09 Analog arithmetic circuit Withdrawn JPH0877282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21567794A JPH0877282A (en) 1994-09-09 1994-09-09 Analog arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21567794A JPH0877282A (en) 1994-09-09 1994-09-09 Analog arithmetic circuit

Publications (1)

Publication Number Publication Date
JPH0877282A true JPH0877282A (en) 1996-03-22

Family

ID=16676339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21567794A Withdrawn JPH0877282A (en) 1994-09-09 1994-09-09 Analog arithmetic circuit

Country Status (1)

Country Link
JP (1) JPH0877282A (en)

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Cited By (10)

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US11169775B2 (en) 2009-06-19 2021-11-09 Singular Computing Llc Processing with compact arithmetic processing element
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US11842166B2 (en) 2009-06-19 2023-12-12 Singular Computing Llc Processing with compact arithmetic processing element
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