JPH087706Y2 - PLL frequency synthesizer circuit - Google Patents

Description

[Detailed description of the device] (a) Industrial application field This device is used for radio receivers and wireless communication devices.
The present invention relates to a PLL (Phase Locked Loop) frequency synthesizer circuit.

(B) Problems to be solved by the conventional technology and device As a PLL frequency synthesizer, there is, for example, one configured as shown in FIG.

In FIG. 4, a VCO (voltage controlled oscillator) is generally composed of a varicap (variable capacitance diode).

As described above, it is known that a VCO using a varicap does not have a linear relationship in the control voltage of the oscillation frequency (reception frequency) as shown in FIG. 6 due to the characteristics of the varicap. It was

In addition, the VCO's performance is primarily considered by how much the frequency changes with the control voltage, and the performance of the entire PLL greatly changes. That is, there are cases where it is desired to have a large frequency variable range, and conversely, when the variable range may be small, but importance is attached to the purity of the oscillating frequency (spectrum purity).

On the other hand, the frequency setting is performed by a programmable divider as shown in the block diagram of the FM tuner synthesizer of FIG. 5, for example.

In the block diagram shown in FIG. 5, the front end portion is a VCO. Further, the programmable divider is controlled by the controller, and the frequency is set by setting the controller by the input device.

In this way, the frequency is set by the programmable divider, but the transfer function of the PLL is 1 / N (N
Is the division ratio of the programmer divider), and it was known that the transfer function becomes smaller as the frequency becomes higher. This becomes the characteristic as shown in FIG. 7 in combination with the characteristic of the varicap described in FIG.

Therefore, in the above-mentioned conventional one, the spectrum purity of the oscillating signal is not constant depending on the frequency, that is, the conversion gain KV of the VCO is not constant depending on the frequency. There was a problem that it was difficult to make a decision.

That is, specifically, as shown in FIG. 6, the varicap used can be used from 1 to 25V,
The use range is limited to 3V to 20V. The oscillation frequency is 65.3 to 79.3MHz, and the change ratio is 1.21 times.

FIG. 7 shows the VCO conversion gain with respect to the reception frequency obtained from FIG. It is 6.8 times higher at the upper and lower limits. Furthermore, since the comparison frequency of the division ratio N is 25 KHz, N at 79.3 MHz is 2612 at 3172,65.3 MHz, and KV / N near 79.3 MHz is 2.2 × 10 ⁶ / 3,172 ≈ 693 KV near 65.3 MHz. From /N=14.9×10 ⁶ / 2,612 ≒ 5710, this ratio is 5710/693 = 8.24 times.

Therefore, even if the calculation is performed with the center frequency of reception of 83 MHz, it will be too far apart on both sides.

To prevent this problem, the conversion gain depends on the reception frequency.
A weighting circuit that keeps the KV / frequency division ratio N constant or a circuit that changes the loop constant is required.

The present invention has been made in view of such problems of the conventional technology, and the purpose thereof is VC
An object of the present invention is to provide a PLL frequency synthesizer circuit that can improve the spectrum purity of an O oscillation signal.

(C) Means for Solving the Problem In order to achieve the above object, in the PLL frequency synthesizer circuit of the present invention, the controller changes the dividing ratio of the programmable divider to set the reception frequency to the desired frequency, and at the same time, The controller is configured to give different control signals according to the set frequency to the phase comparator to change the loop constant of the PLL to improve the spectrum purity of the VCO oscillation signal.

(D) Function The frequency division ratio of the programmable divider is changed by the controller to set the desired reception frequency.

At the same time as this setting operation, a different control signal according to the set frequency is given from the controller to the phase comparator and the PLL
Change the loop constant of and set the operation to improve the spectrum purity of the VCO.

(E) Example An example will be described with reference to the drawings.

FIG. 1 shows an embodiment of a PLL frequency synthesizer circuit, in which 1 is a reference signal oscillator, 2 is a phase comparator, and 3 is
VCO (voltage controlled oscillator), 4 is a programmable divider, and 5 is a controller. The controller 5 changes the frequency division ratio of the programmable divider 4. The present invention is configured so that the controller 5 controls the programmable divider 4 and at the same time, the controller 5 gives different control signals a according to the set frequency to the phase comparator 2. Based on this control signal, the phase comparator 2 changes the loop constant of the PLL to perform operation setting for improving the purity of the oscillation frequency of VCO3, that is, the spectrum purity.

For frequency setting 6, the controller 5 is set by the input device. Examples of this method include pushing the push button to raise and lower the frequency, using a rotary encoder to make it look like a coaxial knob, and taking it in and out from a memory device.

FIG. 2 shows another specific embodiment of the phase comparator 2
The capacitors of the loop filter inserted between VCO3 and VCO3 are four capacitors C1 to C4 having different capacitance values, and the switch S can select four stages of loop constants.

Therefore, the switch S can be switched according to the set frequency to change the loop filter constant of the PLL. As a result, as shown in FIG. 3, it is possible to obtain a characteristic in which the spectrum purity is improved as compared with the characteristic when the conventional loop filter constant is fixed.

(F) Effect of the device This device has a PL according to the set frequency (reception frequency).
Since the loop constant of L can be changed, the spectrum purity of the VCO (voltage controlled oscillator) can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a characteristic diagram showing the SN ratio with respect to the oscillation frequency of the VCO. 4 is a block diagram showing an example of a conventional PLL frequency synthesizer, FIG. 5 is a block diagram of a conventional FM tuner synthesizer, FIG. 6 is a characteristic diagram showing a control voltage with respect to a reception frequency of a front end, and FIG. 7 is Front end
It is a characteristic view which shows the conversion gain with respect to a VCO frequency. Description of main part symbols 2: Phase comparator 3: VCO 4: Programmable divider 5: Controller a: Control signal

Claims (1)

[Scope of utility model registration request] 1. In a PLL frequency synthesizer, a controller changes a frequency division ratio of a programmable divider to set a reception frequency to a desired frequency, and at the same time, a different control signal according to the set frequency is given from a controller to a phase comparator. Change the PLL loop constant to
A PLL frequency synthesizer circuit configured to improve the spectrum purity of the CO oscillation signal.