JPH087699B2 - System with command parity check function - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk device connected to a host through a system interface, and more particularly to a means for improving the consistency of command transmission on the interface and inside a controller.

[0002]

BACKGROUND OF THE INVENTION To enable the connection of devices manufactured by different manufacturers, the American National Standards Institute (ANSI) is a small computer system for interfacing peripheral devices with small computers. -Established various standards including interface (SCSI) standards. However, many standards have not yet been established within the controller for peripheral devices. Peripheral devices, such as optical disk devices, often have controllers that use a wide variety of components from different manufacturers to provide certain controller functions. For example,
An optical disk controller has a microprocessor manufactured by one manufacturer, an optical disk controller manufactured by another manufacturer, and an encoder / decoder for error checking manufactured by another manufacturer. . As a result, numerous components within the controller will have different interface characteristics and different levels of consistency checking. In this situation,
It occurs during the transmission of commands and may not be detected by the hardware inspection circuit inside the system. Solving this problem at the hardware level requires standardization between various component supplier transmission protocols and error checking to improve consistency, and in some cases parity checking hardware or cyclic. Redundancy check (CRC)
Let's need hardware. Without such standardization, certain bits may be lost from one command byte when one component communicates with another. There is also the possibility of generated noise that produces another bit. As a result, an incorrect command may be executed that gives unnecessary results.

The present invention is intended to raise the level of command consistency to an acceptable level by providing a means of improving the consistency of the command transmission process without requiring compliance with new standards. It

The present invention also provides improved directives so that existing systems and peripherals that do not have the means for improved directive consistency of the present invention can continue to function in their normal state. It is characterized by the provision of means for retaining the consistency of transmission.

US Pat. Nos. 4,843,544 and 4,965,801 relate to SCSI controllers. The former patent discusses the transfer of data from the SCSI bus into and out of the storage of optical disks. Two buffers are used for the transfer and this buffer hardware obviously has parity checking capability. The latter patent incorporates all controller components in one integrated circuit.

[0006]

According to the present invention, a parity bit is added to a command block in a host, and the parity of the command block is checked after the command block is stored in a memory of a controller. Is intended to effectively verify the transmission and storage of correct command blocks in many components involved in the transmission.

The host processor, whether it is a small computer or a large system such as the System 370 computer, stores the parity by sequentially storing the parity across the bytes in the command block.
Generate a bit. This places the generated parity bit in a unique location in the command block and sends this command block to the I / O interface for transmission to the target device. The target controller receives and stores this command block, reproduces the parity bit and compares it with the transmitted parity bit. If they are equal, the process continues normally. If they are not equal, an error recovery procedure is invoked, which typically involves retrying the transmission.

The parity check of the command control block is initiated by the host processor by using the command that makes the selection available at the peripheral. Thus, if the parity check capability is not activated, the host can interface with a target controller that does not have parity generation capability. Activation is done by setting the appropriate flag.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a peripheral device, in this example a SCSI bus 1.
2 shows a controller 10 for an optical disk drive 23 connected to a host processor 11 on the H.2. The controller 10 is a target interface / logic circuit 13
And an optical disk controller 14 and a microprocessor 15. Read-only memory (ROM) 16
And random access memory (RAM) 17
Are associated with the microprocessor 15. A run length limit (RLL) circuit 18 moves data in and out of the drive 23. Buffer 1
Reference numeral 9 provides a storage area for data, and an error correction code (ECC) logic circuit 20 performs correction on the data contained in the buffer 19. The optical disk 24 is a drive 23 for writing and reading data with respect to the disk.
Loaded in.

Microprocessor 15 is the system administrator for the controller. This microprocessor includes an optical disk controller 14 and a drive
Control the interface. It interprets SCSI commands and monitors the ECC logic 20 by the optical disk controller. The disk controller 14
Controls the ECC encoding / decoding and data buffering process. ROM 16 provides local control storage for disk controller 14 and RAM
17 provides working storage for the microprocessor 15. The interface / logic circuit 13 is a bus 1.
2 receives commands and data from the host processor. The SCSI start program is a host I / O function that exchanges commands and data between the host and peripheral devices according to the SCSI standard.

The command control block 30 is generated by the host processor and sent on the bus 12 to the controller 10. While the SCSI bus 12 is protected by parity, the buses between other hosts and devices may or may not be protected by hardware parity checking. Also, the bus internal to the host processor and the SCSI start program may not have parity protection. Therefore, in the general case, the register including the command control block in the target interface / logic circuit 13 may or may not include the correct command. These commands are sent from the interface / logic circuit 13 to the RAM 17. Microprocessor 1
Reference numeral 5 denotes an interface / logic circuit 13 for processing the commands contained in the command control block to write data to or read data from the disk 24 so as to move data into or out of the buffer 19, and to return the data from the buffer 19 to the host 11 again. The bus 12 is written or read.

The possibility of picking up one bit or discarding one bit in a particular command exists within the framework of these devices, depending on the parity checking capabilities of the controller 10, bus 12 or host 11. Further, within the controller 10, command consistency may be lost when command data is sent from the target interface / logic circuit 13 to the bus 21 , controller 14, then controller 14 to bus 22, and finally to RAM 17. However, this is because some or all of these components may not be protected by the hardware error detection capability.

To protect the consistency of these commands, the present invention adds a parity bit to a selected unique location within the command control block 30 when the command control block 30 is configured within the host 11. Host process. Once the command transmission to the controller is complete, the command control block resides in RAM 17. The same process that takes place in the host used to generate the parity bits is performed by microprocessor 15 to generate the parity for the command information contained in the command control block, which then resides in RAM 17. A comparison is then made to determine if the parity bit generated by microprocessor 15 is equal to the parity sent by host 11. If the parities match, then the transmission is correct and the command can be executed normally. However, if the parities do not match, a retry is started again to obtain the command control block 30 from the host processor 11. After several retries, a permanent error is reported.

To enable the command block parity check by the controller 10, to signal that a parity check should be performed by the device on the contents of the command control block (CCB) sent by the host, a "mode select" command is sent. Such a command is sent to the device. If the mode select bit is not set, no parity checking is done by the controller. In this way, a device without a parity check function in the controller 10 can be used during transmission from the host. Therefore, a host and a device with or without the parity check capability of the present invention can coexist on the bus 12.

The command control block may be 6, 10 or 12 bytes in length. The host process that generates the parity for the contents of the command control block excludes the last byte or, if necessary, the parity for the entire contents of the control block including the last byte except for the vendor specific bit # 7. Establish. The result of this parity process is stored in the last byte of bit # 7. To generate the parity bit stored in bit 7 of the last byte of the control block, the host process is exclusive of the eight bits of byte 0 of the control block and the corresponding eight bits of byte 1 of the control block. It results in machine operations starting with OR (XOR). By "corresponding bit" is meant that bit 0 of byte 0 is exclusively ORed with bit 0 of byte 1 to produce the result of bit 0. Bit 1 of byte 0 is bit 1 of byte 1
Is exclusive ORed with to produce a bit 1 result, and so on until all 8 bits have been produced to yield an 8 bit result. The host then XORs the 8 bits of the result with the corresponding 8 bits of byte 2 of the control block, performs this result on the corresponding 8 bits of byte 3 of the control block, which is the control Continue until the next byte (N-1) before the last byte of the block. The result of the exclusive-OR of bytes 0 to (N-1) of the control block is stored as the middle 8-bit byte. The 8 bits of this intermediate byte are exclusive OR'd together for bits 0-7 until one parity bit is reached. That is, bit 0 is XORed with bit 1 to produce a 1 bit result, which is XORed with bit 2 to produce a 1 bit result, which is XORed with bit 3 to produce a parity bit. Continues until. This parity
The bit is stored in bit 7 of the last byte of the control block (the choice of bit 7 does not preclude other choices, but is designated as a "vendor-specific bit", so S
This is the preferred configuration in CSI format).

Bit 7 in the generation of the parity bit
If it is required to include the 7 bits of the final byte other than, the intermediate byte is exclusive ORed with the final byte with bit 7 set to zero. The result is a new intermediate byte, the bits of which are exclusive ORed together to obtain a bit, which is stored in bit 7 of the final byte.

Next, the command control block is sent to the target controller by the start program and stored in the target interface / logic circuit 13. The target microcode in the microprocessor 15 reads the command register of the interface / logic circuit 13 via the disk controller and stores this command in the working memory RAM 17 of the microprocessor.

The microprocessor 15, or preferably the controller logic element, then regenerates the parity bits using the same exclusive-OR as was performed in the host processor. This is done by accessing the contents of the command control block located in RAM 17. The result is a parity bit that is compared to the parity bit in bit 7 of the last byte contained in the command control block and sent.

If the comparison in the above operation is successful, then the process of the controller is allowed to continue normal processing of the command control block. However, if this comparison is unsuccessful, execution of the command is prohibited and an error recovery procedure is called to retransmit the command from the host. If the command is generated on a parity protected host and sent on a parity protected bus, the error resend is unlikely to be repeated. However, the repeated error can result from the unprotected controller 10. Thus, if repeated errors occur in such a case, the problem is isolated to the unprotected drive controller 10. Errors are not isolated unless the host and bus are protected by hardware parity.

FIG. 2 illustrates an initialization routine resident in host processor 11 and used to determine whether a peripheral device attached to the host has parity check capability. In step 100, the host issues a "mode detect" command to know these capabilities from the attached peripherals. In step 101, the detection information returned from the device is examined to determine if the device has parity check capability . If so, in step 102, the parity check bit in the mode selection parameter page for this device.
Is set to 1. In step 103, the capability bit is set to 1 and the generate bit is set to 1. If the device is unable to handle parity as found in step 101, it branches to steps 104 and 105 where the capability and parity bits are set to zero for that particular device. Finally, in step 106, an inquiry is made as to whether all devices attached to the bus have been tested. If they have not been tested, the branch is taken back to step 101 to test other devices attached to the bus. Once all devices have been tested, a return is made to the rest of the initialization routine.

After completion of the initialization routine shown in FIG. 2, the host device continues with all other functions associated with the initialization, and finally the flow chart shown in FIG. 3 towards the end of the initialization process. Entering, the purpose of this flow chart is to select the options available to the host at step 110 in the host, eg, one of the options available to a drive yields a command that allows checking the parity according to the method of the present invention. Is. In a device with parity check capability, the mode selection command issued to this device in step 110 is:
The device can be instructed to exercise its parity check capability. This is done by sending the device the appropriate parity check bits in the mode selection parameter page. This process begins at step 111.
Continuing for each device on the bus as shown in, and then returning to completion of initialization.

It should be noted that the mode select command is an artifact of the SCSI command set and is exemplary of the type of command given in step 110. If another type of standard interface is used,
The appropriate command from the command set for this interface will be used.

During the processing of one program in the host, a write command is issued to write some blocks of data to an external storage device, ie an optical disk device. In such a case, the I / O routine resident in the host prepares a command control block for the write command. This control block contains 12 bytes of data. Byte 0 refers to the command itself, byte 1 is the first written to the particular device
, The address of the block of bytes, byte 2 the number of blocks to be written, and so on. If one parity bit is generated by the present invention for the device to which the write command is directed, a call to generate the parity bit is issued by the I / O routine. This call uses the machine operations shown in FIG. In step 120, the generated bit for the specified device is checked. If the generate bit is set to 1, step 121 is executed to store the command control block prepared by the I / O routine in local storage.
In steps 122 and 123, the exclusive O described above is used.
The R process is executed. At step 122, each bit of byte 0 is exclusive ORed with the corresponding bit in byte 1. The result is exclusive ORed with the corresponding bit in byte 2. The result is exclusive ORed with the corresponding bit in byte 3, and so on until all bytes in the command control block have been processed except the last byte. Once the intermediate result is obtained in step 123, the bits of this intermediate result are mutually exclusive-ORed to produce one bit, a 1 or a 0, representing the parity of the command control block. This bit is then stored in bit 7 of the last byte. Bit 7 is S
Note that it is a "vendor specific" bit in the CSI standard. Finally, step 124 returns to the I / O routine to revisit the modified CCB.

The I / O routine will continue to perform its function in the normal way and will eventually send the command control block to the instructed device. In FIG. 5, in step 130, the optical disk controller (ODC) puts the command control block in the RAM 17. This routine is shown in FIG. 6 in which the parity check bit is checked at step 140 to determine if it was set to 1 by the host. If so, in step 141 the command control block is sent to local storage in the microprocessor 15 and the same exclusive O done in the host.
The R process is performed on the command control block in steps 142 and 143. In step 144,
The generated parity bit is compared with the last bit, which is bit 7 in the last byte. If they are equal, the process returns to the process shown in FIG. 5 to display that there is no error. If these bits are not equal, a return is made and an error indication is given.

In FIG. 5, a return from the parity check routine is made at step 132 and a check is made at step 133 to determine if an error has been reported. If there are no errors, the command in the command control block is executed as shown in step 134. But,
If an error is reported, the error condition is reported to the host in step 135. The host will then initiate the retry procedure or take whatever action is indicated.

FIG. 7 shows a modification of the machine operation that could be used if it was desired to include byte N of the command control block when generating the parity bit. If necessary, steps 160-163 shown in FIG. 7 replace steps 122, 123 of FIG. 4 and step 1 of FIG.
42 and 143 are replaced.

To implement the parity generation operation shown in FIG. 7, the bits of byte 0 are exclusive ORed with the corresponding bits of byte 1 in step 160, and the result is exclusive ORed with the corresponding bits of byte 2. , The result is exclusive-ORed with byte 3, and this is the byte (N-
Continue until 1). In step 161, bit 7 of byte N, which is the bit used to indicate the parity of the CCB, is set to zero. Then step 16
At 2, the result of step 160 is exclusive ORed with the corresponding bits of byte N to obtain the intermediate byte. In step 162, the bits of the intermediate byte are exclusive O
R, resulting in one bit representing the parity of the CCB. The machine operation of FIG. 7 corresponds to steps 122 and 12 of FIG.
If so done, the resulting parity bit is stored in bit 7 of byte N as shown in step 123A. The machine operation of FIG. 7 is shown in FIG.
If the step 10 is performed in the controller 10 to replace steps 142, 143 of the above, the resulting bits are compared to the transmitted parity bits as shown in step 144.

The invention has been described in terms of the SCSI architecture. Bits in the middle byte are mutually exclusive O
R, which represents the parity of the command control block
Produces one bit of 0, which is the last byte of the
Stored in bit 7. Bit 7 is in the SCSI standard
It should be noted that this is a "vendor specific" bit.
It

[0029]

When the command is sent from the host to the peripheral device, the consistency of the command is maintained.

[Brief description of drawings]

FIG. 1 is a typical small computer using the present invention.
FIG. 3 is a block diagram showing a system interface (SCSI) controller.

FIG. 2 is a diagram showing each part of initialization of a routine in a host for activating the present invention.

FIG. 3 is a diagram showing each part of initialization of a routine in a host for activating the present invention.

FIG. 4 is a diagram showing a parity generation logic circuit for a host according to the present invention.

FIG. 5 is a diagram showing a parity check logic circuit in the optical disc device and command processing in the present device.

FIG. 6 is a diagram showing a parity check logic circuit in the optical disk device and command processing in this device.

FIG. 7 is a diagram showing a machine operation for a change in a parity generation logic circuit.

[Explanation of symbols]

 10 Controller 11 Host Processor 12 SCSI Bus 13 Purpose Interface / Logic Circuit 14 Optical Disk Controller 15 Microprocessor 16 Read Only Memory (ROM) 17 Random Access Memory (RAM) 18 Run Length Limit (RLL) Circuit 19 Buffer 20 Error correction code (ECC) logic circuit 22 Bus 23 Optical disk drive 24 Optical disk 30 Command control block (CCB)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-232736 (JP, A) JP-A 64-111234 (JP, A) JP-A 58-90251 (JP, A)

Claims (1)

[Claims] 1. A system comprising an optical disk device connected to a host via a system interface, and including means for generating a command control block for each command given to the optical disk device inside the host, wherein the host internal And a first parity generating means arranged for each bit of the first byte in the command control block and each corresponding bit of other bytes excluding the vendor specific bit. An exclusive-OR operation is performed, or an exclusive-OR operation is performed on each bit of the first byte in the command control block and each corresponding bit of the other bytes except the final byte to generate an intermediate byte. And an exclusive OR logic circuit for sequentially performing an exclusive OR operation on a plurality of bits of the intermediate byte. An exclusive OR logic circuit for generating a first bit representing the parity of the control block, generating a first bit representing the parity of the command control block, and including the first bit in a vendor specific bit. First parity generating means, means for transmitting the command control block and the first bit to the optical disk device, and second parity generating means arranged inside the optical disk device, The second parity generating means represents the parity of the command control block by a configuration equivalent to the exclusive OR logic circuit included in the first parity generating means.
Second parity generating means for generating a second bit representing the parity of the command control block, and an exclusive OR logic circuit for generating the bit of the command control block, and a parity of the command control block arranged inside the optical disk device. Means for comparing the first and second bits representing, and producing a signal indicating the absence of an error in the command control block if they are equal.