CN115081429A - Instruction checking method, device, equipment and storage medium - Google Patents
Instruction checking method, device, equipment and storage medium Download PDFInfo
- Publication number
- CN115081429A CN115081429A CN202210802484.6A CN202210802484A CN115081429A CN 115081429 A CN115081429 A CN 115081429A CN 202210802484 A CN202210802484 A CN 202210802484A CN 115081429 A CN115081429 A CN 115081429A
- Authority
- CN
- China
- Prior art keywords
- byte
- instruction
- check
- check byte
- checked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F40/00—Handling natural language data
- G06F40/20—Natural language analysis
- G06F40/205—Parsing
- G06F40/226—Validation
Abstract
The invention discloses a method, a device, equipment and a storage medium for checking an instruction. The method comprises the following steps: acquiring an instruction to be checked, wherein the instruction to be checked comprises a byte array and an initial check byte; determining a target check byte according to the byte array, wherein the target check byte comprises: a first check byte and a second check byte; if the instruction to be checked is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, adjusting the instruction to be checked according to the first check byte and the second check byte to obtain a target instruction. According to the embodiment of the invention, the target instruction is obtained by obtaining the instruction to be verified, determining the target verification byte according to the byte array and adjusting the instruction to be verified according to the target verification byte, so that the process of quickly, accurately and efficiently verifying the instruction to be verified can be realized, and the correct target instruction can be obtained.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for instruction verification.
Background
At present, a satellite remote control instruction uploading and remote measuring content downloading system exists, the system needs to be matched with a remote control instruction table, a remote measuring package table and a remote measuring package content three tables for use, and the three tables are EXCEL tables. The method aims at the instruction verification that a verification tool with an input box is available at present, but only one instruction can be input at a time, then the point button is used for carrying out XOR and verification, and after the verification is finished, the point button is copied and pasted into a remote control instruction list. However, if there are many commands to be verified, the copy-paste click button operation is frequently required, which is relatively inefficient and time consuming.
Disclosure of Invention
The invention provides an instruction checking method, device, equipment and storage medium, which are used for realizing a process of quickly, accurately and efficiently checking an instruction to be checked to obtain a correct target instruction.
According to an aspect of the present invention, there is provided an instruction checking method, the method including:
acquiring an instruction to be checked, wherein the instruction to be checked comprises a byte array and an initial check byte;
determining a target check byte according to the byte array, wherein the target check byte comprises: a first check byte and a second check byte;
if the instruction to be checked is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, adjusting the instruction to be checked according to the first check byte and the second check byte to obtain a target instruction.
According to another aspect of the present invention, there is provided an instruction verifying apparatus, the apparatus including:
the device comprises an acquisition module, a verification module and a verification module, wherein the acquisition module is used for acquiring an instruction to be verified, and the instruction to be verified comprises a byte array and an initial verification byte;
a first determining module, configured to determine a target check byte according to the byte array, where the target check byte includes: a first check byte and a second check byte;
and the adjusting module is used for adjusting the instruction to be checked according to the first check byte and the second check byte to obtain a target instruction if the instruction to be checked is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte.
According to another aspect of the present invention, there is provided an electronic apparatus including:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the instruction checking method according to any of the embodiments of the present invention.
According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the instruction verification method according to any one of the embodiments of the present invention when the computer instructions are executed.
According to the technical scheme, the target instruction is obtained by obtaining the instruction to be verified, wherein the instruction to be verified comprises a byte array and an initial check byte, the target check byte is determined according to the byte array, the target check byte comprises a first check byte and a second check byte, and if the instruction to be verified is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, the instruction to be verified is adjusted according to the first check byte and the second check byte. The embodiment of the invention can realize the process of quickly, accurately and efficiently verifying the instruction to be verified to obtain the correct target instruction.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flowchart of an instruction checking method according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an effect of an instruction checking method according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an instruction checking apparatus according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device implementing the instruction verification method according to the embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "target," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example one
Fig. 1 is a flowchart of an instruction checking method according to an embodiment of the present invention, where the embodiment is applicable to an instruction checking situation, the method may be executed by an instruction checking device, the instruction checking device may be implemented in a hardware and/or software form, and the instruction checking device may be integrated in any electronic device providing an instruction checking function. As shown in fig. 1, the method includes:
and S101, acquiring a command to be verified.
In this embodiment, the instruction to be verified may be an initial instruction to be verified, and for example, the initial instruction may specifically be a satellite remote control instruction.
The instruction to be checked comprises a byte array and an initial check byte.
It should be noted that the byte array may be a main data component of the instruction to be checked, and the initial check byte may be a data component for instruction checking. In this embodiment, the complete instruction to be verified may be composed of 16-bit bytes of hexadecimal data, where the first 14-bit bytes of hexadecimal data of the instruction to be verified constitute a byte array, and the last two bytes of hexadecimal data are the initial check bytes.
Specifically, a batch of instructions to be verified is obtained. In an actual operation process, the obtained batch of instructions to be checked may include a complete instruction to be checked, that is, the instruction to be checked is composed of 16-bit byte hexadecimal data, where the first 14-bit byte hexadecimal data constitutes a byte array, and the last two-bit byte hexadecimal data is an initial check byte.
S102, determining a target check byte according to the byte array.
It should be noted that the target check byte may be a correct check byte corresponding to the instruction to be checked, which is determined according to a byte array in the instruction to be checked.
Wherein the target check byte comprises: a first check byte and a second check byte.
In this embodiment, the target check byte may be composed of two-bit byte hexadecimal data, the first byte of the target check byte is the first check byte, and the second byte of the target check byte is the second check byte.
Specifically, an exclusive-or operation is performed on a byte array in each instruction to be checked, a first check byte and a second check byte corresponding to each instruction to be checked are determined, and a target check byte corresponding to each instruction to be checked is determined according to the first check byte and the second check byte corresponding to each instruction to be checked.
S103, if the instruction to be verified is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, adjusting the instruction to be verified according to the first check byte and the second check byte to obtain a target instruction.
It should be noted that the error instruction may mean that the initial check byte is equivalent to the instruction to be checked and is incorrect, that is, after performing the xor operation according to the byte array in the instruction to be checked, the obtained target check byte is different from the initial check byte.
The adjusting operation may be to overwrite the initial check byte in the instruction to be checked with the determined first check byte and the second check byte.
It should be noted that the target instruction may be a complete and correct instruction obtained by performing calibration adjustment on the instruction to be calibrated.
Specifically, if a target check byte determined by a certain instruction to be checked according to the byte array of the instruction to be checked is different from an initial check byte of the instruction to be checked, the instruction to be checked is determined to be an error instruction, and the initial check byte in the instruction to be checked is covered by the determined first check byte and the determined second check byte, so that a correct target instruction is obtained.
According to the technical scheme, the target instruction is obtained by obtaining the instruction to be verified, wherein the instruction to be verified comprises a byte array and an initial check byte, the target check byte is determined according to the byte array, the target check byte comprises a first check byte and a second check byte, and if the instruction to be verified is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, the instruction to be verified is adjusted according to the first check byte and the second check byte. The embodiment of the invention can realize the process of quickly, accurately and efficiently verifying the instruction to be verified to obtain the correct target instruction.
Optionally, the initial check byte includes a first initial check byte and a second initial check byte.
In this embodiment, the initial check byte may be composed of two-bit bytes of hexadecimal data, the first byte of hexadecimal data in the initial check byte is the first initial check byte, and the second byte of hexadecimal data in the initial check byte is the second initial check byte.
Correspondingly, if the instruction to be verified is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, adjusting the instruction to be verified according to the first check byte and the second check byte to obtain a target instruction, including:
and if the first check byte is not the same as the first initial check byte and/or the second check byte is not the same as the second initial check byte, determining that the instruction to be checked is an error instruction.
Specifically, if a first check byte determined by a certain instruction to be checked according to a byte array of the instruction to be checked is different from a first initial check byte of the instruction to be checked, or a second check byte determined according to the byte array of the instruction to be checked is different from a second initial check byte of the instruction to be checked, or the first check byte determined according to the byte array of the instruction to be checked is different from the first initial check byte and the second check byte determined according to the byte array of the instruction to be checked is different from the second initial check byte, the instruction to be checked is determined to be an error instruction.
And performing covering operation on the initial check byte by using the first check byte and the second check byte to obtain a target instruction.
Specifically, a first check byte determined according to a byte array in the instruction to be checked covers a first initial check byte in the instruction to be checked, and a second check byte determined according to the byte array in the instruction to be checked covers a second initial check byte in the instruction to be checked, so that the target instruction is obtained.
Optionally, the method further includes:
and if the first check byte is the same as the first initial check byte and the second check byte is the same as the second initial check byte, determining that the instruction to be checked is a correct instruction.
It should be noted that the correct instruction may mean that the initial check byte is equivalent to the correct instruction to be checked, that is, after performing the xor operation according to the byte array in the instruction to be checked, the obtained target check byte is the same as the initial check byte.
Specifically, if a first check byte determined by a certain instruction to be checked according to its byte array is the same as its first initial check byte, and a second check byte determined according to its byte array is also the same as its second initial check byte, the instruction to be checked is determined to be a correct instruction. If the instruction to be verified is a correct instruction, the instruction to be verified is not processed.
Optionally, after the instruction to be verified is obtained, the method further includes:
and judging whether the byte number of the byte array in the instruction to be checked is smaller than the byte number threshold value.
The byte number threshold may be the byte number of the byte array in the instruction to be checked, which is set according to the total number of bytes of the byte array of the complete instruction to be checked. For example, the total number of bytes of the byte array of the complete instruction to be checked may be 14, and the byte count threshold may be set to 14.
Specifically, after the batch of instructions to be checked is obtained, it is determined whether the byte number of the byte array in each instruction to be checked is smaller than the byte number threshold, that is, whether the byte array of each instruction to be checked is complete. In the actual operation process, the obtained batch of instructions to be verified can include complete instructions to be verified, that is, the instructions to be verified are composed of 16-bit byte hexadecimal data, wherein the first 14-bit byte hexadecimal data form a byte array, and the last two-bit byte hexadecimal data are initial check bytes; meanwhile, the obtained batch instructions to be verified may also include incomplete instructions, that is, the instructions to be verified only include byte arrays and the initial check bytes are missing, or the instructions to be verified only include partial byte arrays, the byte arrays are incomplete and the initial check bytes are missing.
And if the byte number of the byte array in the instruction to be checked is smaller than the byte number threshold, determining the difference value between the byte number threshold and the byte number as the number of the missing bytes.
The number of missing bytes may be the number of bytes missing from the byte array of the instruction to be checked, compared to the total number of bytes of the byte array of the complete instruction to be checked.
Specifically, whether the number of bytes of the byte array in each instruction to be checked is smaller than a byte number threshold is judged, and if the number of bytes of the byte array in a certain instruction to be checked is smaller than the byte number threshold, the difference between the byte number threshold and the byte number of the byte array in the instruction to be checked is determined as the number of missing bytes. For example, the total number of bytes of the byte array of the complete instruction to be checked may be 14, and then the byte count threshold may be set to 14, and if the byte count of the byte array in a certain instruction to be checked is 7, then the difference 7 between the byte count threshold 14 and the byte count 7 of the byte array in the certain instruction to be checked is determined as the number of missing bytes.
And completing the instruction to be checked according to the number of the missing bytes and a preset value.
In this embodiment, the predetermined number may be sixteen numbers of entries to complete the instruction to be verified. Specifically, the preset value may be set by the user according to actual conditions. Illustratively, the preset value may be sixteen times as large as the number AA.
Specifically, the preset value of the number of the missing bytes is supplemented to the instruction to be checked. For example, the byte count threshold may be set to 14, the preset value may be set to AA, if a certain instruction to be checked is 220006010C 0101, the byte count of the byte array of the instruction to be checked is 7, and if it is determined that the byte count of the byte array in the instruction to be checked is smaller than the byte count threshold, the instruction to be checked is completed with 7 AA, and the completed instruction to be checked is 220006010C 0101 AA AA AA AA AA AA AA.
Optionally, determining the target check byte according to the byte array includes:
a first check byte is determined from odd-numbered bytes in the byte array.
It should be noted that the odd-numbered byte may be a byte of the odd-numbered bit in the byte array of the instruction to be checked, and may be, for example, a first-numbered byte, a third-numbered byte, a fifth-numbered byte, a seventh-numbered byte, a ninth-numbered byte, and so on. Specifically, the number of odd-numbered bytes may be determined according to the total number of bytes of the byte array of the instruction to be checked, for example, the total number of bytes of the byte array of the instruction to be checked is 14, and the number of odd-numbered bytes may be 7.
Specifically, an exclusive or operation is performed on odd-numbered bytes in a byte array of the instruction to be checked to obtain a first check byte. For example, the first byte and the third byte in the byte array of the instruction to be checked are subjected to xor operation, the obtained result is subjected to xor operation with the fifth byte, and so on until the last odd-numbered byte in the byte array of the instruction to be checked is subjected to xor operation, and the obtained xor result is the first check byte.
The second parity byte is determined from the even-numbered bytes in the byte array.
It should be noted that the even-numbered byte may be an even-numbered byte in the byte array of the instruction to be checked, and may be, for example, a second byte, a fourth byte, a sixth byte, an eighth byte, a tenth byte, and the like. Specifically, the number of even-numbered bytes may be determined according to the total number of bytes of the byte array of the instruction to be checked, for example, the total number of bytes of the byte array of the instruction to be checked is 14, and the number of even-numbered bytes may be 7.
Specifically, an exclusive or operation is performed on even-numbered bytes in a byte array of the instruction to be checked to obtain a first check byte. For example, the second byte and the fourth byte in the byte array of the instruction to be checked are subjected to xor operation, the obtained result is subjected to xor operation with the sixth byte, and so on until the last even byte in the byte array of the instruction to be checked is subjected to xor operation, and the obtained xor result is the second check byte.
And determining a target check byte according to the first check byte and the second check byte.
Specifically, the combination of the first check byte and the second check byte is the target check byte, and in this embodiment, the combination of the first check byte and the second check byte may be in a manner that the first check byte precedes the second check byte.
Optionally, determining the first check byte according to an odd-numbered byte in the byte array includes:
and carrying out XOR operation on the first odd-numbered bit byte and the second odd-numbered bit byte in the byte array to obtain a first odd-numbered XOR result.
The first odd-numbered bit byte may be a first bit byte in the instruction to be checked, and the second odd-numbered bit byte may be a third bit byte in the instruction to be checked.
It should be noted that the xor operation may be performed by first converting hexadecimal numbers of the first odd-numbered bit byte and the second odd-numbered bit byte in the byte array into binary numbers, and then performing the xor operation on the first odd-numbered bit byte and the second odd-numbered bit byte in the byte array.
The first odd-bit exclusive-or result may be obtained by performing an exclusive-or operation on a first bit byte in the instruction to be checked and a third bit byte in the instruction to be checked.
Specifically, the hexadecimal numbers of the first byte in the instruction to be checked and the third byte in the instruction to be checked are converted into binary numbers, and then the two numbers are subjected to exclusive-or operation to obtain a first odd-numbered exclusive-or result.
And performing exclusive-or operation on the N odd-numbered bit exclusive-or result and the (N + 2) odd-numbered bit byte to obtain an (N + 1) odd-numbered bit exclusive-or result, wherein N is 1, 2, 3, 4 and 5.
Specifically, the total number of bytes of the byte array of the complete instruction to be checked may be 14, that is, the number of odd-numbered bytes in the byte array of the instruction to be checked may be 7. And performing XOR operation on a first odd-numbered bit byte and a second odd-numbered bit byte in the byte array to obtain a first odd-numbered bit XOR result, performing XOR operation on the first odd-numbered bit XOR result and a third odd-numbered bit byte to obtain a second odd-numbered bit XOR result, performing XOR operation on the second odd-numbered bit XOR result and a fourth odd-numbered bit byte to obtain a third odd-numbered bit XOR result, and so on, performing XOR operation on a fifth odd-numbered bit XOR result and a seventh odd-numbered bit byte to obtain a sixth odd-numbered bit XOR result.
The sixth odd-bit xor result is determined to be the first check byte.
The sixth odd-bit xor result may be an xor result obtained by xoring the fifth odd-bit xor result with the seventh odd-bit byte in the byte array.
It should be noted that, each time the xor operation is performed, the hexadecimal number in the byte array needs to be converted into a binary number, so after the xor result obtained by performing the xor operation on the fifth odd-bit xor result and the seventh odd-bit byte in the byte array, the obtained xor result needs to be converted into the hexadecimal number, and the hexadecimal number is determined to be the first check byte.
Optionally, determining the second parity byte according to the even-numbered byte in the byte array includes:
and carrying out XOR operation on the first even-numbered bit byte and the second even-numbered bit byte in the byte array to obtain a first even-numbered XOR result.
The first even-bit byte may be a second bit byte in the instruction to be verified, and the second even-bit byte may be a fourth bit byte in the instruction to be verified.
It should be noted that the xor operation may be performed by first converting hexadecimal numbers of the first even-bit byte and the second even-bit byte in the byte array into binary numbers, and then performing the xor operation on the first even-bit byte and the second even-bit byte in the byte array.
The first even bit xor result may be obtained by performing xor operation on the second bit byte in the instruction to be checked and the fourth bit byte in the instruction to be checked.
Specifically, the hexadecimal numbers of the second byte in the instruction to be checked and the hexadecimal number of the fourth byte in the instruction to be checked are both converted into binary numbers, and then the two numbers are subjected to exclusive or operation to obtain a first even-numbered exclusive or result.
And performing exclusive-or operation on the N even bit exclusive-or result and the (N + 2) even bit byte to obtain an (N + 1) even bit exclusive-or result, wherein N is 1, 2, 3, 4 and 5.
Specifically, the total number of bytes of the byte array of the complete instruction to be checked may be 14, that is, the even-numbered bytes in the byte array of the instruction to be checked may be 7. And performing XOR operation on a first even-numbered bit byte and a second even-numbered bit byte in the byte array to obtain a first even-numbered XOR result, performing XOR operation on the first even-numbered XOR result and a third even-numbered bit byte to obtain a second even-numbered XOR result, performing XOR operation on the second even-numbered XOR result and a fourth even-numbered bit byte to obtain a third even-numbered XOR result, and so on, performing XOR operation on a fifth even-numbered XOR result and a seventh even-numbered bit byte to obtain a sixth even-numbered XOR result.
The sixth even bit xor result is determined as the second parity byte.
The sixth even bit xor result may be an xor result obtained by xoring the fifth even bit xor result with the seventh even bit byte in the byte array.
It should be noted that, each time the xor operation is performed, the hexadecimal number in the byte array needs to be converted into a binary number, so after the xor result obtained by performing the xor operation on the fifth even bit xor result and the seventh even bit byte in the byte array, the obtained xor result needs to be converted into the hexadecimal number, and the hexadecimal number is determined to be the second check byte.
In the specific implementation process of the technical scheme of the embodiment of the invention, after a batch of instructions to be verified are obtained, an EXCEL table can be newly created, a tool → macro → Visual Basic editor menu command of a menu column in the EXCEL table is executed (or a shortcut key of 'Alt + F11' can be pressed), a Visual Basic editing window is opened, an 'insert → module' menu command is executed in the window to insert a new module, relevant codes of the technical scheme of the embodiment of the invention are input in a code window on the right side, the window is closed after the input is completed, the self-defined function can be named jy (initial of verified pinyin), and then the abbreviated function can be used as if a built-in function is used. Fig. 2 is an effect diagram of an instruction verification method according to an embodiment of the present invention, and as shown in fig. 2, an obtained batch of instructions to be verified is copied and pasted into column a of a newly-created EXCEL table, a custom function name jy is input into an input cell, a determination button is clicked, and automatic verification of the batch of instructions to be verified can be achieved through a pull-down function.
In fig. 2, column a is an acquired batch of instructions to be verified, and column B is a verified target instruction. As can be seen from fig. 2, according to the technical solution of the embodiment of the present invention, the instruction to be verified can be automatically complemented, the target check byte is determined, and the target instruction (for example, the instruction to be verified in the first row in fig. 2) is finally obtained, the target instruction (for example, the instruction to be verified in the second row in fig. 2) can be automatically obtained by adjusting the error instruction in which the initial check byte is incorrect in the instruction to be verified, and the target check byte can be automatically calculated for the instruction to be verified in which the initial check byte is missing, and the target instruction (for example, the instruction to be verified in the fifteenth row in fig. 2) can be obtained by adding the calculated target check byte to the instruction to be verified.
According to the technical scheme of the embodiment of the invention, batch verification of the instructions can be realized through the custom function, the instructions to be verified can be automatically supplemented, the initial verification bytes in the instructions to be verified can be automatically corrected, the operation of frequently copying and pasting click buttons can be solved, the time of workers can be saved, and the working efficiency of the workers can be improved.
Example two
Fig. 3 is a schematic structural diagram of an instruction checking apparatus according to a second embodiment of the present invention. As shown in fig. 3, the apparatus includes: an acquisition module 201, a first determination module 202 and an adjustment module 203.
The obtaining module 201 is configured to obtain an instruction to be checked, where the instruction to be checked includes a byte array and an initial check byte;
a first determining module 202, configured to determine a target check byte according to the byte array, where the target check byte includes: a first check byte and a second check byte;
the adjusting module 203 is configured to, if it is determined that the instruction to be checked is an erroneous instruction according to the first check byte, the second check byte, and the initial check byte, adjust the instruction to be checked according to the first check byte and the second check byte to obtain a target instruction.
Optionally, the initial check bytes include a first initial check byte and a second initial check byte;
accordingly, the adjusting module 203 comprises:
a first determining unit, configured to determine that the instruction to be verified is an error instruction if the first check byte is not the same as the first initial check byte and/or the second check byte is not the same as the second initial check byte;
and the covering unit is used for covering the initial check byte by the first check byte and the second check byte to obtain a target instruction.
Optionally, the apparatus further comprises:
a second determining module, configured to determine that the instruction to be verified is a correct instruction if the first check byte is the same as the first initial check byte and the second check byte is the same as the second initial check byte.
Optionally, the apparatus further comprises:
the judging module is used for judging whether the byte number of the byte array in the instruction to be checked is smaller than a byte number threshold value or not after the instruction to be checked is obtained;
a third determining module, configured to determine, after obtaining the instruction to be checked, if the number of bytes of the byte array in the instruction to be checked is smaller than a byte number threshold, a difference between the byte number threshold and the byte number as a missing byte number;
and the completion module is used for completing the instruction to be verified according to the number of the missing bytes and a preset value after the instruction to be verified is obtained.
Optionally, the first determining module 202 includes:
the second determining unit is used for determining a first check byte according to the odd-numbered bit bytes in the byte array;
a third determining unit, configured to determine a second parity byte according to an even-numbered byte in the byte array;
a fourth determining unit, configured to determine a target check byte according to the first check byte and the second check byte.
Optionally, the third determining unit is specifically configured to:
performing XOR operation on a first odd-numbered bit byte and a second odd-numbered bit byte in the byte array to obtain a first odd-numbered XOR result;
performing exclusive-or operation on the N odd-numbered bit exclusive-or result and an N +2 odd-numbered bit byte to obtain an N +1 odd-numbered bit exclusive-or result, wherein N is 1, 2, 3, 4 and 5;
the sixth odd-bit xor result is determined to be the first check byte.
Optionally, the fourth determining unit is specifically configured to:
carrying out XOR operation on a first even-numbered bit and a second even-numbered bit in the byte array to obtain a first even-numbered XOR result;
performing exclusive-or operation on the Nth even-numbered bit exclusive-or result and an (N + 2) th even-numbered bit byte to obtain an (N + 1) th even-numbered bit exclusive-or result, wherein N is 1, 2, 3, 4 and 5;
the sixth even bit xor result is determined as the second parity byte.
The instruction checking device provided by the embodiment of the invention can execute the instruction checking method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
EXAMPLE III
FIG. 4 shows a schematic block diagram of an electronic device 30 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the electronic device 30 includes at least one processor 31, and a memory communicatively connected to the at least one processor 31, such as a Read Only Memory (ROM)32, a Random Access Memory (RAM)33, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 31 may perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM)32 or the computer program loaded from a storage unit 38 into the Random Access Memory (RAM) 33. In the RAM 33, various programs and data necessary for the operation of the electronic apparatus 30 can also be stored. The processor 31, the ROM 32, and the RAM 33 are connected to each other via a bus 34. An input/output (I/O) interface 35 is also connected to bus 34.
A plurality of components in the electronic device 30 are connected to the I/O interface 35, including: an input unit 36 such as a keyboard, a mouse, etc.; an output unit 37 such as various types of displays, speakers, and the like; a storage unit 38 such as a magnetic disk, an optical disk, or the like; and a communication unit 39 such as a network card, modem, wireless communication transceiver, etc. The communication unit 39 allows the electronic device 30 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
The processor 31 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 31 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. The processor 31 performs the various methods and processes described above, such as the instruction check method:
acquiring an instruction to be checked, wherein the instruction to be checked comprises a byte array and an initial check byte;
determining a target check byte according to the byte array, wherein the target check byte comprises: a first check byte and a second check byte;
if the instruction to be checked is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, adjusting the instruction to be checked according to the first check byte and the second check byte to obtain a target instruction.
In some embodiments, the instruction verification method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 38. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 30 via the ROM 32 and/or the communication unit 39. When the computer program is loaded into the RAM 33 and executed by the processor 31, one or more steps of the instruction verification method described above may be performed. Alternatively, in other embodiments, the processor 31 may be configured to perform the instruction checking method by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired result of the technical solution of the present invention can be achieved.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An instruction checking method, comprising:
acquiring an instruction to be checked, wherein the instruction to be checked comprises a byte array and an initial check byte;
determining a target check byte according to the byte array, wherein the target check byte comprises: a first check byte and a second check byte;
if the instruction to be checked is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, adjusting the instruction to be checked according to the first check byte and the second check byte to obtain a target instruction.
2. The method of claim 1, wherein the initial check bytes comprise a first initial check byte and a second initial check byte;
correspondingly, if the instruction to be checked is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte, adjusting the instruction to be checked according to the first check byte and the second check byte to obtain a target instruction, including:
if the first check byte is not the same as the first initial check byte and/or the second check byte is not the same as the second initial check byte, determining that the instruction to be checked is an error instruction;
and performing covering operation on the initial check byte by using the first check byte and the second check byte to obtain a target instruction.
3. The method of claim 2, further comprising:
and if the first check byte is the same as the first initial check byte and the second check byte is the same as the second initial check byte, determining that the instruction to be checked is a correct instruction.
4. The method of claim 1, after obtaining the instruction to be verified, further comprising:
judging whether the byte number of the byte array in the instruction to be checked is smaller than a byte number threshold value or not;
if the byte number of the byte array in the instruction to be checked is smaller than a byte number threshold, determining the difference value between the byte number threshold and the byte number as the number of missing bytes;
and completing the instruction to be checked according to the number of the missing bytes and a preset value.
5. The method of claim 1, wherein determining a target check byte from the array of bytes comprises:
determining a first check byte according to odd-numbered bit bytes in the byte array;
determining a second check byte according to even-numbered bytes in the byte array;
and determining a target check byte according to the first check byte and the second check byte.
6. The method of claim 5, wherein determining a first check byte from odd-numbered bytes in the byte array comprises:
performing XOR operation on a first odd-numbered bit byte and a second odd-numbered bit byte in the byte array to obtain a first odd-numbered XOR result;
performing exclusive-or operation on the N odd-numbered bit exclusive-or result and an N +2 odd-numbered bit byte to obtain an N +1 odd-numbered bit exclusive-or result, wherein N is 1, 2, 3, 4 and 5;
the sixth odd-bit xor result is determined to be the first check byte.
7. The method of claim 5, wherein determining a second parity byte from even-numbered bytes in the byte array comprises:
carrying out XOR operation on a first even-numbered bit and a second even-numbered bit in the byte array to obtain a first even-numbered XOR result;
performing exclusive-or operation on the nth even bit exclusive-or result and an (N + 2) th even bit byte to obtain an (N + 1) th even bit exclusive-or result, wherein N is 1, 2, 3, 4 and 5;
the sixth even bit xor result is determined as the second parity byte.
8. An instruction checking device, comprising:
the device comprises an acquisition module, a verification module and a verification module, wherein the acquisition module is used for acquiring an instruction to be verified, and the instruction to be verified comprises a byte array and an initial verification byte;
a first determining module, configured to determine a target check byte according to the byte array, where the target check byte includes: a first check byte and a second check byte;
and the adjusting module is used for adjusting the instruction to be checked according to the first check byte and the second check byte to obtain a target instruction if the instruction to be checked is determined to be an error instruction according to the first check byte, the second check byte and the initial check byte.
9. An electronic device, characterized in that the electronic device comprises:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the instruction checking method of any one of claims 1-7.
10. A computer-readable storage medium storing computer instructions for causing a processor to perform the instruction verification method of any one of claims 1-7 when executed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210802484.6A CN115081429A (en) | 2022-07-07 | 2022-07-07 | Instruction checking method, device, equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210802484.6A CN115081429A (en) | 2022-07-07 | 2022-07-07 | Instruction checking method, device, equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115081429A true CN115081429A (en) | 2022-09-20 |
Family
ID=83258033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210802484.6A Pending CN115081429A (en) | 2022-07-07 | 2022-07-07 | Instruction checking method, device, equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115081429A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117492405A (en) * | 2024-01-02 | 2024-02-02 | 东方电气风电股份有限公司 | Verification method for wind turbine generator control system based on field bus |
-
2022
- 2022-07-07 CN CN202210802484.6A patent/CN115081429A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117492405A (en) * | 2024-01-02 | 2024-02-02 | 东方电气风电股份有限公司 | Verification method for wind turbine generator control system based on field bus |
| CN117492405B (en) * | 2024-01-02 | 2024-03-08 | 东方电气风电股份有限公司 | Verification method for wind turbine generator control system based on field bus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109756568B (en) | File processing method and device and computer readable storage medium | |
| CN112597754A (en) | Text error correction method and device, electronic equipment and readable storage medium | |
| CN112380046B (en) | Calculation result verification method, system, device, equipment and storage medium | |
| CN115081429A (en) | Instruction checking method, device, equipment and storage medium | |
| CN112818387A (en) | Method, apparatus, storage medium, and program product for model parameter adjustment | |
| CN110737548A (en) | Data request method and server | |
| CN115547508B (en) | Data correction method, data correction device, electronic equipment and storage medium | |
| CN110175128B (en) | Similar code case acquisition method, device, equipment and storage medium | |
| CN116303013A (en) | Source code analysis method, device, electronic equipment and storage medium | |
| CN115618777A (en) | File generation method, device, equipment and storage medium | |
| CN115482869A (en) | Error injection testing method and device, electronic equipment and storage medium | |
| CN115617800A (en) | Data reading method and device, electronic equipment and storage medium | |
| CN113313268A (en) | Federal learning-based prediction method and device, storage medium and remote sensing equipment | |
| CN114564336A (en) | Data consistency checking method, device, equipment and storage medium | |
| CN108269004B (en) | Product life analysis method and terminal equipment | |
| CN114116688A (en) | Data processing and data quality inspection method, device and readable storage medium | |
| WO2021087662A1 (en) | Memory allocation method and apparatus, terminal, and computer readable storage medium | |
| CN115268880A (en) | Code generation method and device, electronic equipment and storage medium | |
| CN113760765B (en) | Code testing method and device, electronic equipment and storage medium | |
| CN115098405B (en) | Software product evaluation method and device, electronic equipment and storage medium | |
| CN114416168A (en) | Version number processing method and device | |
| CN110909445A (en) | Method and device for calculating opening rate of equipment, electronic equipment and storage medium | |
| CN117033227A (en) | Distributed database testing method, device, equipment and medium | |
| CN115567624A (en) | Message processing method and device, electronic equipment and medium | |
| CN114924976A (en) | Code detection method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |