CN115098405B - Software product evaluation method and device, electronic equipment and storage medium - Google Patents
Software product evaluation method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a software product evaluation method and device, electronic equipment and a storage medium. The method comprises the following steps: obtaining at least one netlist file, and determining circuit resource data corresponding to each netlist file; respectively determining the target time of the EDA software to be evaluated for operating each netlist file and the reference time of the EDA software for operating each netlist file; and evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time. The scheme of the embodiment of the invention can quickly and accurately evaluate the performance of the EDA software to be tested.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to a software product evaluation method and device, electronic equipment and a storage medium.
Background
Electronic Design Automation (EDA) software of Field Programmable Gate Array (FPGA), which has a main function of converting a circuit Design into a netlist file, and then performing a series of processes such as packing, layout, wiring, code generation and the like.
Currently, how to evaluate EDA software and determine the performance of each EDA software is a key issue of research in the industry.
Disclosure of Invention
The embodiment of the invention provides a software product evaluation method, a software product evaluation device, electronic equipment and a storage medium, which are used for quickly and accurately evaluating the performance of EDA software to be tested.
According to an aspect of an embodiment of the present invention, there is provided an evaluation method of a software product, including:
obtaining at least one netlist file, and determining circuit resource data corresponding to each netlist file;
respectively determining the target time of the Electronic Design Automation (EDA) software to be evaluated for running each netlist file and the reference time of the target EDA software for running each netlist file;
and evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time.
According to another aspect of the embodiments of the present invention, there is provided an evaluation apparatus of a software product, including:
the circuit resource number determining module is used for acquiring at least one netlist file and determining circuit resource data corresponding to each netlist file;
the time determination module is used for respectively determining the target time of the Electronic Design Automation (EDA) software to be evaluated for running each netlist file and the reference time of the target EDA software for running each netlist file;
and the evaluation module is used for evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time.
According to another aspect of the embodiments of the present invention, there is provided an electronic apparatus, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,
the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the method of assessing a software product according to any one of the embodiments of the present invention.
According to another aspect of the embodiments of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the method for evaluating a software product according to any one of the embodiments of the present invention when the computer instructions are executed.
According to the technical scheme of the embodiment of the invention, at least one netlist file is obtained, and circuit resource data corresponding to each netlist file is determined; respectively determining the target time of the Electronic Design Automation (EDA) software to be evaluated for running each netlist file and the reference time of the target EDA software for running each netlist file; and evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time, so that the performance of the EDA software to be evaluated can be quickly and accurately evaluated.
It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present invention, nor are they intended to limit the scope of the embodiments of the present invention. Other features of embodiments of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings may be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for evaluating a software product according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for evaluating a software product according to a second embodiment of the present invention;
FIG. 3 is a flowchart of a method for evaluating a software product according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an evaluation device for a software product according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device implementing the evaluation method of the software product according to the embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the embodiments of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without any creative efforts shall fall within the protection scope of the embodiments of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the embodiments of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example one
Fig. 1 is a flowchart of a method for evaluating a software product according to an embodiment of the present invention, where the embodiment is applicable to a case of testing a software product such as EDA, the method may be executed by an evaluation apparatus of the software product, the evaluation apparatus of the software product may be implemented in a form of hardware and/or software, and the evaluation apparatus of the software product may be configured in an electronic device such as a computer or a server. Specifically, referring to fig. 1, the method specifically includes the following steps:
The netlist refers to a description mode for describing the connection condition of the digital circuit by using basic logic gates. The logic gate array has the appearance of a netlist, and is called a netlist. In the art, the electronic circuit may be converted to a netlist file by EDA software, it being understood that the netlist file corresponds one-to-one to the electronic circuit.
In an optional implementation manner of this embodiment, after the netlist files corresponding to the electronic circuits are obtained, circuit resource data corresponding to each netlist file may be further determined. For example, the circuit resource data of the first netlist file may be "5 CLB modules, 6 Memory modules, 7 DSP modules, 10 IO modules", and the like, which is not limited in this embodiment.
And 120, respectively determining the target time of the EDA software to be evaluated for running each netlist file and the reference time of the target EDA software for running each netlist file.
The EDA software to be evaluated is a software product to be evaluated in the embodiment of the invention, can be designed for independent research and development, can also be an existing software product on the market, and is not limited in the embodiment; the target EDA software may be a software product with complete performance, such as EDA software that is commercially available and is not limited in this embodiment. It should be noted that the number of the EDA software to be evaluated designed in this embodiment may be one or multiple, and is not limited in this embodiment.
In an optional implementation manner of this embodiment, after obtaining the plurality of netlist files, the to-be-evaluated EDA software and the target EDA software may run the netlist files respectively, and further, the target time consumed for the to-be-evaluated EDA software to run each netlist file and the target time consumed for the target EDA software to run each netlist file may be obtained respectively.
Illustratively, if three netlist files are obtained, the target time consumed by the EDA software to be evaluated to run the three netlist files can be 2 seconds, 3 seconds and 10 seconds respectively; the target EDA software may run the three netlist files for target time of 3 seconds, 4 seconds, and 15 seconds, respectively.
And step 130, evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time.
In an optional implementation manner of this embodiment, after the target time when the EDA software to be evaluated runs each netlist file and the reference time when the target EDA software runs each netlist file are respectively determined, the performance of the EDA software to be evaluated may be further evaluated according to the circuit resource data, each target time and each reference time corresponding to each netlist file.
In an optional implementation manner of this embodiment, the evaluating the performance of the EDA software to be evaluated according to each circuit resource data, each target time, and each reference time may include: when the circuit resource data are the same and the relation between each target time and each reference time meets the preset relation, determining that the performance of the EDA software to be evaluated is superior to that of the target EDA software; and when the circuit resource data are different, if the circuit resource data of the first netlist file are larger than the circuit resource data of the second netlist file, and the target time of the EDA software to be evaluated running the first netlist file is shorter than the reference time of the target EDA software running the first netlist file, determining that the performance of the EDA software to be evaluated is better than that of the target EDA software.
The preset relation can be that the times that each target time is greater than each reference time is greater than a set threshold, wherein the set threshold is related to the number of the netlist files; for example, if the number of netlist files is 100, the set threshold may be 60 or 70, etc.; for example, if the number of times that the target time is greater than the reference time is 80 (greater than the set threshold value 70), the relationship between each target time and each reference time satisfies the preset relationship.
In an optional implementation manner of this embodiment, if the number of the obtained netlist files is 100, the circuit resource data of each netlist file is the same, and the relationship between each target time and each reference time satisfies the preset relationship, it may be determined that the performance of the EDA software to be evaluated is better than that of the target EDA software.
In another optional implementation manner of this embodiment, if the number of the obtained netlist files is 100 and the circuit resource data of each netlist file is different, for example, the first netlist file includes 10 CLB modules, the second netlist file includes 8 CLB modules, and the rest circuit resource data are the same; at this time, if the target time (for example, 5 seconds) consumed by the EDA software to be evaluated to run the first netlist file is less than the reference time (for example, 7 seconds) consumed by the target EDA software to run the second netlist file, it may be determined that the performance of the EDA software to be evaluated is better than that of the target EDA software at this time.
According to the technical scheme of the embodiment of the invention, at least one netlist file is obtained, and circuit resource data corresponding to each netlist file is determined; respectively determining the target time of the Electronic Design Automation (EDA) software to be evaluated for operating each netlist file and the reference time of the target EDA software for operating each netlist file; and evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time, so that the performance of the EDA software to be evaluated can be quickly and accurately evaluated.
Example two
Fig. 2 is a flowchart of an evaluation method for a software product according to a second embodiment of the present invention, where this embodiment is a further refinement of the foregoing technical solutions, and the technical solutions in this embodiment may be combined with various alternatives in one or more of the foregoing embodiments. As shown in fig. 2, the evaluation method of the software product may include the steps of:
In an optional implementation manner of this embodiment, after obtaining each netlist file, a configuration constraint condition file corresponding to each netlist file may be further generated; the configuration constraint file may include, but is not limited to: a binning constraint, a layout constraint, a routing constraint, a code matching constraint, and the like, which are not limited in this embodiment. The advantage of this is that it can ensure that the calling constraint conditions are the same when different EDA software runs the netlist file of the same circuit.
Furthermore, the obtained netlist files and the configuration constraint condition files corresponding to the netlist files can be analyzed to obtain circuit resource data corresponding to the netlist files; illustratively, after the target netlist file is obtained, the target netlist file and the configuration constraint condition file corresponding to the target netlist file can be analyzed, so that circuit resource data corresponding to the target netlist file is obtained; the target netlist file may be any netlist file, which is not limited in this embodiment.
In an optional implementation manner of this embodiment, after analyzing each netlist file and the configuration constraint condition file corresponding to each netlist file respectively to obtain circuit resource data corresponding to each netlist file, further, target time for the EDA software to be evaluated to sequentially run each netlist file may be determined by running each obtained netlist file through the EDA software to be evaluated; the reference times for each netlist file are run in sequence through the target EDA software. It is understood that, in the present embodiment, the target time and the reference time do not refer to one time, but include a plurality of times; for example, the target time may be 3 seconds for the EDA software to be evaluated to run the first netlist file, 5 seconds for the second netlist file, 10 seconds for the third netlist file, and the like, which is not limited in this embodiment.
And 240, evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time.
According to the scheme of the embodiment, after the netlist files are obtained, the configuration constraint condition files corresponding to the netlist files can be further generated, the netlist files and the configuration constraint condition files corresponding to the netlist files are analyzed respectively, circuit resource data corresponding to the netlist files are obtained, it can be guaranteed that invoked constraint conditions are the same when different EDA software runs the netlist files of the same circuit, and the circuit resource data corresponding to each netlist file can be accurately obtained.
EXAMPLE III
Fig. 3 is a flowchart of an evaluation method for a software product according to a third embodiment of the present invention, which is a further refinement of the above technical solutions, and the technical solutions in this embodiment may be combined with various alternatives in one or more of the above embodiments. As shown in fig. 3, the evaluation method of the software product may include the steps of:
at least one netlist file is obtained, and circuit resource data corresponding to each netlist file is determined 310.
And step 320, determining bottom layer command files corresponding to the sub-processes in the netlist files, and determining time parameters for operating the sub-processes according to the bottom layer command files.
In this embodiment, each sub-flow within the netlist file may include at least one of: boxing, laying out, wiring, generating a code matching file and the like.
In an optional implementation manner of this embodiment, after at least one netlist file is obtained, bottom layer command files corresponding to sub-processes in each netlist file may be determined, and each bottom layer command file is run, so as to determine time consumed by running each sub-process, which is referred to as a time parameter in this embodiment.
In an example of this embodiment, bottom command files corresponding to the four sub-processes of boxing, layout, wiring and generating a code matching file in the target netlist file may be respectively determined in this embodiment, and the four bottom command files are sequentially run, so as to determine a time parameter of the decoration sub-process, a time parameter of the layout sub-process, a time parameter of the wiring sub-process and a time parameter of the generating of the code matching file sub-process.
In an optional implementation manner of this embodiment, determining a bottom layer command file corresponding to each sub-process in each netlist file, and determining a time parameter for running each sub-process according to each bottom layer command file may include: determining first bottom command files corresponding to the sub-processes in the netlist files according to the EDA software to be evaluated, and determining first time parameters for operating the sub-processes according to the first bottom command files; and determining a second bottom command file corresponding to each sub-process in each netlist file according to the target EDA software, and determining a second time parameter for operating each sub-process according to each second bottom command file.
For example, a first bottom file corresponding to each sub-process in the first netlist file may be determined according to the EDA software to be evaluated, and the first bottom file may be operated to obtain a first time parameter consumed by operating each sub-process of the first netlist file; for example, the first time parameter of the packing sub-flow running the first netlist file is 100 seconds, the first time parameter of the layout sub-flow running the first netlist file is 110 seconds, the first time parameter of the wiring sub-flow running the first netlist file is 120 seconds, and the first time parameter of the generating code-matching file sub-flow running the first netlist file is 105 seconds; determining second bottom layer files corresponding to the sub-processes in the second netlist file according to the target EDA software, and operating the second bottom layer files to obtain second time parameters consumed by operating the sub-processes of the second netlist file; for example, the second time parameter for running the packing sub-flow of the second netlist file is 110 seconds, the second time parameter for running the placement sub-flow of the second netlist file is 112 seconds, the second time parameter for running the routing sub-flow of the second netlist file is 123 seconds, and the second time parameter for running the generate-to-match-file sub-flow of the second netlist file is 1085 seconds.
And 330, evaluating the performance of the EDA software to be evaluated according to the circuit resource data and the time parameter.
In an optional implementation manner of this embodiment, after determining the bottom layer command file corresponding to each sub-process in each netlist file and determining the time parameter for operating each sub-process according to each bottom layer command file, the performance of the EDA software for evaluation may be further evaluated according to the circuit resource data and the time parameter.
In an optional implementation manner of this embodiment, the evaluating, according to the circuit resource data and the time parameter, the performance of the EDA software to be evaluated may include: when the circuit resource data are the same and the relationship between each first time parameter and each second time parameter meets a second preset relationship, determining that the performance of the EDA software to be evaluated is superior to that of the target EDA software; and when the circuit resource data are different, if the circuit resource data of the first netlist file are larger than the circuit resource data of the second netlist file, and the first time parameter for the first bottom layer command to operate each sub-process is smaller than the second time parameter for the second bottom layer file to operate each sub-process, determining that the performance of the EDA software to be evaluated is superior to that of the target EDA software.
The second preset relationship may be that the number of times that each first time parameter is greater than each second time parameter is greater than a set threshold, where the set threshold is related to the number of netlist file sub-processes; for example, if the number of netlist files is 100, that is, the number of netlist file sub-processes is 400, the set threshold may be 360 or 370, etc.; for example, if the number of times that the first time parameter is greater than the second time parameter is 380 (greater than the set threshold 370), the relationship between each first time parameter and each second time parameter satisfies the predetermined relationship.
In an optional implementation manner of this embodiment, if the number of the obtained netlist files is 100, the number of the netlist file sub-processes is 400, the circuit resource data of each netlist file is the same, and the relationship between each first time parameter and each second time parameter satisfies the second preset relationship, it may be determined that the performance of the EDA software to be evaluated is superior to that of the target EDA software.
In another optional implementation manner of this embodiment, if the number of the obtained netlist files is 100, the number of the netlist file sub-processes is 400, and the circuit resource data of each netlist file is different, for example, the first netlist file includes 10 CLB modules, the second netlist file includes 8 CLB modules, and the rest circuit resource data are the same; at this time, if the first time parameter (for example, 100 seconds, 90 seconds, 110 seconds and 120 seconds) of the first underlying command to run each sub-flow is smaller than the second time parameter (for example, 110 seconds, 98 seconds, 117 seconds and 126 seconds) of the second underlying file to run each sub-flow, it can be determined that the performance of the EDA software to be evaluated is better than that of the target EDA software.
According to the scheme of the embodiment, at least one netlist file is obtained, and circuit resource data corresponding to each netlist file is determined; determining a bottom layer command file corresponding to each sub-process in each netlist file, and determining a time parameter for operating each sub-process according to each bottom layer command file; according to the circuit resource data and the time parameters, the performance of the EDA software to be evaluated is evaluated, the consumed single time of each sub-process can be determined, and a direction and a reference are provided for the improvement of the flow and the performance of the EDA software, so that the performance and the efficiency of the EDA software are improved.
For better understanding of the embodiments of the present invention, the following is a specific example for explaining the embodiments of the present invention, which mainly includes the following:
step 1, configuring constraint conditions
In order to avoid the influence of different parameter configurations on the process running time, constraint conditions including binning constraint, layout constraint, wiring constraint and code matching constraint are configured for the netlist file of each circuit before each process command is executed, and are stored in the constraint file, so that the same constraint condition is called when different EDAs run the netlist files of the same circuit.
Step 2, counting main resource data of the electronic circuit
The netlist file of the electronic circuit contains the following resource contents: a CLB module, a Memory module, a DSP module, an IO module, and a constrained number of clock networks. The size of these resources is an important factor that affects how long the sub-process takes. By parsing the netlist file and the constraint file, the resource information can be extracted as reference data for the time report.
Step 3, disassembling and operating the sub-process of the EDA software
General EDA software will perform box loading, layout, wiring to the netlist file of the circuit, then generate the assembly code file to output, and the execution of these sub-processes can be implemented by calling the bottom layer command file, so the invention will extract the bottom layer command files of these several sub-processes respectively, and add the time mark when executing each command file, and store into the readable result file.
Step 4, generating a time test report
Extracting the time information of each sub-process from the result file in the step 3, calculating the time consumed by each process and the total time consumed by running the whole netlist file, and writing the time information into a report; and then adding the resource information acquired in the step 2 as a parameter into the report. And running the netlist file in batches to generate a running-time test report of the circuit netlist file. The report format is adjustable according to the actual situation, and the following is a test report sample of transverse and longitudinal comparison.
Transverse comparison test report: different EDA software combines the steps, the same circuit netlist file is run in batch, the average consumed time of each flow is calculated, and a time test report of single EDA transverse comparison can be generated; in one example of this embodiment, the EDA software runtime lateral test report may be as shown in Table 1:
TABLE 1 EDA software runtime transverse test report (units: seconds)
Longitudinal comparison test report: combining the same EDA software with the above steps, operating different circuit netlist files, and generating a time test report (EDA-number: representing EDA software tools of different manufacturers) for longitudinal comparison according to the obtained result; in one example of this embodiment, the EDA software runtime longitudinal test report may be as shown in Table 2:
TABLE 2 EDA software runtime longitudinal test report (unit: seconds)
The test report generated in the scheme of the embodiment of the invention can embody different resource amounts, total time consumed under different constraint conditions and time consumed by each sub-process when the FPGA EDA software runs the electronic circuit netlist file, and provide directions and references for improving the process and performance of the FPGA EDA software, thereby improving the performance and efficiency of the FPGA EDA software.
In the technical scheme of the embodiment of the invention, the acquisition, storage, application and the like of the personal information (such as face information, voice information and the like) of the related user all accord with the regulations of related laws and regulations without violating the customs of public order.
Example four
Fig. 4 is a schematic structural diagram of an evaluation device for a software product according to a fourth embodiment of the present invention. As shown in fig. 4, the apparatus includes: a circuit resource number determination module 410, a time determination module 420, and an evaluation module 430.
A circuit resource number determining module 410, configured to obtain at least one netlist file, and determine circuit resource data corresponding to each netlist file;
the time determining module 420 is configured to determine target time for the electronic design automation EDA software to be evaluated to run each netlist file and reference time for the target EDA software to run each netlist file respectively;
and the evaluation module 430 is configured to evaluate the performance of the EDA software to be evaluated according to each circuit resource data, each target time, and each reference time.
According to the scheme of the embodiment, at least one netlist file is obtained through a circuit resource number determining module, and circuit resource data corresponding to each netlist file is determined; respectively determining the target time of the EDA software to be evaluated for operating each netlist file and the reference time of the target EDA software for operating each netlist file through a time determination module; the performance of the EDA software to be evaluated is evaluated through the evaluation module according to the circuit resource data, the target time and the reference time, and the performance of the EDA software to be evaluated can be quickly and accurately evaluated.
In an optional implementation manner of the embodiment of the present invention, the circuit resource number determining module 410 is specifically configured to generate configuration constraint condition files corresponding to the netlist files;
and analyzing each netlist file and the configuration constraint condition file corresponding to each netlist file respectively to obtain circuit resource data corresponding to each netlist file.
In an optional implementation manner of the embodiment of the present invention, the time determining module 420 is specifically configured to sequentially run each netlist file through the EDA software to be evaluated, and determine each target time;
and sequentially running the netlist files through the target EDA software to determine the reference time.
In an optional implementation manner of the embodiment of the present invention, the time determining module 420 is specifically configured to determine that the performance of the EDA software to be evaluated is better than that of the target EDA software when the data of each circuit resource is the same and the relationship between each target time and each reference time satisfies a preset relationship;
when the circuit resource data are different, if the circuit resource data of the first netlist file are larger than the circuit resource data of the second netlist file, and the target time of the EDA software to be evaluated for running the first netlist file is shorter than the reference time of the target EDA software for running the first netlist file, determining that the performance of the EDA software to be evaluated is better than that of the target EDA software.
In an optional implementation manner of the embodiment of the present invention, the method further includes:
the time parameter determining module is used for determining bottom layer command files corresponding to the sub-processes in the netlist files and determining time parameters for operating the sub-processes according to the bottom layer command files;
and the second evaluation module is used for evaluating the performance of the EDA software to be evaluated according to the circuit resource data and the time parameter.
In an optional implementation manner of the embodiment of the present invention, the time parameter determining module is specifically configured to determine, according to the EDA software to be evaluated, a first bottom command file corresponding to each sub-process in each netlist file, and determine, according to each first bottom command file, a first time parameter for operating each sub-process;
determining a second bottom command file corresponding to each sub-process in each netlist file according to target EDA software, and determining a second time parameter for operating each sub-process according to each second bottom command file;
each sub-flow within the netlist file includes at least one of: boxing, laying out, wiring and generating a code matching file.
In an optional implementation manner of the embodiment of the present invention, the second evaluation module is specifically configured to determine that the performance of the EDA software to be evaluated is better than that of the target EDA software when the data of each circuit resource is the same and the relationship between each first time parameter and each second time parameter meets a second preset relationship;
and when the circuit resource data are different, if the circuit resource data of the first netlist file are larger than the circuit resource data of the second netlist file, and the first time parameter for the first bottom layer command to operate each sub-process is smaller than the second time parameter for the second bottom layer file to operate each sub-process, determining that the performance of the EDA software to be evaluated is superior to that of the target EDA software.
The software product evaluation device provided by the embodiment of the invention can execute the software product evaluation method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
EXAMPLE five
FIG. 5 illustrates a block diagram of an electronic device 10 that may be used to implement embodiments of the present invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of embodiments of the inventions described and/or claimed herein.
As shown in fig. 5, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from a storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the electronic apparatus 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
A number of components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
In some embodiments, the evaluation method of the software product may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the evaluation method of the software product described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured by any other suitable means (e.g., by means of firmware) to perform the evaluation method of the software product.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
Computer programs for implementing methods of embodiments of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.
In the context of embodiments of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user may provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the embodiments of the present invention may be executed in parallel, may be executed sequentially, or may be executed in different orders, as long as the desired result of the technical solution of the embodiments of the present invention can be achieved, which is not limited herein.
The above detailed description does not limit the scope of the embodiments of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modifications, equivalents, and improvements made within the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (9)
1. A method for evaluating a software product, comprising:
obtaining at least one netlist file, and determining circuit resource data corresponding to each netlist file;
respectively determining the target time of the Electronic Design Automation (EDA) software to be evaluated for running each netlist file and the reference time of the target EDA software for running each netlist file;
evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time;
the evaluating the performance of the EDA software according to the circuit resource data, the target time and the reference time comprises the following steps:
when the data of the circuit resources are the same and the relation between the target time and the reference time meets a preset relation, determining that the performance of the EDA software to be evaluated is superior to that of the target EDA software;
when the circuit resource data are different, if the circuit resource data of the first netlist file are larger than the circuit resource data of the second netlist file, and the target time of the EDA software to be evaluated for running the first netlist file is shorter than the reference time of the target EDA software for running the first netlist file, determining that the performance of the EDA software to be evaluated is better than that of the target EDA software.
2. The method of claim 1, wherein determining circuit resource data corresponding to each of the netlist files comprises:
generating configuration constraint condition files corresponding to the netlist files;
and analyzing each netlist file and the configuration constraint condition file corresponding to each netlist file respectively to obtain circuit resource data corresponding to each netlist file.
3. The method according to claim 1, wherein the separately determining the target time of the Electronic Design Automation (EDA) software to be evaluated to run each netlist file and the reference time of the target EDA software to run each netlist file comprises:
sequentially running each netlist file through the EDA software to be evaluated to determine each target time;
and sequentially running the netlist files through the target EDA software to determine the reference time.
4. The method of claim 1, further comprising:
determining bottom layer command files corresponding to the sub-processes in the netlist files, and determining time parameters for operating the sub-processes according to the bottom layer command files;
and evaluating the performance of the EDA software to be evaluated according to the circuit resource data and the time parameter.
5. The method of claim 4, wherein determining an underlying command file corresponding to each sub-process in each netlist file and determining a time parameter for running each sub-process according to each underlying command file comprises:
determining a first bottom command file corresponding to each sub-process in each netlist file according to the EDA software to be evaluated, and determining a first time parameter for operating each sub-process according to each first bottom command file;
determining second bottom-layer command files corresponding to the sub-processes in the netlist files according to target EDA software, and determining second time parameters for operating the sub-processes according to the second bottom-layer command files;
each sub-process within the netlist file includes at least one of: boxing, laying out, wiring and generating a code matching file.
6. The method as claimed in claim 5, characterized in that said evaluating the performance of the EDA software to be evaluated according to the circuit resource data and the time parameter comprises:
when the circuit resource data are the same and the relationship between each first time parameter and each second time parameter meets a second preset relationship, determining that the performance of the EDA software to be evaluated is superior to that of the target EDA software;
and when the circuit resource data are different, if the circuit resource data of the first netlist file are larger than the circuit resource data of the second netlist file, and the first time parameter for the first bottom layer command to operate each sub-process is smaller than the second time parameter for the second bottom layer file to operate each sub-process, determining that the performance of the EDA software to be evaluated is superior to that of the target EDA software.
7. An evaluation device for a software product, comprising:
the circuit resource number determining module is used for acquiring at least one netlist file and determining circuit resource data corresponding to each netlist file;
the time determining module is used for respectively determining the target time of the Electronic Design Automation (EDA) software to be evaluated for running each netlist file and the reference time of the target EDA software for running each netlist file;
the evaluation module is used for evaluating the performance of the EDA software to be evaluated according to the circuit resource data, the target time and the reference time;
the evaluation module is specifically configured to determine that the performance of the EDA software to be evaluated is superior to that of the target EDA software when the data of the circuit resources are the same and the relationship between the target time and the reference time satisfies a preset relationship;
when the circuit resource data are different, if the circuit resource data of the first netlist file are larger than the circuit resource data of the second netlist file, and the target time of the EDA software to be evaluated for running the first netlist file is shorter than the reference time of the target EDA software for running the first netlist file, determining that the performance of the EDA software to be evaluated is superior to that of the target EDA software.
8. An electronic device, characterized in that the electronic device comprises:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of assessing a software product of any one of claims 1-6.
9. A computer-readable storage medium storing computer instructions for causing a processor to perform a method of evaluating a software product according to any one of claims 1 to 6 when executed.
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| CN111400994A (en) * | 2018-12-29 | 2020-07-10 | 广东高云半导体科技股份有限公司 | Netlist form verification method and device, computer equipment and storage medium |
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