JPH087693Y2 - APD bias voltage control circuit - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an APD bias voltage control circuit, and in particular to DC / DC.
The present invention relates to a technique for reducing the influence of the output impedance of a conversion circuit and improving the maximum light receiving sensitivity of a light receiving unit.

[Conventional technology]

Conventionally, the APD bias voltage control circuit of this type of optical receiver has a DC / DC conversion circuit 3 as shown in FIG. 2 so as to make a received weak signal as large as possible and also make noise small. To obtain the optimum current multiplication factor,
The gain control voltage detected by the output signal amplitude detection circuit 14 is supplied to the base of the transistor 5 at the point b to control the APD bias voltage.

In the conventional APD bias voltage control circuit described above, the optimum current multiplication factor is determined when the minimum photosensitivity is obtained.
The bias voltage is as shown by line 1 in FIG.

The gain control signal for obtaining the optimum current multiplication factor is b in FIG.
The bias voltage 12 which is input to the base of the transistor 5 at the point and required by the DC / DC conversion circuit 3 is applied to the APD 1.
Further, the optical receiver controls not only the multiplication factor of the APD but also the gain of the equalizing amplifier 2 in order to increase the dynamic range. In other words, the bias voltage 12 of the APD and the gain of the equalizing amplifier 2 are also lowered in order to operate normally even when the optical input power is large. At this time, the gain control voltage at point b becomes too low and APD
The bias voltage 12 to obtain the required response speed is DC / D
Since it cannot be obtained from the C conversion circuit 3, in the circuit shown in FIG.
Even if the gain control voltage at the point b drops too much, the clamp circuit 13 constituted by means does not lower the bias voltage 12 for obtaining the response speed required by the APD.

[Problems to be solved by the invention]

However, when the optical input power increases, the photocurrent I _{1 of the} APD also increases. At this time, since the output impedance at the output point d of the DC / DC conversion circuit 3 is not sufficiently small,
The voltage drop at the point d caused by the increase in the photocurrent I ₁ of the APD cannot be ignored, as when the received light power is weak. When the received light level is high, the DC / DC conversion circuit 3
Since the current consumption of the diode also increases, the current flowing through the diode 6 and the variable resistor 8 also increases, resulting in a decrease in the potential at the point e and a decrease in the voltage at the point c. For this reason, the potential at the output point d of the DC / DC conversion circuit 3 is lowered, and the bias voltage 12 for obtaining the response speed required by the APD is lowered to stop the operation. In other words, the maximum light receiving level of the optical receiver is mainly due to the output impedance of the DC / DC conversion circuit 3 and the internal resistance of the variable resistor 8, and the input c of the DC / DC conversion circuit 3 is affected.
Clamp circuit composed of points, that is, diodes 6
It has the drawback that the output voltage of 13 drops.

The above drawbacks will be described using the relationship between the received light power and the APD bias voltage shown in FIG. The line 1 shows the relationship between the APD bias voltage and the received light power for obtaining the optimum current multiplication factor at the minimum received light level of the APD. The APD bias voltage 9 is a voltage for obtaining a response speed required for APD. In the circuit diagram shown in FIG. 2, the maximum light receiving level without the clamp circuit 3 composed of the resistor 7, the variable resistor 8 and the diodes 6 and 9 is the position 6 in FIG. . Clamp circuit 3
Does not lower the voltage at the input point c of the DC / DC conversion circuit, the APD bias voltage maintains the voltage on line 2 in FIG. 3, but actually the received light power increases and , APD current I ₁ increases, the influence of the output impedance of the DC / DC conversion circuit cannot be ignored, and the voltage drops as shown by line 3, and the maximum light reception level is at the position of 7. . The dotted line 5 is when the output impedance of the DC / DC conversion circuit 3 is zero.

An object of the present invention is to provide an APD bias voltage control circuit which can secure the APD bias voltage required for a response operation to some extent so as to obtain the characteristic 2 in FIG. 3, that is, even when the optical input power increases. It is in.

[Means for solving problems]

The APD bias voltage control circuit of the present invention is an optical signal receiving circuit using an avalanche photodiode (hereinafter abbreviated as APD) as a photoelectric conversion element, and an output signal of an equalizing amplifier which receives an electric output signal of the APD as an input. DC / DC that detects amplitude and DC / DC that supplies bias voltage to the APD
A conversion circuit; a first transistor having the detection circuit output as a base input; and a clamp circuit composed of a second transistor having a sliding terminal of the variable resistor connected to the base, The transistor and the emitter of the second transistor are connected to each other and are connected to the input of the DC / DC conversion circuit.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit showing an embodiment of the present invention.

In the figure, the equalization amplifier 2 and the output signal amplitude detection circuit 14
The gain control voltage generated by is supplied to the DC / DC conversion circuit 3 via the transistor 5. DC / DC conversion circuit 3
Applies a bias voltage to APD1 that provides the optimum current multiplication factor of APD1 with the minimum light receiving sensitivity of the optical receiver. That is,
The signal from the light receiving element APD is as large as possible, and noise is made as small as possible. The relationship between the APD bias voltage and the optical input power at this time is as shown by line 1 in FIG. Further, the optical receiver is designed to change not only the multiplication factor of the APD but also the gain of the equalizing amplifier 2 in order to increase the dynamic range. In other words, in order to operate normally even when the optical input power is large, the APD
The bias voltage 12 and the gain of the equalizing amplifier 2 are reduced. At this time, the gain control input point b of the APD becomes too low, the bias voltage for obtaining the response speed required by the APD cannot be obtained from the DC / DC conversion circuit 3, and the maximum reception sensitivity is shown in FIG. It will be 6 position. Further, the APD bias voltage at the position 9 in FIG. 3 is set to the minimum bias voltage capable of maintaining the response speed required by the APD. Therefore, in the present invention, in order to improve the maximum light receiving sensitivity, a clamp circuit 13 composed of a diode 9, a variable resistor 8, a resistor 7, and a transistor 11 is used to connect the emitter of the transistor 11 and the emitter of the transistor 5 to Wired. -OR connection, DC /
Output to the DC conversion circuit 3. That is, the APD bias voltage 12
Is going to drop from a constant voltage (position of line 2 in FIG. 3) due to increase of APD current I ₁ and decrease of output impedance of the DC / DC conversion circuit 3, the variable resistor 8 causes the base voltage of the transistor 11 to rise. Set to raise. in short,
When the optical input power becomes large, the output impedance of the DC / DC conversion circuit 3 is not sufficiently low when the APD current I ₁ increases, so the APD bias voltage 12 tries to decrease, but the DC / DC conversion circuit 3 The APD bias voltage is increased by the clamp circuit 13 that raises the input point c
Since the voltage is set so that it is not affected by the output impedance of the C / DC conversion circuit 3, DC / DC can be used up to the position of line 4 in Fig. 3.
The influence of the output impedance of the conversion circuit 3 can be reduced, and the maximum light receiving sensitivity is at the position of 8 and is greatly improved.

[Effect of device]

As described above, the present invention provides a transistor emitter whose base input is an output signal detection circuit output of an equalization amplifier connected with an APD electric signal as an input, a resistor,
It has a variable resistor, a diode, and a clamp circuit composed of a transistor, and since it is connected to the input of the DC / DC conversion circuit by Wired-OR connection, the influence of the output impedance of the DC / DC conversion circuit is reduced, The dynamic range of the optical receiver is increased, and the maximum light receiving sensitivity is significantly improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a bias control circuit according to the prior art, and FIG. 3 is a diagram showing a relationship between an APD bias voltage and an optical input power. 1 ... Avalanche photodiode (APD), 2 ...
Equalizing amplifier, 3 ... DC / DC conversion circuit, 4 ... resistor, 5
... transistor, 6 ... diode, 7 ... resistor,
8 ... Variable resistor, 9 ... Diode, 10 ... Capacitor, 11 ... Transistor, 12 ... APD bias voltage, 13
...... Clamp circuit, 14 …… Output signal amplitude detection circuit, I ₁ …
... APD current, a ... power supply voltage terminal, b ... gain control voltage input point, c ... DC / DC conversion circuit input point, d ... DC / DC conversion circuit output point, in Fig. 3, line 1: The relationship between the optical input power and the APD bias voltage when the APD obtains the optimum current multiplication factor with the minimum photosensitivity, line 2: the level at which the APD bias voltage is kept constant in the circuit diagrams of the conventional and the present invention, Line 3: APD bias voltage drop level in the conventional circuit diagram, Line 4: APD bias voltage drop level in the circuit diagram of the present invention, Line 5: Attempts to keep the APD bias voltage constant in the conventional and inventive circuit diagrams. , And the level when the output impedance of the DC / DC conversion circuit is zero, 6 ... the maximum photosensitivity when only the gain control circuit is used, 7 ...
Maximum light receiving sensitivity in the conventional circuit, 8 ... Maximum light receiving sensitivity in the circuit of the present invention, 9 ... APD is the lowest level of the APD bias voltage to obtain the required response speed.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04B 10/26 10/28

Claims (1)

[Scope of utility model registration request] 1. An optical signal receiving circuit using an avalanche photodiode as an optical-electrical conversion element for converting an optical signal into an electric signal, wherein the electric output signal of the avalanche photodiode is detected to detect an output signal amplitude of an equalizing amplifier. A circuit, a DC / DC conversion circuit for supplying a bias voltage to the avalanche photodiode, a first transistor having the detection circuit output as a base input, and a sliding terminal of a variable resistor connected to a second base A clamp circuit composed of a transistor, the emitters of the first transistor and the second transistor are connected to each other, and are connected to the input of the DC / DC conversion circuit, the optical input power of the optical signal The bias voltage is decreased and the gain of the equalizing amplifier is changed according to the increase of Balun Chez photodiode bias voltage control circuit.