JPH0870265A - Synchronization tracking device - Google Patents

Abstract

PURPOSE: To miniaturize a synchronization tracking device by digitizing circuits for the device. CONSTITUTION: A received wave IN is separated into an I component and a Q component by an IQ separate section 11, a PN multiplier section 12 multiplies digitally PN codes EPNI, EPNQ with the I and Q components of received data and a PN multiplier section 16 multiplies digitally PN codes LPNI, LPNQ with the I and Q components of the received data. Average sections 13, 14, 17, 18 average each output signal of the PN multiplier sections 12, 16 respectively to provide it to absolute value generating sections 15, 19. The absolute value generating sections 15, 19 take absolute values xE, xL. A difference generating section 20 takes a difference (y) of the absolute values xE, xL and provides an output of it to a phase deviation control section 21. The phase deviation control section 21 outputs an output signal S21 based on the difference (y) and a PN code generator 22 generates a PN code depending on the output signal S21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code division multiple connection for performing communication by multiplexing signals modulated by spread spectrum in the same frequency band.
The present invention relates to a synchronization tracking device at a receiving station in a mobile communication system based on ccess (hereinafter referred to as CDMA) communication.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference: Spread spectrum communication system application technology, 1992, Takaaki Hasegawa, "Synchronization and retention" P.59-67 FIG. 2 is a schematic block diagram of a conventional synchronization tracking device. This synchronization tracking device has an in-phase component (hereinafter referred to as an I component) of a received wave having a complex envelope that has passed through a spatial propagation path.
And pseudo random signal (Pseudo Noise code, hereafter, PN)
It is provided with a multiplier 1 that performs multiplication with a code. The output side of the multiplier 1 is a low pass filter (Low Pass Filter).
, Hereinafter referred to as LPF) 2 and is connected to the input side of the absolute value circuit 3.

Further, this synchronization tracking device is provided with a multiplier 4 which multiplies a PN code by a quadrature component (hereinafter referred to as a Q component) of a received wave. The output side of the multiplier 4 is the LPF 5
Is connected to the input side of the absolute value circuit 6 via. The output side of the absolute value circuit 3 is connected to the addition input side of the difference circuit 7, and the output side of the absolute value circuit 6 is connected to the subtraction input side of the difference circuit 7. The output side of the difference circuit 7 is connected to the input side of the loop filter 8. The loop filter 8 is for z-converting the input signal. The output side of the loop filter 8 is connected to the input side of a voltage controlled oscillator (hereinafter referred to as VCO) 9. The VCO 9 is the loop filter 8
The frequency of the output signal changes according to the output voltage of the. The output side of the VCO 9 is connected to the input side of a shift register 10 that generates a PN code. The early output of the PN code output from the shift register 10 is
It is adapted to be input to the multiplier 1. A late output whose phase is delayed from the early output is input to the multiplier 2.

Next, the operation of FIG. 2 will be described. When the complex envelope received wave IN that has passed through the space propagation path enters the synchronous tracking device, it is first separated into an I component and a Q component, and the multiplier 1,
At 4, the PN code is multiplied by the early output and the late output having a phase different from that of the early output. Since each high-frequency component is removed from each multiplied signal, the LPF
Smoothed at 2 and 4, respectively. Each smoothed signal is integrated for one cycle of the clock input to the shift register 10, and the absolute value circuits 3 and 6 take absolute values to convert each integration result from a complex envelope to a real number. The difference circuit 7 takes the difference value of the two absolute value signals, and then inputs this to the loop filter 8. The loop filter 8 converts into a voltage corresponding to this difference value. Loop filter 8
The VCO 9 is driven by the output voltage from the VCO 9. VCO
The clock from 9 is input to the shift register 10.
The shift register 10 generates an early output and a late output based on the clock from the VCO 9.

[0005]

However, the conventional synchronization tracking device has the following problems. In general,
A plurality of synchronization tracking devices are housed in a portable device for mobile communication, but in the synchronization tracking device having the above-mentioned configuration, the device is configured by an analog circuit, the device scale is large, and the configuration is complicated,
Since the portable device itself becomes large, it is inconvenient to carry. In order to eliminate the above-mentioned problems of complexity of the configuration and enlargement of the device scale, the present invention first digitizes the entire circuit to reduce the amount of processing, and further reduces the number of parts to simplify the configuration. It is an object of the present invention to provide a device that realizes miniaturization of the device scale.

[0006]

In order to solve the above problems, the present invention provides a receiving station of a mobile communication system based on a CDMA system, in which signals modulated by spread spectrum are multiplexed in the same frequency band for communication. The following means are provided in the synchronization follow-up device described in 1. That is, a separation unit that separates a received signal represented by a complex number transmitted through the spatial propagation path into an in-phase component and a quadrature component, a multiplication result of the in-phase component and the first pseudo-random signal, an quadrature component, and a second component. And the result of multiplication with the pseudo random signal are added to output the real part of the complex number, and the result of multiplication of the in-phase component and the second pseudo random signal is calculated from the result of multiplication of the quadrature component and the first pseudo random signal. The first digital operation unit that subtracts and outputs the imaginary part of the complex number, the multiplication result of the in-phase component and the third pseudo random signal, and the multiplication result of the quadrature component and the fourth pseudo random signal are added. Outputs the real part of a complex number, and the orthogonal component and the third
And a second digital operation unit for outputting the imaginary part of the complex number by subtracting the multiplication result of the in-phase component and the fourth pseudo random signal from the multiplication result of the pseudo random signal of.

A first averaging circuit for sequentially integrating one symbol for the real part output from the first digital multiplication unit and averaging the integration results using a transversal filter, From the second digital multiplication unit, a second averaging circuit that sequentially performs integration of one symbol on the imaginary part output from the first digital multiplication unit and averages the integration result using a transversal filter. A third averaging circuit that sequentially performs integration for one symbol on the output real part and averages the integration result using a transversal filter, and an imaginary part output from the second digital multiplication part. A fourth averaging circuit that sequentially performs integration for one symbol and averages the integration results using a transversal filter is provided.

Further, a first absolute value generation section for generating absolute values of a first complex number having an output signal of the first averaging circuit and an output signal of the second averaging circuit as a real part and an imaginary part, respectively. And a second absolute value generator that generates the absolute value of the second complex number having the output signal of the third averaging circuit and the output signal of the fourth averaging circuit as the real part and the imaginary part, respectively. It is provided. Also, a difference generation unit that generates a difference value between the absolute value of the first complex number and the absolute value of the second complex number, a phase shift control unit that digitally changes the clock timing based on the difference value, The first pseudo-random signal and the second pseudo-random signal having a phase different from the phase of the first pseudo-random signal are input to the first digital multiplication unit based on the clock output from the shift control unit, and the second pseudo-random signal is input to the first digital multiplication unit. A fourth pseudo-random signal having a phase different from that of the pseudo-random signal and the third pseudo-random signal is input to the second digital multiplication unit, and a fifth pseudo-random signal having the same phase as the clock is further input to the mobile communication system. And a pseudo-random signal generator that outputs the signal to the inside.

[0009]

According to the present invention, since the synchronization follow-up device is configured as described above, the separation unit separates the received signal represented by the complex number transmitted through the spatial propagation path into the in-phase component and the quadrature component. . The first digital operation unit adds the multiplication result of the in-phase component and the first pseudo random signal and the multiplication result of the quadrature component and the second pseudo random signal to output the real part of the complex number, and the quadrature. The multiplication result of the in-phase component and the second pseudo random signal is subtracted from the multiplication result of the component and the first pseudo random signal to output the imaginary part of the complex number. On the other hand, the second digital operation unit adds the multiplication result of the in-phase component and the third pseudo random signal and the multiplication result of the quadrature component and the fourth pseudo random signal, and outputs the real part of the complex number, Further, the multiplication result of the in-phase component and the fourth pseudo random signal is subtracted from the multiplication result of the orthogonal component and the third pseudo random signal, and the imaginary part of the complex number is output. Further, the first averaging circuit sequentially performs integration for one symbol on the real part output from the first digital operation unit, and averages the integration result using a transversal filter. Similarly, the second averaging circuit sequentially performs integration for one symbol on the imaginary part output from the first digital operation unit, and averages the integration result using a transversal filter. The third averaging circuit sequentially performs integration for one symbol on the real part output from the second digital operation unit, and averages the integration result using a transversal filter. The fourth averaging circuit sequentially performs integration for one symbol on the imaginary part output from the second digital operation unit, and averages the integration result using a transversal filter.

Further, the first absolute value generation unit calculates the absolute value of the first complex number having the output signal of the first averaging circuit and the output signal of the second averaging circuit as the real part and the imaginary part, respectively. To generate. Similarly, the second absolute value generation unit generates the absolute value of the second complex number having the output signal of the third averaging circuit and the output signal of the fourth averaging circuit as the real part and the imaginary part, respectively. . The difference generation unit generates a difference value between the absolute value of the first complex number and the absolute value of the second complex number. The phase shift control unit
The clock timing is digitally changed based on this difference value. The pseudo-random signal generator includes a first pseudo-random signal and a second pseudo-random signal having a phase different from that of the first pseudo-random signal based on the clock output from the phase shift controller.
Each of the pseudo random signals of No. 1 to the first digital operation unit, and to the second digital operation unit of each of the fourth pseudo random signals having different phases from the second pseudo random signal and the third pseudo random signal. The fifth pseudo random signal having the same phase as the clock is input to the mobile communication system. As described above, the synchronization tracking device is realized by the digital circuit. Therefore, the above problem can be solved.

[0011]

1 is a schematic block diagram of a synchronization tracking device showing an embodiment of the present invention. This synchronization tracking device
The IQ separation unit 11 is provided for separating the reception wave IN having the complex envelope that has passed through the space propagation path into I and Q components. I
The I component output terminal of the Q separation unit 11 is connected to the I component input terminal of the PN multiplication unit 12, which is the first digital operation unit. The Q component output terminal of the IQ separation unit 11 is the PN multiplication unit 12
It is connected to the Q component input terminal of. The real part output terminal of the PN multiplication unit 12 is connected to the input side of the averaging unit 13. The imaginary part output terminal of the PN multiplication unit 12 is connected to the input side of the averaging unit 14. The output side of the averaging unit 13 is connected to one input terminal of the absolute value generating unit 15, and the averaging unit 14
The output side of is connected to the other input terminal of the absolute value generator 15.

On the other hand, the I component output terminal of the IQ separation unit 11 is connected to the I component input terminal of the PN multiplication unit 16 which is the second digital operation unit. The Q component output terminal of the IQ separation unit 11 is connected to the Q component input terminal of the PN multiplication unit 16. The real part output terminal of the PN multiplication unit 16 is connected to the input side of the averaging unit 17. The imaginary part output terminal of the PN multiplication unit 16 is connected to the input side of the averaging unit 18. Averaging unit 1
The output side of 7 is connected to one input terminal of the absolute value generating section 19, and the output side of the averaging section 18 is connected to the other input terminal of the absolute value generating section 19. The output side of the absolute value generation unit 15 is connected to the subtraction input side of the difference generation unit 20, and the output side of the absolute value generation unit 19 is connected to the addition input side of the difference generation unit 20. The output side of the difference generation unit 20 is connected to the input side of the phase shift control unit 21. The output side of the phase shift control section 21 is connected to the input side of the PN code generator 22. An early I component output terminal of the PN code generator 22 is connected to an early I component input terminal of the PN multiplier 12, and an early Q component output terminal of the PN code generator 22 is an early Q component input terminal of the PN multiplier 12. It is connected to the. The late I component output terminal of the PN code generator 22 is connected to the late I component input terminal of the PN multiplication unit 16, and the late Q component output terminal of the PN code generator 22 is P
It is connected to the late Q component input terminal of the N multiplier 16. The PN code output terminal of the PN code generator 22 is connected to the output terminal 23.

FIG. 3 is a block diagram of the PN multiplication unit in FIG. The I component rI of the received wave IN is input to the I component input terminal of the PN multiplication unit, and the Q component rQ of the received wave IN is input to the Q component input terminal. Next, the multiplication result of the I component rI and the I component PNI of the PN code and the multiplication result of the Q component rQ and the Q component PNQ of the PN code are added, and expressed by the following equation (1) from the real part output terminal. The real part PI is output. PI = rI.PNI + rQ.PNQ (1) On the other hand, the multiplication result of the I component rI and the Q component PNQ of the PN code is subtracted from the multiplication result of the Q component rQ and the I component PNI of the PN code to obtain the imaginary part. An imaginary part PQ represented by the following equation (2) is output from the output terminal. PQ = rQ · PNI−rI · PNQ (2) FIG. 4 is a schematic configuration block diagram of the averaging unit in FIG. 1. This averaging unit integrates the input signal P and outputs the output signal x
An integrating circuit 31 that outputs (t) is provided. On the output side of the integrating circuit 31, N delay elements 33-1 to 33-N (N; natural number of 1 or more) are serially connected. Each of the output sides of the delay elements 32-1 to 32-N has a weighting factor K _{1 to} K.
_The coefficient elements 33-1 to 33-N each having _N are connected to the adder 34, and the output side of the integrating circuit 31 is also connected to the adder 34. The output signal y (t) of the averaging unit is represented by the following equation (3): y (t) = x (t) + K ₁ y (t−T) + K ₂ y (t−2T) + ... + K _N y (t-NT) (3) However, T: sample time width Next, the operation of FIG. 1 will be described.

A reception wave IN represented by a complex number that has propagated through the space propagation path is separated into an I component and a Q component by an IQ separation unit 11 and input to PN multiplication units 12 and 16, respectively. PN
In the multiplying unit 12, two PN codes EPNI and EPNQ, which are the PN codes on the Early side and which are different in phase, input from the PN code generator 22 and the I component and Q component of the received data are digitalized as shown in FIG. The real part EP
The I and the imaginary part EPQ are output to the averaging units 13 and 14, respectively. Similarly, in the PN multiplication unit 16, the PN code generator 2
Two PN codes LPNI and LPNQ having different phases, which are local reference signals on the rate side input from 2, and the I component and the Q component of the received data are digitally multiplied to obtain a real part LPI and an imaginary part LPQ. Output to the averaging units 17 and 18, respectively. The averaging unit 13 performs integration for one sample on the real part EPI, filters this by the N-stage transversal filter, and inputs the average value y ₁₃ to the absolute value generating unit 15. The averaging unit 14 performs integration for one sample on the imaginary part EPQ, filters this by an N-stage transversal filter, and inputs the average value y ₁₄ to the absolute value generating unit 15. The averaging unit 17 is the real part LP
One sample is integrated with respect to I, filtered by an N-stage transversal filter, and the average value y
₁₇ is input to the absolute value generator 19. The averaging unit 18
One sample is integrated with respect to the imaginary part LPQ, and this is N
Filter with the transversal filter of the stage,
The average value y ₁₈ is input to the absolute value generator 19.

The absolute value generator 15 converts the filtered complex number (y ₁₃ + y ₁₄ i) (i; imaginary unit) into an absolute value xE represented by the following equation (4) to obtain a real number. xE = (y ₁₃ ² + y ₁₄ ² ) ^1/2 (4) In the absolute value generator 19, the absolute value xL of the filtered complex number (y ₁₇ + y ₁₈ i) shown by the following equation (5) is expressed. Convert to a real number by taking. xL = (y ₁₇ ² + y ₁₈ i ² ) ^1/2 (5) The absolute values xE and xL are input to the difference generation unit 20, and the two absolute values xE and xL shown in the following equation (6). The difference y is calculated and output to the phase shift controller 21. y = xL−xE (6) The phase shift control unit 21 determines that the signal strength on the late side is strong when the difference y is larger than 0, that is, the synchronization time is shifted to the late side, and the difference y is When it becomes equal to or higher than the predetermined threshold value, the output signal S21 is set to +1.

On the other hand, the phase shift controller 21 determines that the difference y is 0.
When it is smaller, it is determined that the signal strength on the early side is strong, that is, the synchronization time is deviated to the early side. When the difference y does not exceed the predetermined threshold value, the output signal S21 is set to 0. That is, the output signal of the difference generation unit 20 can tell from the difference between the signal strength on the early side and the signal strength on the late side whether the synchronization is deviated, that is, the synchronization is advanced or delayed. Generator 22
An output signal S21, which is the clock timing for outputting the PN code, is output. When the output signal S21 of the phase shift control unit 21 is +1, the PN code generator 22 has a PN code EP that is 1/2 chip phase ahead of the reference clock.
NI and EPNQ are output to the PN multiplication unit 12, and the output signal S
When 21 is -1, the PN code LPNI and LPNQ delayed by 1/2 chip phase from the reference clock are used as the PN multiplication unit 1
Output to 6. Further, when the output signal S21 is 0, PN
The code generator 22 has a PN whose phase matches the reference clock.
The code S22 is output to the output terminal 23. As mentioned above,
According to the present embodiment, the analog circuit VCO and the loop filter in the prior art are removed, and the phase shift control unit 21 which is a digital circuit is added in its place. Therefore, the multiplication speed is increased and the circuit configuration is improved. Realization of simplification and downsizing of the device scale.

[0017]

As described in detail above, according to the present invention, the VCO and the loop filter, which are analog circuits in the conventional synchronous tracking device, are removed, and instead, a phase shift control section constituted by a digital circuit is provided. Since I added
The multiplication speed of the multiplier can be increased, and the circuit configuration can be simplified and the device scale can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a synchronization tracking device showing an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a conventional synchronization tracking device.

FIG. 3 is a configuration diagram of a PN multiplication unit in FIG.

4 is a schematic configuration block diagram of an averaging unit in FIG. 1. FIG.

[Explanation of symbols]

11 IQ Separating Section (Separating Section) 12, 16 PN Multiplying Section (Digital Operation Section) 13, 14, 17, 18 Averaging Section 15, 19 Absolute Value Generating Section 20 Difference Generating Section 21 Phase Shift Control Section 22 PN Code Generator (Pseudo random signal generator)

Claims (1)

[Claims] 1. A synchronous tracking device in a receiving station of a mobile communication system based on a code division multiple access system, in which signals modulated by spread spectrum are multiplexed in the same frequency band for communication, and transmitted through a spatial propagation path. A separation unit that separates the received signal represented by the received complex number into an in-phase component and a quadrature component; a multiplication result of the in-phase component and a first pseudo-random signal; the quadrature component and a second pseudo-random signal; Output the real part of the complex number, and subtract the multiplication result of the in-phase component and the second pseudo random signal from the multiplication result of the quadrature component and the first pseudo random signal. And outputs the multiplication result of the in-phase component and the third pseudo-random signal and the multiplication result of the quadrature component and the fourth pseudo-random signal. Then a complex number And outputs the real part of the complex number and subtracts the multiplication result of the in-phase component and the fourth pseudo random signal from the multiplication result of the orthogonal component and the third pseudo random signal, and outputs the imaginary part of the complex number. The second digital operation unit for performing the above operation and the real part output from the first digital multiplying unit are sequentially integrated for one symbol, and the integration result is averaged using a transversal filter. An averaging circuit, and a second averaging circuit that sequentially performs integration for one symbol on the imaginary part output from the first digital multiplication unit and averages the integration result using a transversal filter. A third averaging circuit that sequentially integrates one symbol for the real part output from the second digital multiplication unit and averages the integration result using a transversal filter; Digital multiplier of A fourth averaging circuit that sequentially performs integration of one symbol on the imaginary part output from the above, and averages the integration result using a transversal filter; and an output signal of the first averaging circuit and A first absolute value generation unit that generates an absolute value of a first complex number having an output signal of the second averaging circuit as a real part and an imaginary part, respectively, and an output signal of the third averaging circuit and a fourth A second absolute value generator that generates an absolute value of a second complex number whose output signal of the averaging circuit is a real part and an imaginary part, respectively, and an absolute value of the first complex number and an absolute value of the second complex number. A difference generation unit that generates a difference value with the value, a phase shift control unit that digitally changes the timing of the clock based on the difference value, and the first pseudo based on the clock output from the phase shift control unit. Random signal and the first pseudo run The arm signal to enter a different second pseudo random signal in phase to each of the first digital multiplier section, and the third
Of the pseudo random signal and the fourth pseudo random signal having different phases from the third pseudo random signal are input to the second digital multiplying unit, respectively, and a fifth pseudo random signal having the same phase as the clock. And a pseudo-random signal generator that outputs the signal to the mobile communication system.