JPH0869416A - Virtual machine system - Google Patents

Abstract

PURPOSE: To decrease the generation of host DAT to a single time when the entry identifier(EID) of a TLB entry indicates that a guest actual address is valid and a host actual address is invalid. CONSTITUTION: On condition that a TLB entry selected by a TLB entry decision part 2 matches the VMID of an in-execution virtual computer and the EID indicates that the guest and host actual addresses are invalid when a guest virtual address is supplies to a guest DAT mechanism and selection part 7, the decision part 2 starts guest and host DAT and selects and outputs the host actual address from the host DAT to a selection part 8; when the EID indicates that the host actual address is invalid, the decision part 2 starts the host DAT to select and output the host actual address from the host DAT to the selection part and the host DAT receives the guest actual address in the entry and outputs the host actual address, but when the EID shows that the host actual address is valid, the decision part 2 selects and outputs the host actual address in the entry to the selection part 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual computer system having an address translation buffer (TLB), and more particularly to a virtual computer system capable of speeding up address translation.

[0002]

2. Description of the Related Art A virtual computer system uses a real computer for time division, and sets virtual hardware information in each time slot so that one real computer
It is a system that realizes the operation of one or more virtual machines. A program that manages a real computer and realizes a virtual computer system in this way is called a host.
A program running on the virtual computer is called a guest. The main memory used by the guest exists on the virtual memory created by the host. Therefore, the main memory of the guest exists as the host data in the main memory of the real computer or the auxiliary memory. Therefore, the access to the main memory by the guest, whether it is by the virtual address or the real address, requires the dynamic address translation (host DAT) by the host.

In particular, the main memory access by the guest virtual address is performed by the guest in dynamic address translation (guest DA
T) is required. Since the guest segment table exists in the host virtual space, it is necessary to perform the host DAT to obtain the real address of the real computer (host real address) in order to obtain the segment table entry. Similarly, to get the page table entry, the host DA
T is needed. In this way, the real address (guest real address) of the guest virtual address obtained by the guest DAT is further converted into the host real address by performing the host DAT.

FIG. 2 is a diagram summarizing a process of converting a guest virtual address into a host real address. Two
Is a guest segment table entry (guest STE)
3 is the page table entry (guest PTE),
Reference numeral 5 is a host DAT for converting a guest real address of data into a host real address. The conversion of the guest virtual address requesting the main memory access into the host real address in this way is called 2-level address conversion (2-level DAT). In the 2-level DAT, the host DAT is performed three times as shown by 2, 3, and 5 in FIG. 2, so that the occurrence frequency thereof greatly affects the system performance.

As a technique for speeding up such address translation, there is a technique relating to an address translation buffer (TLB). In Japanese Examined Patent Publication No. 61-22825, T
It is possible to simultaneously hold two types of entries on the LB, a host entry and a guest entry of a virtual machine currently implemented on a real computer. In addition, Japanese Examined Japanese Patent Sho 58-8073
In the gazette, a TLB field is expanded to identify a virtual machine identifier (VM) for identifying a host and a plurality of guests.
The method of providing the identifier) is shown. According to this method, it becomes possible to simultaneously hold the host entry and the plurality of guest entries on the TLB. Therefore, T
The rate of conversion using LB is increased and the performance is improved.

[0006]

When the host real page corresponding to the guest virtual address is paged out to the auxiliary storage device for the convenience of the main memory management of the host, in these conventional techniques, the paged out host real page is used. The invalid bit of the host page table entry having the page address is set to 1 to invalidate the TLB entry in which the paged-out host real page address is registered. Here, the problem is that the translation table of the guest DAT that translates the guest virtual address into the guest real address is valid without any change, but when there is a main memory access request at the guest virtual address, the TLB entry becomes invalid. As a result, two-level DAT is generated, and (1) guest DAT is performed, so that two host DATs (2 and 3 in FIG. 2) are generated. In this way, when the guest real address obtained by the guest DAT is host DAT (5 in FIG. 2), a host interrupt occurs due to invalidation of the page table entry, and after the target host real page is paged in, (2) The two-level DAT is repeated from the beginning again, so that the host DAT (2, 3, 5 in FIG. 2) occurs three times.

It is an object of the present invention to provide a guest real address corresponding to a guest virtual address by the TLB even if the host real page corresponding to the guest virtual address is paged out for the convenience of the host. 2-level DA that is repeated by suppressing the occurrence of guest DAT that accompanies DAT
It is intended to improve the performance of the virtual computer system by reducing the occurrence of the host DAT of T to once.

[0008]

To achieve the above object, the present invention has a virtual machine having a mechanism for converting a virtual address created by one or more virtual machines on one real machine into a real address of the real machine. Guest D in the computer system
It has an AT mechanism, a host DAT mechanism, and a plurality of entries, and each entry is valid / invalid of the judgment information field, guest real address field, host real address field, and guest real address field, and valid of the host real address field. An address translation buffer (TLB) consisting of an entry identifier field indicating invalidity,
A TLB entry selection unit that selects an entry of the TLB based on a given guest virtual address, determination information and an entry identifier in the TLB entry selected and read by the TLB entry selection unit, and a determination regarding the virtual computer in execution A TLB entry determination unit that receives information and makes a determination and outputs a determination output, and a host real address read from the TLB or a host real address output from the host DAT mechanism according to the determination output of the TLB entry determination unit. A host real address selection unit for selectively outputting any of the above, the guest virtual address is given to the guest DAT mechanism and the TLB entry selection unit, and the judgment information in the selected TLB entry and the judgment information about the virtual machine in execution. Match the entry identifier is guest And indicating that the host real address is invalid, the TLB entry determination unit activates the guest and host DAT mechanism and outputs a determination output for causing the host real address selection unit to selectively output the host real address output by the host DAT mechanism, The activated host DAT mechanism outputs the host real address in response to the output of the activated guest DAT mechanism, and when the entry identifier indicates that the host real address is invalid, the TLB entry determination unit activates the host DAT mechanism and The host real address selection unit outputs a judgment output for selecting and outputting the host real address output by the host DAT mechanism, and the activated host DAT
The mechanism receives the guest real address in the selected TLB entry and outputs the host real address. When the entry identifier indicates that the host real address is valid, the TLB entry determination unit determines the TLB entry selected by the host real address selection unit. The judgment output for selectively outputting the host real address in is output.

[0009]

When the guest virtual address is given to the guest DAT mechanism and the TLB entry selector, and when the entry identifier indicates that the guest and host real addresses are invalid, the guest and host DAT mechanism is activated, and the activated host DAT. The mechanism receives the output of the activated guest DAT mechanism and outputs the host real address, and this host real address is selected and outputted. When the entry identifier indicates that the host real address is invalid, the host DAT mechanism is activated, and the activated host DAT mechanism is selected by the selected TLB.
Upon receiving the guest real address in the entry, the host real address is output, and this host real address is selected and output. When the entry identifier indicates that the host real address is valid, the host real address in the TLB entry is selected and output. As described above, according to the present invention, the host real address can be obtained by effectively utilizing the TLB entry having the page address invalidated by the host, and the 2-level DAT can be speeded up.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows one embodiment using the TLB of the present invention. It comprises a TLB unit 1, a TLB entry determination unit 2, a host DAT mechanism 4, a guest DAT mechanism 5, an entry identifier control unit 6, a TLB entry selection unit 7, and a host real address selection unit 8. The TLB entry of the TLB part 1 is
The entry information field (EID) and the VM identifier field (VMID) are included in the judgment information field, the guest real address field (GR), and the host real address field (HR). G-R, H-
The top address of the page is stored in R.

The EID consists of 2 bits and has the following meanings depending on the contents. 00: TLB entry invalid 01: GR valid 10: HR valid 11: Both GR and HR valid The fields of these TLB entries are registered at the time of address translation.

Address translation is performed by the guest DAT mechanism 5 and the host DAT mechanism 4. Guest DAT mechanism 5
This is a mechanism for performing a guest DAT (steps 1 to 4 in FIG. 2) for converting a guest virtual address given by the line 106 into a guest real address by using the guest DAT table executed by the real computer. In addition, the host DAT mechanism 4
Uses the DAT table managed by the host to convert the guest real address to the host real address.
This is a mechanism for performing AT (5 in FIG. 2).

Host DAT mechanism 4 and guest DAT mechanism 5
Is activated by the TLB entry determination unit 2.
The TLB entry determination unit 2 determines the validity / invalidity of the TLB entry selected by the TLB entry selection unit 7 based on a part of the address on the line 106 (the TLB is configured so that the TLB entry to be selected always exists). The host DAT mechanism 4 and the guest DAT mechanism 5 are activated based on this determination result. When the TLB entry determination result indicates that the TLB entry is invalid, both the guest DAT mechanism 5 and the host DAT mechanism 4 are activated, and when the TLB entry is valid and only GR is valid, the host DAT Only mechanism 4 is activated.

Then, when the guest DAT mechanism 5 is activated, the guest DAT mechanism 5 obtains a valid guest real address, and the TLB selected by the TLB entry selector 7 is selected.
In the entry, the guest real address whose EID is '01' is registered on the line 108. Similarly, when the host DAT mechanism 4 is activated, when the host DAT mechanism 4 obtains a valid host real address, the TLB entry selected by the TLB entry selector 7 is line 104 and the EID is "1".
Register the host real address obtained as 1 '.

The entry identifier control unit 6 is a control unit that changes the contents of the EID of the TLB entry having the host real address that is invalidated by the page invalidation instruction to "HR invalid". When the host executes an invalid page instruction (IPTE instruction) to invalidate the host real page, the entry identifier control unit 6 receives the activation signal and the invalid host real page address from the line 107, and sequentially selects the TLB entries. The TLB entry selection unit 7 is controlled so as to do so. At this time, the contents of the selected TLB entry are read out by the sequential selection by the TLB entry selection unit 7, and the contents of HR and the contents of EID are shown in the lines 105 and 10.
It is sent to the entry identifier control unit 6 via 9. The entry identifier control unit 6 controls the contents of H-R on line 105 and line 10
The host real page address received in 7 is compared, and the comparison result is obtained. Then, the TLB entry (HR equivalent to the host real page address on the line 107) for which this comparison result is coincident
If the EID content (content of the line 109) of the TLB entry having "1" is "11", the EID content of the TLB entry is set to "01". Similarly, the TL for which this comparison result matches
Contents of EID of B entry (TLB entry having HR equal to host real page address of line 107) (line 1
If the content of 09) is '10', the EID of the same TLB entry
Set the contents of to '00'.

Now, when the guest virtual address is given to the line 106 for the guest to access the main memory, T
The LB entry selector 7 determines the TL corresponding to the address.
Select B entry. The selected TLB entry is
The TLB entry determination unit 2 determines whether it is valid or invalid. A line 110 provides the TLB entry determination unit 2 with TLB entry determination information such as the VMID of the virtual computer currently implemented on the real computer. The result of the TLB entry validity / invalidity determination by the TLB entry determination unit 2 is line 110.
Entry judgment information of the selected TLB entry judgment information field and the EID of the same TLB entry
It depends on the content of. Entry determination information and TLB on line 110
The comparison of the entry determination information fields may be, for example, the comparison of the VM identifiers described in Japanese Patent Publication No. 58-8073, or the determination information other than the VM identifier may be combined. If the comparison results do not match, TLB
If the entry is invalid, the EID is other than "00", and the comparison result is a match, the TLB entry is valid. If the EID is "00", the TLB entry is invalid even if the comparison result is a match.

Here, if the TLB entry selected by the guest virtual address on the line 106 is invalid, the TLB entry judgment unit 2 does not have the host real address corresponding to the guest virtual address on the HR, and therefore the guest DAT on the line 103. The guest DAT is activated in the mechanism 5 and the host DAT is activated in the mechanism 4 by the line 101 (activation of the two-level DAT). At this time, the guest DAT5 mechanism obtains the guest virtual address on line 106 and performs the guest DAT to obtain a valid guest real address. Next, the guest DAT5 mechanism registers a valid guest real address in the GR of the TLB entry selected by the virtual address via the line 108, and the EID of the TLB entry means GR valid '01'. To register. Next, the host DAT mechanism 4 obtains a valid guest real address via the line 108 and performs a host DAT to obtain a valid host real address. The host DAT mechanism 4 registers the valid host real address obtained by the host DAT in the HR through the line 104, and registers "11", which means that both GR and HR are valid, in the EID. The TLB entry selected at this time is equal to the TLB entry in which the guest DAT mechanism 5 has registered the guest real address. Therefore, the content of the EID is changed from "01" to "11".

The host real address thus obtained is sent to the host real address selector 8 through the same line 104. The host real address selection unit 8 is controlled by the TLB entry determination unit 2 and the host DAT mechanism 4 and the guest DAT mechanism 5 are controlled.
Select the host real address on line 104 when is activated. In this way, the main memory obtains the host real address. The relationship between the guest virtual address given to the line 106 and the guest real address registered in the TLB by the guest DAT mechanism 5 is valid until the guest DAT table is changed. Even if the host DAT (processing of the host DAT mechanism 5) is interrupted after registering the EID and GR on the line 108 (for example, when the invalid bit of the host page table entry is 1), G- R is valid. Therefore, the EID remains GR-enabled, '01'.

Now, such a TLB entry is a line 10
When selected with 6 guest virtual addresses, ie TL
If the B entry is valid and the EID is “01” (GR is valid), the TLB entry determination unit 2 has the guest real address corresponding to the guest virtual address in GR,
The host DAT is activated to the host DAT mechanism 4 by the line 101. Then, as in the case where the TLB entry is invalid, the host D
When the AT mechanism 4 obtains the host real address corresponding to the GR guest real address from the host DAT, the AT mechanism 4 TLs the line 104.
'11' meaning that both GR and HR are valid for the EID of the TLB entry selected by the B entry selector 7
And the obtained host real address is registered in HR. The obtained host real address is sent to the host real address selection unit 8 via the line 104, and the host real address selection unit 8 selects the host real address on the line 104 under the control of the TLB entry determination unit 2.

As described above, the TLB entry selected by the guest virtual address is "01" even if the EID is "00".
However, in the end, both the GR and HR become valid (EID is "11") TLB entries. The relationship between the guest real address of the GR in the TLB entry and the guest virtual address is valid unless the guest DAT table is changed, as described above. Also, the EID is '11'
Guest real address and HR of TLB entry of
The host real address relationship of is valid unless the host DAT table is changed. However, when the HR host real address corresponding to the GR guest real address is targeted for page-out to the auxiliary storage due to the host main memory management, the host DAT table is changed. Occurs. Therefore, the guest's TLB entry with the host real address being paged out must invalidate HR. At this time, since the guest DAT table is not changed, the EID is "11" for the TL.
B entry is GR valid / HR invalid (EID is' 0
It should be 1 ').

Such control is performed when a page invalid command (IPTE command) is issued by the host. When this page invalid instruction is issued, the invalid bit of the host page table entry having the invalid page address becomes "1". Then, the entry identifier control unit 6
As described above, the TLB entry having the invalid host real page address is searched, and the EI of the corresponding TLB entry is searched.
Change D. At this time, the EID of the TLB entry is
When the HR is valid, the contents that make the HR invalid are registered. That is, when the content of the EID of the TLB entry is "11", it is changed to "01".

When such a TLB entry is selected by the guest virtual address of the line 106, that is, the selected TLB entry is valid, and the host page invalidation instruction causes the EID to be "01" (G-R is valid). TL changed to
For B entry, TLB entry is valid and EID
Is "01" (GR is valid), there is a valid guest real address in GR.
The AT mechanism 4 performs host DAT. However, since the invalid bit of the host page table entry is set to 0 by the page invalid instruction as described above, a host program interrupt occurs at the time of host DAT and the processing is interrupted. At this time, the EID of the TLB entry remains "01".

Upon the occurrence of the host program interrupt,
After the target page is paged in from the auxiliary storage device (invalid bit 0 of the host page table entry is set), the host performs main memory access again with the same guest virtual address. The TLB entry selected at this time is the same TL as the TLB entry that caused the host program interrupt.
This is the B entry. Therefore, the guest DAT can be omitted since a valid guest real address is obtained from the TLB (since the EID is '01'). Then, the host DAT is performed with the guest real address obtained from the TLB.
At this time, since the invalid bit of the host page table entry is 0, the host interrupt does not occur. Thereafter, as described above, the line 104 registers the obtained real host address in HR and "11" which means that both GR and HR are valid in EID. And the obtained host real address is line 1
At 04, the data is sent to the host real address selection unit 8, and the host real address selection unit 8 selects the host real address on the line 104 under the control of the TLB entry determination unit 2.

In the above case, in the prior art, even if the relationship between the guest virtual address and the guest real address is valid if the host real page becomes invalid, the TLB entry having the invalid host real page address must be invalidated. There wasn't. Therefore, although the two-level DAT occurs and the relationship between the guest virtual address and the guest real address is valid, the guest DAT (processes 1 to 4 in FIG. 2) and the host DAT (5 in FIG. 2) are executed and the host real address is executed. I had to ask for an address. However, in this embodiment, the relationship between the guest virtual address, the guest real address, and the host real address is held in the TLB entry and is identified. When the host real address is invalid for the guest virtual address as the identification result, the guest real address is supplied to speed up the two-level DAT (because the guest DAT can be omitted).
The host real address can be determined. Also, line 10
If the TLB entry selected by the guest virtual address of 6 is valid and the EID is '10' (HR is valid) or '11' (GR / HR is valid), the HR The content is sent by line 105 to the host real address selector 8. Under the control of the TLB entry determination unit 2, the host real address selection unit 8 determines that the TLB entry is valid and the HR
Is valid (EID is '10' or '11'), line 105
Select the host real address of.

As described above, in this embodiment, the guest DAT is
Register the guest real address obtained in step 3 in the TLB entry,
By managing the TLB entry in which the host real address is invalidated by EID, the address conversion of the virtual machine is speeded up, and the system performance is improved. The case where the EID is '10' is registered when the host is operating on the real computer, and is determined as the TLB entry of the host. Therefore, when the HR is invalidated by the page invalidation instruction in the TLB entry having the EID of "10", the EID is set to "00" (TLB entry invalidity).
Further, the TLB of this embodiment can identify a plurality of guests by VMID.

[0026]

According to the present invention, in a virtual computer system, a TL having a page address invalidated by the host is used.
B entry can be effectively used, and TLB
By having the guest real address in, the 2-level DAT can be speeded up, and the performance of the virtual computer system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a process of converting a virtual address of a conventional guest into a host real address in a virtual computer system.

[Explanation of symbols]

 1 TLB unit 2 TLB entry determination unit 4 Host DAT mechanism unit 5 Guest DAT mechanism unit 6 Entry identifier control unit 7 TLB entry selection unit 8 Host real address selection unit

Claims (1)

[Claims] 1. A virtual computer system having a mechanism for converting a virtual address created by one or more virtual computers on a single real computer into a real address of the real computer, including a guest DAT mechanism, a host DAT mechanism, and a plurality of host DAT mechanisms. And each entry has an entry identifier field indicating a judgment information field, a guest real address field, a host real address field, valid / invalid of the guest real address field, and valid / invalid of the host real address field. A translation buffer (TLB), a TLB entry selection unit that selects an entry of the TLB based on a given guest virtual address, and a T that is selected and read by the TLB entry selection unit.
The TLB entry determination unit that makes a determination by receiving the determination information in the entry of the LB, the entry identifier, and the determination information about the virtual machine that is being executed, and the determination output of the TLB entry determination unit,
Host real address read from or the host DAT
A host real address selector for selectively outputting any of the host real addresses output from the mechanism, wherein the guest virtual address is the guest DAT mechanism and the TL.
When the determination information given to the B entry selection unit matches the determination information regarding the selected TLB entry and the determination information regarding the running virtual machine, the TLB entry determination unit determines when the entry identifier indicates that the guest and host real addresses are invalid. The guest and host DAT mechanism is activated, and a determination output is output to the host real address selection unit to selectively output the host real address output by the host DAT mechanism, and the activated host D
The AT mechanism receives the output of the activated guest DAT mechanism and outputs the host real address. When the entry identifier indicates that the host real address is invalid, the TLB entry judgment unit activates the host DAT mechanism and outputs the host real address. The selection unit outputs a judgment output for selectively outputting the host real address output by the host DAT mechanism, and the activated host DAT mechanism selects the selected TL.
The host real address is output in response to the guest real address in the B entry, and when the entry identifier indicates that the host real address is valid, the TLB entry determination unit determines the host real address in the TLB entry selected by the host real address selection unit. A virtual computer system characterized by outputting a judgment output for selective output.