JPH0869409A - Data reading method for semiconductor memory - Google Patents

Abstract

PURPOSE: To transfer data from a memory cell of a dynamic RAM, which is placed in continuous read operation, at a high speed and read data out without the discontinuity of switching timing. CONSTITUTION: A cell array consists of (m) subarrays, (m) sense amplifiers paired with them, and a switching circuit which switches and connects data lines according to a switching circuit selecting one of their output lines independently, blocks 1a and 1b consists of (k) columns of cell arrays CA and CB, and (n) cell array output lines to which the outputs of cell arrays in the same columns are connected in common, and the switching circuit 2 switches one of the 2n cell array output lines with the switching signal SW2; when data of one block are read out through the switching circuit 2, data of the other block are read out to the input terminal of the switching circuit 2, so that the data can be transferred and read out fast without any discontinuous period even when the blocks are switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reading data from a semiconductor memory, and more particularly to a method of reading data from memory cells in two cell blocks arranged in pairs alternately and continuously. The present invention relates to a data reading method.

[0002]

2. Description of the Related Art One example of a conventional semiconductor memory of this type is No. 15 to 15 published in May 1993, Technical Report of the Institute of Electrical Communication.
It is described on page 21. FIG. 6 is a block diagram of a cell array CA in FIG. 6 which is a block diagram of an essential part of a DRAM having a multi-divided array structure described in the magazine. 8 (a) and FIG. 8 (b), in this type of semiconductor memory, the cell array CA has row lines WL1, WL2,
, A predetermined number of column lines BL1, BL2,
..., memory cells M11 and M1 at the intersections of BLm, respectively.
, M2m, ..., M (m is a positive integer) sub-arrays 41, 42, ..., 4m and the column lines BL1, BL2, ..., BLm of these m sub-arrays are connected, respectively. M sense amplifiers SAMP51, SAMP
52, ..., SAMP5m and the output lines DL1, DL2 ,.
And an external address signal (not shown).
In response to the first switching signal SW1 generated from the first switching circuit 6, the cell array CA that selectively outputs the output of the sense amplifier as the signal YL is k (k is a positive integer) rows,
2n (n is a positive integer and is arranged in k <m <n) columns, and is composed of a cell block having 2n data lines in which k output lines of these cell arrays CA are commonly connected to each column,
2n data lines YL1 to YL2n of this cell block
A second switching circuit 2 and a data amplifier 3 for selectively outputting the output group of the cell array supplied via the second switching signal SW2 generated from the external address signal.

In the method of reading data from the semiconductor memory having the above-mentioned structure, referring to FIG. 9 showing a flow chart of the read operation, first, the row lines WL1 and WL are connected.
One of 2, ..., For example, WL1 is selected and becomes active (process 901). By being activated, the sub-arrays 41, ... Connected to this row line WL1.
, 4m of memory cells M11, M12, ..., M1m, ... Are selected and column lines BL1 connected to these memory cells are selected.
Data is read into BL2, ..., BLm, respectively (process 902). These data are supplied to the sense amplifiers 51, 52, ..., 5m to which the respective column lines are connected, and when the sense amplifier activation signal becomes active, they are amplified and switched by the output lines DL1 ,. The data is transferred to the input terminal of the circuit 6 (process 903).

Here, the output line D of these sense amplifiers
One of L1, ..., DLm, for example, the sense amplifier output line DL1 from which the data of the memory cell M11 of the sub-array 41 of each cell array is being read is switched to the switching signal SW1.
Is active (process 904), the switching circuit 6 to which the respective cell arrays are connected is selectively connected and output to the output line YL1. Then, the same processing is performed in each cell array, and the data is simultaneously read out to the input terminals of the switching circuit 2 via the output lines YL1 to YL2n (processing 905).

When the switching signal SW2 becomes active (process 906), one of the cell array output lines YL1 to YL2n, here YL1 in the switching circuit 2 is sequentially connected according to the switching signal SW2 (process 907), and the switching circuit is operated. The data is transferred to the data amplifier 3 via the second output line YDL and amplified (process 908), and the data of the memory cell of the sub-array 41 in each cell array is read out continuously to the internal bus line.

In this way, after the data of all the sub-arrays 41 are continuously read, the sense amplifier output line DL2 is set in accordance with the switching signal SW1 in order to subsequently read the data from the memory cells of the sub-array 42 of each cell array. It is selected by the switching circuit 6 of each cell array, and is read all at once to the input terminals of the switching circuit 2 via the cell array output lines YL1 to YL2n. In the switching circuit 2, one of the cell array output lines YL1 to YL2n is switched to the switching signal SW.
2 are sequentially connected, transferred to the data amplifier via the output line YDL of the switching circuit 2, and the data of the memory cells of the sub-array 42 in each cell array are read continuously to the internal bus line (processes 909 and 910).

[0007]

In the method of reading memory cell data described above, the cell arrays belonging to the same column, for example, the sub-arrays 41 to 4m in CA11 to CAk1 of FIG. 8A are switched to continuously read the data. Consider the case. Referring to FIG. 10, which shows a timing chart for explaining a conventional data read method, for example, 2n memory cell data of each sub-array 41 in each cell array CA11 to CAk2n are continuously read, and then a switching signal. SW1 is switched, the sense amplifier output line DL2 to be selected next in the switching circuit 6 is connected in accordance with this signal, and the switching circuit 2 again outputs the output lines YL1 to YL of the switching circuit 6 in accordance with the switching signal SW2.
2n are continuously switched and transferred to the data amplifier 3 via the output line YDL of the switching circuit 2. Therefore, the data of the 2n cell array blocks CA11 to CA1n are continuously read, the sub-arrays in each cell array are switched, and the 2n cell array blocks CA11 to CA1 are again read.
When the data of 2n is continuously read, the output line YL1 between the output terminal of each cell array and the input terminal of the switching circuit 2
Due to the wiring resistance and wiring capacitance of ~ YL2n, a propagation delay occurs in these transferred signals.

Therefore, a discontinuity occurs in the data switching timing on the output line YL corresponding to the switching timing by the data output switching signal SW1, and the switching signal SW2 is switched in response to the delayed data switching timing on YL. Since the timing is switched, a discontinuous portion also occurs in the data output to the output line YDL of the switching circuit 2. When data is read in a low speed cycle, this discontinuity can be ignored, but in the case of a high speed cycle, this discontinuity cannot be ignored.

The object of the present invention has been made in view of the above-mentioned drawbacks, and cell arrays to which switching signals of a switching circuit for controlling data output from m sub-arrays are independently supplied are arranged in k rows and n columns. Data read method of semiconductor memory which has two sets of cell blocks and prevents discontinuity of data output due to propagation delay occurring in transferred signals when reading continuous data from these cell blocks. To provide.

[0010]

The feature of the data reading method of the semiconductor memory of the present invention is that the sub-array in which memory cells are arranged at the intersections of a predetermined number of column lines intersecting the row lines is m (m Are positive integers), m sense amplifiers to which the column lines of these m subarrays are respectively connected, and a first switching circuit to which output lines of these m sense amplifiers are connected. A cell array in which the output of the sense amplifier is selectively output by the first switching circuit in response to a first switching signal generated from an address signal is k (k is a positive integer) rows, 2n (n is a positive integer). Is an integer of k <m <
n) columns, which are composed of cell blocks having 2n data lines in which k output lines of these cell arrays are commonly connected for each column, and are supplied through the 2n data lines of this cell block. What is claimed is: 1. A semiconductor memory comprising a second switching circuit for selectively outputting an output group of a cell array in response to a second switching signal generated from the external address signal, the selection signal for the row line and the sense amplifier activation. When the activation signals are respectively active, the first
Output of the sub-array is selectively output in response to the switching signal, and the second switching circuit selectively supplies the output group consisting of these selected outputs to the internal bus line in response to the second switching signal. In a method of reading data from a semiconductor memory;
It is composed of a first cell block and a second cell block arranged in row n columns and each having the first switching circuit, and the first switching circuit included in the second cell block is supplied with an external address signal. The first cell block is controlled in response to the generated third switching signal, and the first cell block receives the memory cell data output from the m × 2n sub-arrays connected to the m row lines. After reading to the input terminal of the first switching circuit in the block,
Of these data, m × n memory cell data are read from the n first switching circuits to the data line in response to the first switching signal, and the read data is further read by the second switching circuit. In addition to the selective output by the switching circuit, in parallel with the output operation, the remaining m × n memory cell data on the data line are also responded to the third switching signal in the second cell block. A first read method of reading in advance and waiting, and the second cell block is configured to output m × n memory cell data from the n first switching circuits in response to the third switching signal. The data is read to the data line, the read data is further selected and output by the second switching circuit, and in parallel with this output operation, the first cell block also outputs the first data. In response to the switching signal lies in having at least one of the method of the second reading method to wait in advance read the rest of the m × n of said memory cell data on the data lines.

Corresponding identical rows and identical columns of the cell array of the first cell block and the cell array of the second cell block have a pair relationship,
Data is read from n identical columns of one of the two cell blocks, and then data is continuously read from corresponding cell blocks of the same n columns of the other cell block. At the time of performing, by performing using at least one of the first and second reading methods, the switching of the second switching signal can be repeated in the same cycle without having a discontinuous period. .

Further, the cycle of the timing at which the first and third switching signals respectively select and switch the memory cell data on the data line has a repeating period of at least one cycle of the second switching signal. However, the phase of at least one bit of the address signal may be different between the timings.

Furthermore, the switching timing of the first switching signal is either before or after the memory cell data transferred onto the data line is read from the second switching circuit by the second switching signal. On the other hand, the switching timing of the second switching signal and the switching timing of the third switching signal may be set to be opposite to each other before and after the reading.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a main portion of a dynamic memory to which an embodiment of a data reading method of a semiconductor memory of the present invention is applied. Referring to FIG. 1, a cell block 1 having a group of cell arrays CA arranged in k rows and n columns and having output lines YL1 to YLn to which output lines of each column are commonly connected.
a (hereinafter referred to as a block 1a) and a cell array CB group arranged in k rows and n columns, and a cell block 1b having output lines YLn + 1 to YL2n to which output lines in each column are commonly connected.
(Hereinafter referred to as block 1b) and output lines YL1 to YL
n and the output lines YLn + 1 to YL2n are connected to the input ends, and the memory cell data supplied via these output lines are selectively output to the output line YDL in response to the switching signal SW2 generated from the external address signal. The switching circuit 3 and the data amplifier 3 for amplifying the memory cell data supplied via the output line YDL and transferring it to the internal bus line are provided.

The cell array CA of the block 1a and the cell array CB of the block 1b have the same configuration as that of the block shown in FIG. 8B described in the conventional example. That is, referring to FIG. 2 which is a block diagram showing the configuration of the cell array CB in the block 1b, the row lines WL1 and WL
2, ..., A predetermined number of column lines BL1, BL
, ..., BLm at the intersections of the memory cells M11 and M, respectively.
, ..., M1m, ..., and sub-arrays 41, 42, ..., 4m having a group of memory cells connected to each column line as one group, and column lines BL1, BL2 of these m sub-arrays. ,,, BLm connected to m
, 5 m, and the output lines DL1, DL2, ..., Of these m sense amplifiers.
DLm is connected to the first switching circuit 6 and is generated from an external address signal (not shown).
Is the switching signal SW1, and for the cell array CB is the switching signal SW1.
1 of m sense amplifiers in response to each of 11
One of them is selectively output as a signal YL by a switching circuit 6. The difference from the conventional example is that the timings of the switching signals SW1 and SW11 supplied to the switching circuit 6 are supplied at timing different from that of SW1 of the conventional example.

Referring to FIGS. 3 and 4 which are flowcharts showing a method of reading data in the semiconductor memory having the above-described structure, according to an external address signal, for example, each cell array CA11 to CA1n of the block 1a belonging to the same column is. And the desired word line WL1 in each cell array CB11 to CB1n of the block 1b is selected (process 301), and the data of each memory cell M11 to M1m connected thereto is changed to each bit line BL1 to BL1.
It is read by m (process 302). The sense amplifier activation signal is activated, the data read to each bit line BL1 to BLm is amplified, and is transferred to the input terminal of the switching circuit 6 via the output lines DL1 to DLm (process 303).

Next, in accordance with the external address signal, for example, when the external address signal selects DL1 of each sense amplifier output line, each cell array CA11-C of the block 1a.
Switching signal SW1 in A1n is activated in switching circuit 6 so as to connect DL1 of each sense amplifier output line. The data read to DL1 of each cell array CA11 to CA1n of the block 1a is stored in each cell array output line Y.
It is transferred to the input terminal of the switching circuit 2 via L1 to YLn and stands by (process 304). Similarly, the switching signal SW11 in each of the cell arrays CB11 to CB1n of the block 1b is activated in the switching circuit 6 so as to connect DL1 of each sense amplifier output line. The data read to DL1 of each cell array CB11 to CB1n of the block 1b is
Transfer to the input terminal of the switching circuit 2 via each of the cell array output lines YLn + 1 to YL2n and wait (process 30).
5).

Next, either the block 1a or the block 1b is transferred first (process 306). For example, in the case where the block 1a is transferred first, the switching signal SW2 is sequentially selected according to the external address signal. Then
The data on the output lines YL1 to YLn is transferred to the data amplifier 3 via the output line YDL of the switching circuit 2 (Process 30).
7). At this time, selection is sequentially made from YL1 and cell array C is selected.
The output line YLn of A1n is connected by the switching circuit 2 in accordance with the switching signal SW2, the data transferred to the cell array output line YLn is read, and at the same time, the switching signal SW1 in each of the cell arrays CA11 to CA1n in the block 1a is read.
Is switched to a signal for selecting the sense amplifier output line DL2 to be selected next (process 311). In parallel with this processing 311, the data amplifier 3 outputs to the output line YLn of the block 1b.
The data of +1 to YL2n are transferred via the output line YDL (process 310). When the processing 311 is switched, the switching signal SW11 in each of the cell arrays CB11 to CB1n in the block 1b remains activated.

On the other hand, the block 1b shown in FIG.
The switching signal SW2 is sequentially selected, and the output line YD of the switching circuit 2 is selected.
Output lines YLn + 1 to YL2 to the data amplifier 3 via L
The data of n is transferred (process 312). At this time, the transfer sequentially proceeds from the output lines YLn + 1 to YL2n, the output line YL2n of the cell array CB1n is connected by the switching circuit 2 according to the switching signal SW2, and the data transferred to the cell array output line YL2n is read out, and at the same time, in the block 1b. The switching signal SW11 in each of the cell arrays CB11 to CB1n is switched to a signal for selecting the sense amplifier output line DL2 to be selected next (process 316). This process 3
In parallel with 16, data of the output lines YL1 to YLn of the block 1a are transferred to the data amplifier 3 via the output line YDL (process 315). At the time of switching the process 316, the switching signal SW1 in each of the cell arrays CA11 to CA1n in the block 1a remains activated. That is, the switching signals SW1 and SW11 indicate that the other one maintains the activated state when the other one is switched.

Incidentally, in parallel with the execution of the process 307, the output line Y of each cell array CB11 to CB1n of the block 1b.
While Ln + 1 to YL2n are connected by the switching circuit 2 in accordance with the switching signal SW2 to transfer data to the output line YDL of the switching circuit 2, each cell array CA11 to CA in the block 1a is connected.
The data of A1n, that is, the data of the memory cell of the sub-array 42 to be selected next is output lines YL1 to YL of each switching circuit 6 to which the output line DL2 of the sense amplifier is connected.
It is transferred to the input terminal of the switching circuit 2 via n (processes 308 and 309). That is, one of the output data of the block 1a and the output data of the block 1b is the switching circuit 2 respectively.
While the data is being transferred from the data amplifier to the data amplifier 3, the other shows that it is waiting on the input terminal side of the switching circuit 2 (processes 313 and 314).

The above processing operations are sequentially executed for DL1 to DLm and repeated until data transfer is completed for a predetermined cell array or all cell arrays CA11 to CAkn and CB11 to CBkn (processing 317).

As described above, the output lines YLn + 1 to YL2n of the respective cell arrays CB11 to CB1n of the block 1b.
The data that has been read out is sequentially output to the data amplifier in the switching circuit 2, and the switching signal SW2 is set to YL again.
By being activated to select sequentially from 1,
Since the data of the memory cells in the sub-array 42 in each cell array to be subsequently transferred has already been read to the output lines YL1 to YLn of each cell array CA11 to CA1n in the block 1a, the data of the switching circuit 2 is already read. Data can be continuously read at the output without generating a discontinuous portion where data is interrupted at the time of switching.

Next, switching signals SW1, SW11 and S
Referring to FIG. 5A showing the block diagram of the generation circuit of W2 and FIG. 5C showing the operation timing chart thereof, the switching signal generation unit 50 includes the address buffer circuits 501, 502 and 503 and the decoder. 504, 5
05 and 506, the external address signal 1 is supplied to the address buffer circuit 501, and the column address signal is extracted from the address signal 1 to generate the internal address signal 50.
7 and SW from this internal address signal 507
The predetermined switching signal SW1 is decoded by the 1-decoder 504.
Generate Similarly, the external address signal 2 is supplied to the address buffer circuit 502, and the column address signal is extracted from this address signal 2 as an internal address signal 508, and the internal address signal 508 is decoded by the SW11 decoder 505 to a predetermined value. The switching signal SW11 is generated. Further, the external address signal 3 is supplied to the address buffer circuit 503, and the column address signal is extracted from this address signal 3 as an internal address signal 509, and the internal address signal 509 is also used as the SW2 decoder 5.
It is decoded at 06 to generate a predetermined switching signal SW2.

In the timing chart of FIG. 5C, SW
1 and SW11 are shown at the same timing,
It is preset at different predetermined timings by the system operation of the memory circuit to which this embodiment is applied.

Further, as shown in FIG. 5B, the switching signal SW2 has a structure in which the address generating circuit 510 is connected to the above-mentioned address buffer circuit 503 so that the external address signal 3 whose timing changes bit by bit. It is also possible to fetch only the head address and then switch the internal address signal 509 by the address generation circuit 503.

Next, FIG. 6 is a timing chart for explaining the operation of SW1 and SW11, showing a case where SW1 is switched after the data transferred to the output line YLn of the cell array CA is read by SW2. , And FIG. 7 showing the case where SW1 is switched before the data transferred to the output line YL1 of the cell array CA is read by SW2. Referring to FIG.
When the row line WL1 is selected and the sense amplifier activation signal is active, T1 of the switching signal SW1 indicates the DL1 selection period of the sub array 41 in the cell array CA, and T2 is D of the sub array 42 in the cell array CA.
The L2 selection period is shown.

T3 of the switching signal SW11 is a cell array CB.
The DL1 selection period of the sub-array 41 in
Indicates the DL2 selection period of the sub-array 42 in the cell array CB.

The output lines YL1 to YL of the cell array CA are also provided.
The signal T1 'output to Ln is the DL of the switching signal SW1.
Corresponding to one selection period T1, T2 ′ is D of the switching signal SW1.
It shows that it corresponds to the L2 selection period T2.

Further, the output line Y in the cell array CB
It is shown that T3 ′ of the signals output to Ln + 1 to YL2n corresponds to the DL1 selection period T3 of the switching signal SW1 and T4 ′ corresponds to the DL2 selection signal T2 of the switching signal SW1.

Referring to these timing charts, the switching signal S is output to the output line YDL of the switching circuit 2 from the start of transfer in synchronization with the switching timing of the switching signal SW2.
In the DL1 selection period T1 of the W1 cell array CA, the data of the output lines YL1 to YLn of the cell array CA are transferred,
During this period, the output lines YLn + 1 to 1 of the cell array CB are simultaneously
DL1 data of the sub-array 41 in the cell array CB is waiting on the YL2n in response to the DL1 selection period T3 of the SW11.

After YLn of the cell array CA is read, the switching signal SW1 switches to the DL2 selection period T2 of the cell array CA, and the switching signal SW2 is output to the output line YDL.
The data of DL1 which has been waiting is transferred to the output lines YLn + 1 to YL2n of the cell array CB in synchronization with the switching timing of the above, and during this period, the output lines YL1 to YLn of the cell array CA are simultaneously responded to the DL2 selection period T2 of SW1. DL2 of the sub-array 42 in the cell array CA
Data is waiting.

Then, the output line YL in the cell array CB.
After the 2n DL1 data is read at the switching timing of the switching signal SW2, the switching signal SW11 becomes DL.
When the selection period T3 is switched to the DL2 selection period T4, the output line YDL has output lines YL1 to YL1 of the cell array CA.
The data of DL2 waiting in YLn is transferred, and at the same time, the cell array C is output on the output lines YLn + 1 to YL2n of the cell array CB in response to the DL2 selection period T4 of SW11.
DL2 data of sub-array 42 in B waits.
After that, the data transfer is executed by the same operation.

On the other hand, in FIG. 7, the DL1 selection period T1 of the switching signal SW1 and the DL1 selection period T1 'of the output lines YL1 to YLn, the DL2 selection period T2 and the DL2 selection period T2' of the output lines YL1 to YLn in the cell array CA are shown. , D of the switching signal SW11 in the cell array CB
The relationship between the L1 selection period T3 and the DL1 selection period T3 ′ of the output lines YLn + 1 to YL2n, the DL2 selection period T4, and the DL2 selection period T4 ′ of the output lines YLn + 1 to YL2n is the same as in FIG.

Referring to these timing charts, the output line YDL of the switching circuit 2 is synchronized with the data switching timings on the output lines YLn1 to YLn by the switching signal SW2, and the cell array CA of the switching signal SW1 is transferred to the output line YDL of the switching circuit 2 from the start of transfer. Cell array C in DL1 selection period T1
Data on the output lines YL1 to YLn of A are transferred, and during this period, the output lines YLn + 1 to YL2 of the cell array CB are simultaneously transmitted.
On the n, DL1 data of the sub-array 41 in the cell array CB is waiting in response to the DL1 selection period T3 of SW11.

After YLn of the cell array CA is read out, the cell array CB is connected to the output line YDL in synchronization with the switching timing of the switching signal SW2 from YLn + 1 to YL2n.
The data of DL1 which has been waiting is transferred to the output lines YLn + 1 to YL2n. Next, the switching signal SW2 is set to YL1 again.
Up to the switching timing of YLn, the YL1 data of DL1 is read again in that state, so that SW1 is DL2 of the next cell array CA before that.
By switching to the selection period T2, the cell array CA
Sub-array 42 output onto the output lines YL1 to YLn of
The DL2 data is transferred to YDL in synchronization with the switching timing of the switching signal SW2 from YL1 to YLn. At this time, DL2 data is transferred to the output lines YL1 to YLn of the cell array CA, and at the same time, the switching signal SW11 also switches to the DL2 selection period T4.

Therefore, while the DL2 data of the output lines YL1 to YLn of the cell array CA are being transferred to the YDL of the T2 period, the output line YLn + of the cell array CB is simultaneously generated.
1 to YL2n, DL2 of the sub-array 42 in the cell array CB in response to the DL2 selection period T4 of SW11.
Data is waiting.

Subsequently, the DL2 data of the cell array CA is read out via the output line YLn, and then the switching signal SW.
2 YLn + 1 to YL2n switching timing is synchronized with the output line YDL to the output line YLn + 1 of the cell array CB.
The data of DL2 that has been waiting in YL2n is transferred. Thereafter, similar operations are repeated to execute data transfer.

In the above-described embodiment, as an example, the sub-arrays 41 and 42 in the cell arrays CA and CB are used.
However, the switching signals SW1 and SW11 are
It is possible to select up to 4 m of sub-arrays.

As described above, in the present embodiment, when data is continuously read from the cell arrays belonging to the same 2n pairs of 2n pairs, the data is transferred to the output line YLn of the cell array CA. When the switching signal SW1 is switched after the data is read by the switching signal SW2, or when the switching signal SW1 is switched before the data transferred to the output line YL1 of the cell array CA is read by the switching signal SW2. In either case, when the data of one block 1a is being read, the data of the other block 1b can be prepared halfway, so that the data can be continuously written compared to the conventional example. Data can be read, and even if the data cycle width is shortened, data can be read continuously at high speed.

[0041]

As described above, according to the method of reading data of the semiconductor memory of the present invention, the cell array of the first block and the cell array of the second block, which respectively have m × n memory cell data, correspond to each other. And the same column are paired semiconductor memories, and n of one of these two blocks is
When data is read from the cell blocks of the same column of the book and subsequently data is continuously read from the cell blocks of the corresponding n columns of the other block,
Of the m × 2n memory cell data, the m × n memory cell data output from the first block is read from the first switching circuit to the data line in response to the first switching signal, and this reading is performed. The selected data is further selectively output by the second switching circuit, and the second operation is performed in parallel with this output operation.
Also in the block, the first read method of reading the remaining m × n memory cell data on the data line in advance in response to the third switching signal, and the second read method, and the second read method.
Block reads m × n memory cell data from the first switching circuit to the data line in response to the third switching signal, and the read data is further selectively output by the second switching circuit. 1st in parallel with output operation
Even in the block, the data is read by using at least one of the second read methods of reading the remaining m × n memory cell data on the data line in advance and waiting in response to the first switching signal. By executing this, when the data of one cell array block is being read, the data of the other cell array block can be prepared halfway, so the switching of the second switching circuit is discontinuous compared to the conventional example. Data can be continuously read without having a period, and even when the data cycle width is shortened, data can be continuously read at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a semiconductor memory targeted by a method of reading data from a semiconductor memory according to the present invention.

FIG. 2 is a block diagram showing a main part of a cell block included in a semiconductor memory that is a target of the present embodiment.

FIG. 3 is a flowchart for explaining a data reading method of a semiconductor memory according to the present invention.

FIG. 4 is a flowchart for explaining a data reading method of a semiconductor memory of the present invention.

FIG. 5A is a block diagram showing switching signals SW1, SW11, and SW2 generation units used in the data reading method of the semiconductor memory of the present invention. FIG. 9B is a block diagram showing another example of the SW2 generation unit. (C) is a timing chart of the switching signals SW1, SW11, and SW2 generation units.

FIG. 6 is an explanatory timing chart showing a case where SW1 is switched after the data transferred to the output line YLn of the cell array CA is read by the SW2 in the embodiment of the invention.

FIG. 7 is an explanatory timing chart showing a case where SW1 is switched before the data transferred to the output line YL1 of the cell array CA is read by SW2 in the embodiment of the present invention.

FIG. 8A is a block diagram showing a main part of a semiconductor memory targeted by a data reading method of a semiconductor memory in a conventional example. (B) It is a block diagram which shows the principal part of the cell block which the semiconductor memory in a prior art example has.

FIG. 9 is a flowchart for explaining a data reading method of a semiconductor memory in a conventional example.

FIG. 10 is a timing chart for explaining a data reading method of a semiconductor memory in a conventional example.

[Explanation of symbols]

1a, 1b Block 2, 6 Switching circuit 3 Data amplifier 41-4m Sub-array 51-5m Sense amplifier (SAMP) CA11-CAkn Cell array of block 1a CB11-CBkn Cell array of block 1b DL1-DLm Sense amplifier output line of sub-array 41-4m M11 to M2m memory cells SW1, SW11, SW2 switching signal YL1 to YLn output line of block 1a YLn + 1 to YL2n output line of block 1b

Claims (4)

[Claims] 1. A sub-array in which memory cells are arranged at intersections of a predetermined number of column lines intersecting with row lines is m.
(M is a positive integer) and m sense amplifiers to which the column lines of these m subarrays are connected, respectively, and these m sense amplifiers.
A first switching circuit to which the output lines of the individual sense amplifiers are connected, and the output of the sense amplifier is selected by the first switching circuit in response to a first switching signal generated from an external address signal. Output cell arrays are arranged in k (k is a positive integer) rows and 2n (n is a positive integer and k <m <n) columns, and k output lines of these cell arrays are commonly connected to each column. A cell block having 2n data lines, the output group of the cell array supplied through the 2n data lines of the cell block in response to a second switching signal generated from the external address signal. A semiconductor memory having a second switching circuit for selectively outputting,
When the selection signal of the row line and the sense amplifier activation signal are respectively active, the output of the sub-array is selectively output in response to the first switching signal, and the output group including these selection outputs is output as the second output group. In the data reading method of the semiconductor memory in which the second switching circuit selectively supplies the internal bus line in response to the switching signal of the above; the cell block has the cell arrays arranged in k rows and n columns, and Of the first cell block and the second cell block, each of which has a switching circuit, and the first switching circuit included in the second cell block responds to a third switching signal generated from an external address signal. Memory cells output from the m × 2n sub-arrays connected to the m row lines Wherein the chromatography data of the own cell block first
Read out to the input terminal of the switching circuit, and read out m × n memory cell data of these data from the n first switching circuits to the data line in response to the first switching signal. The read data is further selectively output by the second switching circuit and, in parallel with the output operation, remains on the data line in the second cell block in response to the third switching signal. M
A first read method of reading out × n pieces of the memory cell data in advance and waiting, and the second cell block outputs n × m pieces of the memory cell data in response to the third switching signal. Read from the first switching circuit to the data line, the read data is further selected and output by the second switching circuit, and in parallel with the output operation, the first cell block also outputs the data. Data of a semiconductor memory having at least one of a second read method of previously reading the remaining m × n memory cell data on the data line in response to the switching signal of 1 and waiting. Read method. 2. The corresponding same row and the same column of the cell array of the first cell block and the cell array of the second cell block are in a pair relationship, and one cell of these two cell blocks is in a pair relationship. When data is read from n same columns of a block and subsequently data is continuously read from corresponding cell blocks of the same n columns of the other cell block, the first and the first 2. The semiconductor memory according to claim 1, wherein the switching of the second switching signal is repeated in the same cycle without having a discontinuous period by executing it by using at least one of the two reading methods. Data read method. 3. A cycle of timing at which each of the first and third switching signals selects and switches memory cell data on the data line has a repetition period of at least one cycle of the second switching signal. 2. The method of reading data of a semiconductor memory according to claim 1, wherein the phases of at least one bit of the address signal are different between the timings. 4. The switching timing of the first switching signal is either before or after the memory cell data transferred onto the data line is read from the second switching circuit by the second switching signal. On the other hand, it is set within the switching timing period of the second switching signal, and the switching timing of the third switching signal is opposite to that before the reading and after the reading. The method for reading data from a semiconductor memory according to claim 1.