JPH0869359A - Disk array device - Google Patents

Abstract

PURPOSE: To improve the performance of the entire disk array device without deterioration in the entire performance due to the cause of the presence of a storage device with low performance even when plural storage devices whose performance or capacity differs from each other are employed to form the disk array device. CONSTITUTION: The size of shared data is changed depending on the processing speed of each storage device being a component of a logical group 15 in the disk array device. Read/write in each storage device is executed depending on the division ratio to average a processing time when each storage device is accessed in parallel. Thus, a data transfer time among storage devices (drives 14) being components of the disk array device is averaged to improve the processing performance. That is, even when the logical group 15 is formed by employing storage devices whose processing speed differs from each other in mixture, the suppression of the entire processing speed due to the presence of storage devices whose processing speed is low is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array device, and more particularly to a file system capable of high performance input / output operation.

[0002]

2. Description of the Related Art In a current computer system, data required by a high-order side such as a CPU is stored in a secondary storage device, and the data is stored in the secondary storage device as needed by the CPU. -Writing and reading data. A non-volatile storage medium is generally used as the secondary storage device, and typical examples thereof include a magnetic disk device (hereinafter referred to as a drive) and an optical disk.

In recent years, as computerization has advanced, there has been a demand for higher performance of this type of secondary storage device in computer systems. As one solution, a disk array composed of a large number of drives each having a relatively small capacity is considered.

As a known document, "D. Patterson, G. Gibs
on, and RHKartz; A Case for Redundant Arrays of In
expensive Disks (RAID), in ACM SIGMOD Conference, Chi
cago, IL, (June 1988) ”. In this document, a disk array (level 1) for duplicating data, a disk array (level 3) for dividing data and processing in parallel, and a disk array (level 4, 5) for separately handling data separately. ), The results of examination of its performance and reliability have been reported. The method currently described in this paper is considered to be the most common disk array.

First, a level 3 disk array will be briefly described. In the level 3 disk array, one piece of data given from the upper level is divided into 1-byte units, and the divided data is distributed and stored in a plurality of drives. When reading the data, the divided data pieces are collected from a plurality of drives, combined, and transferred to a higher level. Therefore, at level 3, parallel processing can be performed by a plurality of drives, and the transfer speed can be improved.

Next, a disk array (level 5) in which individual data is distributed without dividing the data and handled independently will be described. Level 4 is such that the parity distributed in each drive forming the disk array in level 5 is stored in one drive that stores only parity.

In the level 4 and level 5 disk arrays, individual data is handled independently without being divided, and is distributed and stored in a large number of relatively small capacity drives. In a secondary storage device of a general-purpose large-scale computer system that is generally used at present, since the capacity per drive is large, the drive is used for another read / write request, and the drive cannot be used and is kept waiting. Many things happened. In this level 5 (or 4) disk array,
Since a large-capacity drive used in a secondary storage device of a general-purpose large-scale computer system is composed of a large number of relatively small-capacity drives to store data in a distributed manner,
Even if the number of read / write requests increases, it will be possible to perform processing distributedly among multiple drives in the disk array.
Waiting for read / write requests is reduced.

Next, the parity in the disk array will be described. Since the disk array comprises a conventional large-capacity drive with a large number of relatively small-capacity drives, the number of parts increases and the probability of failure increases. For this reason, parity is prepared in the disk array.

Parity is created by taking the exclusive OR for each corresponding bit between corresponding data in each drive constituting the disk array. The parity created in this way is stored in a drive other than the data in which the data involved in creating the parity is stored.

A set of drives recoverable when a failure occurs in a certain drive among the drives forming the disk array is called a logical group. In addition, a set of data that creates parity in a logical group and parity data created from these data are collectively referred to as a parity group.

When a failure occurs in any one of the drives forming the logical group, each data in the failed drive is the data in the normal drive for each parity group to which the data belongs. It is possible to restore by taking the exclusive OR of the and parity.

As such a disk array, one using a drive (magnetic disk device) as a storage medium has been realized and studied. Recently, it has been considered to use a non-volatile semiconductor memory such as a flash memory instead of using a drive. For example, JP-A-5-27
No. 924 discloses a method of using an EEPROM, which is a non-volatile semiconductor memory, in place of a magnetic disk in an external storage device.

[0013]

In the conventional level 3 processing in a disk array, one data is stored by dividing it into a plurality of drives for each byte, and when reading out, the divided data is collected from a plurality of drives. To combine and transfer to the upper level. Therefore, at level 3, parallel processing by a plurality of drives becomes possible, and the transfer speed can be improved.

At level 3, data of equal capacity is assigned to each drive forming the logical group.
If the performance of all the drives constituting the logical group of the disk array is equal, the transfer rate becomes "the parallel number of drives x the transfer rate of one drive" by the level 3 parallel processing. However, when the drives in the logical groups have different performances, the performance of the entire disk array is limited by the performance of the drive with the lowest performance.

For example, a logical group is composed of five drives # 1 to # 5, and drives # 1, # 2,
It is assumed that the transfer rates of # 3 and # 5 are 6 MB / s and only the drive # 4 has 3 MB / s. When data is stored at the conventional level 3, data of equal capacity is allocated to each of the drives # 1 to # 5. In this case, the transfer process in each drive is performed in parallel, but since the data transfer time of the drive # 4 is twice as long as the transfer time of the drive # 1 and the like, the drives # 1, # 2, # 3, #
In No. 5, even if the data transfer is completed, it is necessary to wait until the transfer of the drive # 4 is completed. Therefore, the performance of this disk array is ultimately determined by the transfer performance of drive # 4.

An object of the present invention is that even if a disk array device is constructed using a plurality of storage devices having different performances and capacities, there is a storage device having a low performance and the overall performance is degraded. It is intended to improve the performance of the disk array device as a whole without causing such a problem.

[0017]

Therefore, according to the present invention, in a disk array device comprising a plurality of storage devices forming a logical group and a control device for controlling the storage devices, the processing speed of each storage device is increased. The size of the distributed data is changed accordingly. That is, a small amount of data is assigned to a storage device having a low processing speed, and a large amount of data is assigned to a storage device having a high processing speed.

Specifically, m (m is an integer of 2 or more) data storage devices for striping and storing the data given by the host device, and the data stored in the m data storage devices. A logical group is composed of n (n is an integer of 1 or more) error correction code storage devices for storing the error correction code created from
In a disk array device equipped with a control device for controlling these storage devices, the relative ratios of the processing speeds of the m data storage devices and the n error correction code storage devices are sequentially k1: k2: ...: ki :. When the striping unit is represented by u, the minimum access unit of each storage device is represented by the relative ratio ki (i = 1 to m + n) of the processing speed of the storage device and The product of striping unit u is k i · u. What is processing speed?
It is the processing time when reading or writing data such as the rotation waiting time and transfer speed in the disk drive.

The relative ratio of processing speeds may be maintained in an address table and managed. The error correction code may be any code as long as it is created from data stored in m data storage devices. The error correction code is 1
Not only the types, but also a plurality of types of error correction codes may be created and stored.

When the allocation of the amount of data to be stored in the storage device is changed according to the processing time of each storage device in this way, when a certain amount of data is written, only one storage device will be full at the beginning. There is. In that case, it is advisable to configure the disk array with the remaining storage devices.

As the storage device, in addition to a disk drive, a non-volatile semiconductor memory device such as a flash memory may be used.

[0022]

According to the present invention, since the size of data to be distributed is changed according to the processing speed of each storage device forming a logical group, parallel transfer is performed in each storage device of the logical group. It is possible to average the data transfer time among the storage devices in the logical group. Therefore, even if the logical group is configured by mixing the storage devices having different processing speeds, it is not possible to suppress the overall processing speed due to the existence of the storage device having the slow processing speed.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 shows the overall configuration of a disk array device according to a first embodiment of the present invention. In this embodiment, a disk array controller (hereinafter referred to as an ADC) 2 that controls RAID level 3 is composed of a control unit and a logical group 15. CPU1
It is a higher-level device that issues a read command and a write command to the ADC 2. Logical group 15 has m drives 14
And a drive path 16 that connects each drive 14 to the drive interface circuit (Drive IF) 13 of the control unit. In addition, this drive 1
The number of 4 is not particularly limited in order to obtain the effect of the present invention.

This logical group 15 is a recovery unit of drive failure, and each drive 1 in this logical group 15
Parity is created from each data in 4. A set of data that creates parity in the logical group 15 and the parity created from these data are combined to form a parity group.

The command issued from the CPU 1 is input to the interface adapter (hereinafter referred to as IF Adp) 4 of the ADC 2 through the external interface path 3. The IF Adp4 determines whether the command issued from the CPU 1 can be accepted.

Specifically, as shown in FIG. 1, the CPU 1
The command sent from ADC to ADC2 is IF A
It is taken in by dp4. The MP9, which is a microprocessor, performs the accepting process when the process is possible, and sends a response of unacceptable to the CPU1 when the process is impossible. After the command can be accepted in this way, a read process or a write process (new or update) as described later is started.

Before describing the read processing and the write processing, the method of dividing and storing data in the ADC 2 of this embodiment will be specifically described with reference to FIG.
As described above, the present embodiment is basically based on the RAID level 3 control, but since there is a characteristic part according to the present invention, there is a part different from the normal RAID level 3 control.

In FIG. 2, each of the rectangles marked with 1, 2, 3, ..., N represents individual divided data (referred to as data 1, data 2, ...), and these data are It is stored in the drives (Drive) # 1 to # 4. D
drive # 5 is a parity disk.

As will be described later in detail, in the present embodiment, Dr among Drive # 1 to Drive # 5 forming the logical group is Dr.
The transfer speed of ive # 1, # 2, # 3, # 5 is 6MB / s
And the transfer speed of Drive # 4 is 3 MB / s.

In this case, in the conventional RAID level 3 control, data of the same size is equally distributed regardless of the performance of each drive. That is, the parity P1 is created using data 1 to data 4, and each data is driven
# 1 to # 5 are stored, parity P2 is created using data 5 to data 8, and each data is driven to Drive # 1 to # 5.
The data is stored in # 5, and so on. The drives are accessed in parallel, but
Since the transfer speed of e # 4 is half of the transfer speed of other drives, even if the data transfer ends in Drive # 1, # 2, # 3, and # 5, wait until the transfer of Drive # 4 ends. It must be done, and overall performance will not improve.

Therefore, in the present embodiment, considering that the transfer speed of the Drive # 4 is half the transfer speed of the other drive, the capacity of the data stored in the Drive # 4 is smaller than that of the data stored in the other drive. Allocation is made to be half of the capacity. That is, as shown in FIG.
data # 1 and data 2 for ve # 1, data 3 and data 4 for Drive # 2, and data 5 for Drive # 3
And data 6 are stored respectively. Also, Drive #
Data 4 is stored in 4. Then, a parity P1 is created from data 1, data 3, data 5, and data 7, a parity P2 is created from data 2, data 4, and data 6, and these parities P1 and P2 are Drive #, which is a parity disk. Store it in 5.

As a result, when the drives are accessed in parallel, the transfer amount of Drive # 4 is half the transfer amount of the other drives, so that the performance is improved as a whole.

Next, specific read processing and write processing in this embodiment will be described. First, the initial setting method for each drive of the logical group will be described.

(Initial setting method) In this embodiment, as shown in FIG. 1, a logical group 15 is composed of five drives 14. In the logical group 15, basically, CP
A parity group (RAID level 3) is configured by 4 data obtained by dividing the data from U1 into 1-byte units and 1 parity (4D + 1P). However, Figure 2
As described above, in this embodiment, a parity group of 3 data and 1 parity (3D + 1P) is also mixed.

In FIG. 3, the address designated by the CPU 1 when issuing a read or write request is the drive 14
Address table 2 used when converting to other addresses
It is 1. The address table 21 exists in the cache memory 8 and is stored in MP9 when the system is powered on.
CPU from the specific one or more drives 14 in the logical group 15 to the cache memory 8
It is automatically read without knowledge of 1. On the other hand, when the power is turned off, the drive 14 that has read the address table 21 in the cache memory 8 by the MP 9
The data is automatically stored in a predetermined place therein without any knowledge of the CPU 1.

In FIG. 3, the address table 21 is
Logical group number 22, data name 23, drive number 2
4, division ratio 25, in-drive address 26, and cache address 27.

A number for specifying one logical group is registered in the logical group number 22. A logical address designated by the CPU 1 is registered in the data name 23. A portion where the data name 23 is not registered indicates a free area. In the cache address 27, when the data corresponding to the data name 23 exists in the cache memory 8, the address in the cache memory 8 is registered. On the other hand, when the cache address 27 is not registered (blank), it indicates that the data of this data name 23 does not exist in the cache memory 8.

In the drive number 24, the number of the drive 14 in which each data of the data name 23 is stored is registered. In the division ratio 25, a data allocation ratio for each drive is set. The in-drive address 26 is set to an address indicating where the data of the data name 23 is stored in each drive of the drive number 24.

In this example, the division ratio 25 of Drive # 4 is 1 and the division ratio 25 of the other Drives # 1, # 2, # 3, and # 5 is 2, so the drive address of Drive # 4 is The capacity of the data stored at the address indicated by 26 is half the capacity of the data stored at the address indicated by the in-drive address 26 of the other Drives # 1, # 2, # 3, and # 5. . For example, when FIG. 2 and FIG. 3 are associated with each other, Data # 1 in FIG.
~ Address Add of Drive # 1 corresponding to data 7
At the position of r11, the data 1 and 2 of FIG.
2 at the address Addr21 of FIG.
4 is at the address Addr31 of Drive # 3, and the data 5 and 6 of FIG. 2 are at the address A of Drive # 4.
At the position of ddr41, the data 7 of FIG.
At the position of the address Addr51 of No. 5, the parity P of FIG.
1 and P2 are stored respectively.

FIG. 4 shows a processing flowchart when the MP9 is initialized. The initial setting method will be described with reference to FIG.

First, when the system administrator makes an initial setting, the drives 14 constituting the logical group 15 are determined. For example, when it is desired to configure the logical group 15 having the logical group number LG # 1 with the drives 14 of Drive # 1, # 2, # 3, # 4, and # 5, the system administrator sets the logical table to the address table 21. L for group number 22
G # 1 is registered (step 40), and Dr is added to the drive number 24 of the drives that make up this logical group 15.
ive # 1, # 2, # 3, # 4, # 5 are respectively registered (step 41).

Registration to the address table 21 is performed by the system administrator using the MP9 of the ADC 2 to the address table 21 in the cache memory 8. Next, the system administrator sets the division ratio 25 of level 3 according to the performance of each drive 14 of the set logical group 15 (step 42). In this example, Drive # 1, #
The transfer speed of 2, # 3, # 5 is 6MB / s, and Drive
The transfer rate of # 4 is 3 MB / s. In this case, Dri
Since the transfer rate of ve # 4 is half of the transfer rate of Drive # 1, etc., the data allocation ratio for Drive # 1, # 2, # 3, # 5 and Drive # 4 is 2: 1. Therefore, Drive # in the address table 21
2 is set to the division ratio 25 of 1, # 2, # 3, and # 5, and D
1 is set to the division ratio 25 of live # 4.

In the above description, the system administrator sets the division ratio in consideration of the performance of the drives 14 in the logical group 15. However, when setting the drive 14, A
It is also possible for the MP9 in the DC2 to automatically set the division ratio from the performance of the drive 14 at the same time.

(Address Conversion Method) Next, an address conversion method using the address table of FIG. 3 will be described.

C indicating a read or write request
The PU 1 specifies the logical group number 22 and the data name 23 as the address. Read or write request from CPU1 and MP of ADC2 that received the address
9 determines the drive number 24 and the in-drive address 26 where the data is actually stored by the address table 21 as shown in FIG. At this time, the address table 21 recognizes the division ratio of the read or write data for each drive 14.

For example, referring to FIG.
When a read request is issued to Data # 1 of the logical group 15 of No. 1, the address where this data is stored can be known from the address table 21. The addresses are Addr11 and Drive # 2 of Drive # 1.
Addr21, Drive # 3 Addr31, Dr
This is Addr41 of ive # 4. Also, the parity is D
It can be seen that it is stored in Addr 51 of live # 5. Further, it can be seen that Drive # 1, # 2, # 3, # 5 has a division ratio of 2, and Drive # 4 has a division ratio of 1.

In this way, the drive 14 that actually reads / writes the address designated by the CPU 1
After the address is converted into the address, the read or write request is issued to the in-drive address 26 of the drive 14. The size of read or write data to each drive is a size according to the division ratio.

Next, a processing method for performing such address conversion and specifically reading or writing data will be described.

(New Writing Processing) FIG. 5 shows a processing flowchart of the MP9 when newly writing data.
A method for newly writing data will be described with reference to FIGS. 5 and 1.

When the command from the CPU 1 is received, A
The MP9 of the DC2 checks whether the command can be processed, and if yes, returns a response indicating that the command can be processed to the CPU1 (step 51). The command issued by the CPU1 is fetched by the ADC2 via the IF Adp4, and the M
A read request or a write request is decoded by P9 (step 52). In the case of a write request, it is processed as follows. The read process will be described later with reference to FIG.

After the CPU 1 receives the response that the processing is possible, the write data is transferred to the ADC 2. At this time, in ADC2, IF A
Establishes a connection between dp4 and CPU1 (step 5)
3). After establishing the connection between CPU1 and ADC2,
Data transfer from the CPU 1 is accepted.

From the CPU 1, the logical group number 22, the data name 23 and the write data are transferred. CH I
In response to the instruction from MP9, F5 performs protocol conversion on these data transferred from CPU1 (step 54). Thereby, the speed of the data from the CPU 1 is adjusted from the transfer speed in the external path 3 to the processing speed in the ADC 2. Specifically, when the channel interface between the CPU 1 and the ADC 2 is an optical interface, the CH IF 5 converts the protocol of the optical interface into a protocol for electrical processing in the ADC 2.

After completion of protocol conversion and speed control in CH IF5, the data is transferred to the data control circuit (DC
C) Under the data transfer control by C6, it is transferred to the cache adapter circuit (C Adp) 7 and stored in the cache memory 8 by C Adp7 (step 5).
5). The C Adp 7 is a circuit that reads and writes data from and to the cache memory 8 in response to an instruction from the MP 9, and monitors the state of the cache memory 8.
It is a circuit that performs exclusive control for each read and write request.

When the MP9 recognizes the write request command and further recognizes that the data to be written is new data to be written for the first time, the MP9 starts the process of registering the data name 23 sent from the CPU 1 in the address table 21.

Specifically, the following is done. First, in the address table 21, no data is registered in the in-drive address 26 in which the data name 23 is not registered. Therefore, when writing new data, the MP 9 sets the logical group 22 in the address table 21.
On the other hand, if the address 26 in the drive in which the data name 23 is not registered is searched and found, the data name 23 is registered in the address 26 in the drive (step 5).
6). As described above, in the address table 21,
By recognizing a new data writing area and registering the data name 22 in the relevant section of the address table 21,
Register new write data.

In this embodiment, the parity is created in each drive 14 forming the logical group 15 as shown in FIG. 2 and stored in Drive # 5. MP9
Refers to the address table 21 from the address designated by the CPU 1 and recognizes the drive number 26 of the drive 14 storing the data and parity and the drive address 26 in the drive 14 (step 57).

For example, the MP9 is the Drive # 1, #
In-drive address 26 of 2, # 3 and # 4 is Addr1
Assume that it is recognized that Data # 1 is newly written at the positions of 1, Addr21, Addr31, and Addr41. At this time, MP9 uses Dr.
The in-drive address 26 of ive # 5 recognizes that the parity is stored at the position of Addr 51.

In this way, after recognizing the drive number 24 and the in-drive address 26 for writing the newly written data and the parity of the data, the MP9 drives
Writing processing of newly writing data and parity to # 1, # 2, # 3, # 4, and # 5 is started (step 5).
8).

MP9 is a driver for Drive IF13.
The drive 14 is instructed to issue a new write data and new parity write request (step 5).
9). The Drive IF 13 issues a write command to the drive 14 via the drive path 16 according to the SCSI write processing procedure. Driv
In the drive 14 to which the write command has been issued from the eIF 13, the seek and rotation waiting access processing is performed to the designated in-drive address 26.

After the access processing in the drive 14 is completed, the cache adapter circuit (C Adp) 10
Reads newly written data from the cache memory 8. At this time, the MP 9 refers to the address table 21 and checks the division ratio (step 60). In FIG.
Drive # 1, # 2, # 3 of logical group LG # 1
In # 4 and # 5, the division ratio is Drive # 1, # 2,
# 3 and # 5 are 2, and Drive # 4 is 1. After recognizing the division ratio, the MP 9 instructs the C Adp 10 to read the data from the cache memory 8 according to this division ratio (step 61). C A who received this instruction
The dp 10 reads the data from the cache memory 8 according to this division ratio.

In this embodiment, as shown in FIG.
As data to be assigned to drives # 1, # 2, and # 3, 2 bytes are taken out from the beginning of the data in the cache memory 8, and then 1 byte is taken as data to be assigned to Drive # 4. From cache memory 8 to C Ad
FIG. 6 shows a flowchart for reading the data in p10.

In FIG. 6, C Adp10 is MP9
When receiving a read instruction from the computer (step 81), C A
The read counter in dp10 is reset (cleared to zero). Next, 1 is added to the counter value (step 82). The counter value obtained by adding 1 is divided by 4, and it is determined whether or not the remainder is 0 (step 83). If the remainder is not 0, 2 bytes are read from the cache memory 8 (step 84) and the process proceeds to step 86. if,
If the remainder is 0, the cache memory 8 to 1
Byte read (step 85), and the process proceeds to step 86.

The data read in this way is P
It is transferred to G11 (step 86), and parity is created in PG11. The method of creating the parity in PG11 will be described later. After transferring the data to the PG 11, the value of the read number counter is checked to determine whether or not the data transfer of the predetermined data amount is completed (step 87). The determination by the read number counter is performed as follows.

As can be seen from FIG. 6, the fact that the read number counter is incremented by 4 means that 7-byte data has been read from the cache memory 8. Therefore, if the unit of one read or write request from the CPU 1 is 4 KB, the counter value is 2
When 288 (= 4 KB ÷ 7 × 4) is reached, 4 KB data transfer is completed. Therefore, each time the transfer to the PG 11 is completed, the C Adp 10 checks the read number counter value in step 87 and makes a determination. If the result of this determination is that the reading of all data has not been completed, the next byte is read. If completed, the reading from the cache memory 8 ends.

In this way, data is taken out according to the division ratio of each drive 14 in the logical group. These extracted data are called divided data. In this example,
The divided data is either 1 byte or 2 bytes. Specifically, the divided data stored in each drive of Drive # 1, # 2, and # 3 is 2 bytes, and the divided data stored in Drive # 4 is 1 byte.

The new write data read from the cache memory 8 to C Adp 10 as described above is
It is transferred to the parity generation circuit (PG) 11 and the parity is created in PG 11.

The parity is created as shown in FIG. That is, among the divided data (2 bytes or 1 byte) assigned to each drive 14, the odd byte (that is, the 1st byte) is Drive
Parity is created from the corresponding bytes (first byte) of the four divided data stored in the drives 14 of # 1, # 2, # 3, and # 4. For even-numbered bytes (that is, the second byte), Drive # 1, # 2,
Parity is created from the corresponding bytes (second byte) of the three divided data stored in each drive 14 of # 3. Therefore, FIG. 7 shows a flowchart of a method of creating a parity.

In FIG. 7, the 1-byte or 2-byte data transferred from C Adp 10 is sequentially set in registers 1, 2, 3, and 4 in PG11 (step 90). Each time transfer data is set in the register in the PG 11, the value in the PG counter is incremented (step 91). The counter in the PG is CAd.
It shall be initialized to 0 before receiving the data transfer from p10.

Next, the value of the PG counter is divided by 4, and it is determined whether the remainder is 0 (step 92). If the remainder of the in-PG counter is not 0 in this determination, the process returns to step 90 to continue storing data in the in-PG registers 1, 2, 3, and 4 (step 93). If the remainder is 0, it means that 7-byte data has been set in the registers 1, 2, 3 and 4 in the PG, so the routine proceeds to step 94.

As described with reference to FIG. 6, the data from C Adp 10 is transferred in the order of 2 bytes, 2 bytes, 2 bytes and 1 byte. Therefore, at the time of proceeding from step 92 to step 94, the first 2 bytes are stored in the register 1 in the PG 11, the next 2 bytes are stored in the register 2, the next 2 bytes are stored in the register 3, and the last 1 bytes are stored in the register 4. Each byte is set.

Next, the data is read from the registers 1, 2, 3, 4 byte by byte (step 94), and the parity is created from the 4-byte data (step 95).
Although 2 bytes of data are set in the registers 1, 2 and 3, the 1 byte read in step 94 is the first byte data of the 2 bytes. next,
Data is read byte by byte from the registers 1, 2, and 3 (step 96), and a parity is created from the 3-byte data (step 97). Two bytes of data are set in the registers 1, 2 and 3, but step 94
The 1 byte read in is the data of the second byte of the 2 bytes. The parity thus created is transferred to the selector 12 together with the data involved in creating the parity (step 98). Finally, the PG registers 1, 2, 3, 4 are reset (step 10
1).

In the selector 12, the transferred divided data and parity are transferred to the corresponding drive 1 concerned.
4 is transferred to the Drive IF 13 connected to No. 4. Dr
The ive IF 13 is connected to the MP 9 via the selector 12. The DriveIF 13 transfers the newly written divided data and parity transferred by the instruction of the MP9 to the drive 14 via the drive path 16 and writes the parity to the position of the drive internal address 26 of the drive 14. At this time, the C Adp 10 reports to the MP 9 that the divided data or new parity to be newly written is stored in the drive 14.

In this embodiment, the number of parity is one, but there is no problem if the number of parity is one or more.

(Write processing) Next, the drive 1 has already been written.
The case of updating in which the data written in 4 is rewritten with new data will be described.

The new data to be updated is stored in the cache memory 8 from the CPU 1 like the new write data at the time of writing the new data. The MP 9 refers to the address table 21 from the logical group number 22 and the data name 23 designated by the CPU 1 and recognizes the drive number 24, the in-drive address 26, and the division ratio 25 of the drive 14 in which data and parity are stored.

For example, referring to FIG.
It is assumed that a write request for updating is issued to ta # 1. The MP9 uses the address table 21 to drive Dri.
ve # 1, # 2, # 3, # 4 drive address 26
Is Addr11, Addr21, Addr31, Add
The data is stored in the position of r41, and the drive address 26 of Drive # 5 recognizes that the parity should be stored in the position of Addr51. Also, the division ratio is
e # 1, # 2, # 3, # 5 is 2, and Drive # 4 is 1
Is.

When the recognition of the update destination drive number 24, the in-drive address 26, and the division ratio by the MP9 is completed in this way, C A is performed in the same manner as the above-described new writing.
The new data is divided according to the division ratio at dp10 to create divided data, new parity is created from these divided data, and the new data and new parity are set to the drive 14 concerned.
It is stored in the address 26 in the drive.

(Reading process) Next, the drive 1 has already been read.
The case of reading the data written in 4 will be described. FIG. 8 shows a processing flowchart when the MP 9 performs the reading processing. The read processing method will be described with reference to FIG.

The MP9 refers to the address table 21 from the logical group number 22 and the data name 23 designated by the CPU 1 and recognizes the drive number 24 in which the data to be read is stored and the in-drive address 26 thereof (step 71). .

Next, the MP 9 checks the cache address 27 of the address table 21 and determines whether or not the data to be read exists in the cache memory 8 (step 72). If the address is registered in the cache address 27 and the data to be read is stored in the cache memory 8 (cache hit), M
P9 starts the control of reading the data from the cache memory 8, and if it is not in the cache memory 8 (cache miss), it starts the control of reading the data in the drive 14 concerned.

The processing at the time of a cache hit will be described. The MP9 uses the address table 21 to specify the logical group number 22 and the data name 23 specified by the CPU 1.
To the cache address 27 in the cache memory 8 in which the data is stored (step 73),
The data is read out to the cache memory 8. Specifically, the data is read from the cache memory 8 by the cache adapter circuit (C Adp) 7 under the instruction of MP9 (step 74).

The data read by the C Adp 7 is transferred to the channel interface circuit (CH IF) 5 under the control of the data control circuit (DCC) 6.
The CHIF 5 converts the protocol into a channel interface protocol in the CPU 1 and adjusts the speed to a speed corresponding to the channel interface. After the protocol conversion and speed adjustment in CH IF5, IF Adp4
To transfer data to the CPU 1 (step 7).
5).

On the other hand, if it is determined in step 72 that a cache miss has occurred, the MP 9 uses the address table 21 to determine the logical group number 22 and data name 23 designated by the CPU 1 from the drive number 24 and its drive, as in the case of a cache hit. The in-drive address 26 which is the physical address of the drive is recognized (step 76). MP9
For each recognized Drive
The IF 13 is instructed to issue a read request to the drive 14 (step 77). Each Drive
In IF13, according to the SCSI read processing procedure,
Issue a read command.

In the drive 14 to which the read command has been issued from the Drive IF 13, the seek / rotation wait access process is performed to the designated in-drive address 26. After the access processing in the drive 14 is completed, the drive 14 reads the divided data and transfers it to the Drive IF 13. Drive
The IF 13 transfers the transferred divided data to C Adp.
10 and the cache memory is 8 in C Adp10.
The data is stored in (step 78).

The method of writing the divided data from the C Adp 10 to the cache memory 8 may be the reverse of the method of dividing the data by writing new data to create the divided data. That is, the divided data is combined to create the data, which is written in the cache memory 8. The method is shown below.

First, the C Adp 10 reports to the MP 9 that data is stored in the cache memory 8, and the MP 9 which receives this report refers to the address table 21 to check the division ratio (step 79). In FIG. 3, Drive # 1, # 2, # 3, # of logical group LG # 1
In # 4 and # 5, the division ratio is Drive # 1, # 2, #
3, # 5 is 2, and Drive # 4 is 1. MP9
After recognizing the division ratio, instructs C Adp10 to combine the division data according to the division ratio to create data (step 80). C Adp that received this instruction
10 combines the divided data sent from the Drive IF 13 according to this division ratio. So C A
FIG. 9 is a flowchart showing the processing in which dp10 combines the divided data.

In FIG. 9, C Adp10 which has received a division data combination instruction from MP9 (step 102).
2 bytes from the data read from Drive # 1 to register 1 in CAdp10, 2 bytes from the data read from Drive # 2 to register 2, and
Two bytes from the data read from ve # 3 are set in the register 3, and one byte from the data read from the Drive # 4 are set in the register 4 (step 10).
3).

Next, in C Adp10, register 1,
Reads data from 2 and 3 by 2 bytes (Step 1
04), 1-byte data is read from the register 4 (step 105). The data of the registers 1, 2, 3, and 4 thus read are combined in the C Adp 10 in this order (step 106). Then, it is transferred to the cache memory 8 like the data before division in FIG. 2 (step 107). When the transfer of the combined data to the cache memory 8 is completed, the registers 1, 2, 3,
4 is reset (step 108).

Next, as in the flow of reading data from the cache memory 8 shown in FIG. 6, the value of the read counter is checked to see if all data has been read (step 109). If not completed, the process returns to step 103, and the next data is transferred to the register 1,
Set to 2, 3, 4. If completed, the process ends.

Next, an arbitrary drive 1 in the logical group
When a failure occurs in No. 4 and one of the divided data cannot be read, the following processing is performed.

First, the divided data and parity transferred from the Drive IF 13 to the C Adp 10 via the selector 12 are transferred to the parity generation circuit (PG) 11, and a failure occurs in the PG 11 as shown in FIG. The divided data stored in the drive 14 is restored. The division data can be restored by performing an exclusive OR of the existing division data and the parity, as in the method of creating the parity when writing new data.
For example, assume that Drive # 1 has failed. FIG. 10 shows a flowchart of the failure recovery processing at this time.

In FIG. 10, the PG 11 receives the recovery instruction from the MP 9 (step 110), and then the Drive #
The data read from Nos. 2, # 3, # 4, and # 5 are set in registers 2, 3, 4, and 5, respectively (step 11).
1). The data to be set is 2 in registers 2, 3, and 5.
Byte, register 4 becomes 1 byte.

Next, each byte is read from the registers 2, 3, 4, and 5 (step 112), an exclusive OR is obtained from the read data, and the data stored in Drive # 1 is restored (step). 113). Step 1
1 byte read from registers 2, 3 and 5 at 12 is 2
It is the data of the first byte of the bytes. Next, read byte by byte from registers 2, 3, and 5 (step 1
14), obtain an exclusive OR with the read data, and
The data stored in the live # 1 is recovered (step 115). The 1 byte read from the registers 2, 3 and 5 in step 114 is the second byte data of the 2 bytes.

Next, the data stored in the recovered Drive # 1 and the data (data of registers 2, 3, 4, 5) involved in the recovery of this data are combined (step 116) and combined. The data is transferred to the cache memory 8 (step 117). When the transfer to the cache memory 8 is completed, each register is reset (step 118).

Next, by the same algorithm as in FIGS. 6 and 9, it is checked whether the recovery of all data is completed (step 119). If not completed, the process returns to step 111 to continue the recovery of data. When the recovery of all the data in Drive # 1 is completed, the processing ends.

At this time, C Adp10 reports to MP9 that the data has been stored in the cache memory 8 and M
P9 is the CPU of the address table 21 based on this report.
1 registers the address in the cache memory 8 storing the data in the cache address 27 of the logical group number 22 and the data name 23 which issued the read request. After that, the data is transferred to the CPU 1 in the same procedure as the cache hit.

FIG. 11 is a diagram for explaining the transfer time and capacity in the disk array device of this embodiment. Further, FIG. 12 is a diagram for explaining a data transfer time when reading or writing divided data divided and stored with equal capacity in each drive 14 in a logical group as in the related art.

As can be seen from FIG. 12, when the divided data has the same capacity, the transfer time is determined by the transfer speed of the drive 14 (Drive # 4 in this case) having the slowest transfer speed.

On the other hand, as shown in FIG. 11A, when divided data is divided and stored in each drive 14 in the logical group with a capacity corresponding to the transfer speed ratio of each drive 14, the data to be read or written The transfer time is averaged and the processing performance is improved.

When the capacity of the divided data to be stored in each drive is changed according to the transfer speed ratio in this way, as shown in FIG. 11B, the data is stored between the drives forming the logical group. The amount of data that will be stored will differ. In the example described in the present embodiment, as shown in this figure, the transfer speed of Drive # 4 is Drive # 1, #
Since the transfer rate of 2, # 3, # 5 is 1/2, the division ratio is 1: 2, and the data capacity stored in Drive # 4 is 1 / of Drive # 1, # 2, # 3, # 5. It is 2. Therefore, Drive # 1, # 2, # 3, #
If the capacities of 4 and # 5 are the same, the drive # 4 stores only half the capacity of the other drives.

Therefore, as shown in FIG. 13, it is advisable to share the drive 14 of Drive # 4 with two logical groups. In the address table 21 shown in FIG. 3, logical groups LG # 1 and LG # 2 are set, but these logical groups share Drive # 4. That is, the logical group LG # 1 is Drive
The logical group LG # 2 is composed of # 1, # 2, # 3, # 4, and # 5, and the drive group Drive # 6, # 7, # 8, # 4, and # 9.
Consists of

In this way, if a drive having a low transfer rate and a low division ratio is shared by a plurality of logical groups, such a drive can be used efficiently, which is convenient.

[Embodiment 2] In this embodiment, as shown in FIG. 14, one drive having a high transfer speed is mixed. In this embodiment, it is assumed that the configuration of the disk array controller (hereinafter referred to as ADC) 2 that controls the RAID level 3 is as shown in FIG. In the following description, only the part different from the first embodiment will be described in detail.

(Initial setting method, address conversion method) In this embodiment, as shown in FIG. 1, five drives 14 form a logical group 15. In the present embodiment, as shown in FIG. 14 and FIG. 15, two types of error correction codes ECC (Error Correctio) are used, one byte each from Drive # 1 and # 2, and two bytes from Drive # 3.
n Codes) are created, and these two types of ECC are stored in another drive 14. Specifically, in FIG. 14 and FIG. 15, the data 1 of the Drive # 1 and the Drive #
An ECC 1 is created using the data 2 of # 2 and the data 3 of Drive # 3, and the data 1 and the Drive 1 of Drive # 1 are created.
An ECC 1'is created using the data 2 of ve # 2 and the data 4 of Drive # 3. ECC1 is Drive # 4
, And ECC1 ′ is stored in Drive # 5.

FIG. 16 shows the address table 2 of this embodiment.
It is 1. The address table 21 of FIG. 16 is the same as the first embodiment in FIG. 3 except that the division ratio of each drive 14 is different from the address table 21 of the first embodiment. The initial setting and the address conversion method in this embodiment are the same as those in the first embodiment.

(New Writing Processing) When writing new data, as in the first embodiment, the new data is written in the cache memory 8 and the data name is registered in the empty area of the data name 23 of the address table 21. When confirming the writing of the new data to the cache memory 8, the MP 9 instructs the Drive IF 13 to issue the write request of the new writing data and the new parity to the drive 14.

The Drive IF 13 issues a write command to the drive 14 via the drive path 16 in accordance with the SCSI write processing procedure. D
The drive 14 to which the write command has been issued from the drive IF 13 performs access processing for seek and rotation waiting for the designated in-drive address 26.

After the access processing in the drive 14 is completed, the cache adapter circuit (C Adp) 10
Reads new write data from the cache memory 8. At this time, the MP 9 refers to the address table 21 to check the division ratio.

In FIG. 16, Dr of the logical group LG # 1
In ive # 1, # 2, # 3, # 4, # 5, Dri
The transfer rate of ve # 1, # 2, # 4, # 5 is 3 MB / s, and the transfer rate of Drive # 3 is 6 MB / s.
Therefore, the transfer speed ratio is 1: 2, and the division ratio is Drive
e # 1, # 2, # 4, # 5 is 1 and Drive # 3 is 2
Is. After recognizing the split ratio of each drive, MP9
The C Adp 10 is instructed to read the data from the cache memory 8 according to this division ratio. Upon receiving this instruction, the C Adp 10 reads the data from the cache memory 8 according to this division ratio. FIG. 17 shows a flowchart of a read process from the cache memory 8 by the C Adp 10.

In FIG. 17, C Adp10 is MP
When a read instruction is received from 9 (step 130), C
The read number counter in Adp10 is reset and 1 is added to the counter value (step 131). Next, this counter value is divided by 3, and it is determined whether the remainder is 0 (step 132). If the remainder is not 0, 1 byte is read from the cache memory 8 (step 13).
4). If the remainder is 0, 2 bytes are read from the cache memory 8 (step 133).

The data read in this way is P
It is transferred to G11 (step 135), and parity is created in PG11. As a result, the data transfer to PG11 is repeated in the order of 1 byte, 1 byte, 2 bytes. After transferring the data to the PG 11, the value of the read number counter is checked to determine whether or not the data transfer of the predetermined amount of data is completed (step 13).
6). The determination by the read number counter is the same as that in the first embodiment.

Thus, from the cache memory 8 to C
The new write data read to Adp10 is transferred to the parity generation circuit (PG) 11, and ECC is created in PG11.

The ECC is created by using the Dri in the divided data assigned to each drive 14 as shown in FIG.
Two types of ECC are created from 1 byte corresponding to the divided data stored in ve # 1 and # 2 and 2 bytes corresponding to the divided data stored in Drive # 3. PG1
18 shows a flowchart of a method of creating two types of ECC in No. 1 in FIG.

In FIG. 18, the data (repeatedly transferred in the order of 1 byte, 1 byte, 2 bytes) transferred to the PG 11 is set in the PG register as follows. That is, the first 1 byte is set in the PG register 1, the next 1 byte is set in the PG register 2, and the next 2 bytes are set in the PG register 3 (step 121).

Next, 1 set in the PG register 1
Byte data and 1 set in PG register 2
The byte data and the 2-byte data set in the PG register 3 are read from the respective registers (step 122). Then, in PG11, 1-byte data in PG register 1 and 1 in PG register 2
An ECC1 is created from the byte data and the first byte of the 2-byte data in the PG register 3 (step 123). Further, in PG11, ECC1 'is created from the 1-byte data of PG internal register 1, the 1-byte data of PG internal register 2, and the remaining 1-byte of the 2-byte data of PG internal register 3. (Step 124).

In this way, the two types of ECC1 and ECC are
After 1'is created, 1-byte data in the PG register 1, 1-byte data in the PG register 2, 2-byte data in the PG register 3, ECC1, ECC
1'and transferred to the selector 12 (step 125),
Reset registers 1, 2, and 3 in PG (step 1
26). When creating an ECC as in the present embodiment, the ECC may be parity.

Thus, data and EC from PG11
In the selector 12 to which C1 and ECC1 'have been transferred,
Drive IF 13 connected to the drive 14 in which these divided data and ECC are to be respectively stored
Transfer to The Drive IF 13 is connected to the MP 9 via the selector 12. Drive IF13
Then, the new write division data and the ECC transferred by the instruction of MP9 are transferred to the drive 14 via the drive path 16 and written to the in-drive address 26 of the drive 14. At this time, C Adp10 is
The fact that the divided data or the new ECC to be newly written is stored in the drive 14 is reported to the MP9.

The above-described new write division data and ECC write to each drive is 1 byte for Drive # 1 (1 byte of PG register 1) and 1 byte for Drive # 2 (1 byte of PG register 2). ), Drive
2 bytes in # 3 (2 bytes in PG register 3), D
1 byte for live # 4 (1 byte for ECC1), D
1 byte for live # 5 (1 byte for ECC1 '),
And so on. That is, 2 bytes are written only in Drive # 3, which has a transfer rate twice that of other drives, and 1 byte is written in the other drives.

(Write processing) Next, the drive 1 has already been written.
The case of updating in which the data written in 4 is rewritten with new data will be described.

The new data to be updated is stored in the cache memory 8 from the CPU 1 as in the case of writing the new data. The MP 9 refers to the address table 21 from the logical group number 22 and the data name 23 designated by the CPU 1, and drives 1 in which data and ECC are stored.
The drive number 24, the in-drive address 26, and the division ratio 25 of 4 are recognized.

For example, in FIG. 16, CPU1 to D
It is assumed that a write request for updating is issued to ata # 1. The MP9 uses Dr.
The in-drive address 26 of the ive # 1, # 2, # 3 is A
The divided data is stored in the positions of ddr11, Addr21, and Addr31, and the in-drive address 26 of Drive # 4 and # 5 is EC in the positions of Addr41 and Addr51.
Recognize that C should be stored. In this way, the drive number 24 and the in-drive address 26 of the update destination by MP9
When the recognition of is completed, the new data is divided by C Adp10 according to the division ratio, the divided data is created, and two kinds of new ECCs are created from these divided data, as in the case of the new writing described above. The new data and the new ECC are stored in the in-drive address 26 of the drive 14.

(Reading process) Next, the drive 1 has already been read.
The case of reading the data written in 4 will be described. The reading process is also similar to the procedure described in FIG. 8 of the first embodiment.

At the time of this read processing, the method of writing the divided data from the C Adp 10 to the cache memory 8 is as follows.
The reverse of the method of dividing data by writing new data and creating divided data may be performed. That is, the divided data is combined to create the data, which is written in the cache memory 8. The method is shown below.

First, the C Adp 10 reports to the MP 9 that data is stored in the cache memory 8, and the MP 9 receiving this report refers to the address table 21 to check the division ratio. In FIG. 16, the logical group LG
In Drive # 1, # 2, # 3, # 4, and # 5 of # 1, the drive ratio of Drive # 1, # 2, # 4, and # 5 is 1.
Thus, Drive # 3 is 2. After recognizing the division ratio, the MP 9 instructs the C Adp 10 to combine the division data according to the division ratio to create the data. Upon receiving this instruction, the C Adp 10 combines the divided data sent from the Drive IF 13 according to this division ratio. FIG. 19 is a flowchart showing a process in which the C Adp 10 combines the divided data.

In FIG. 19, C Adp10 (step 14) which has received a division data combination instruction from MP9.
0) indicates that one byte from the data read from Drive # 1 is stored in register 1 in C Adp10, and Drive #
1 byte from the data read from 2 to register 2,
Two bytes are set in the register 3 from the data read from the Drive # 3 (step 141).

Next, in C Adp10, register 1,
Data is read byte by byte from 2 (step 14
2), 2 bytes of data are read from the register 3 (step 143). The data of the registers 1, 2, and 3 thus read are combined in this order in C Adp 10 (step 144). Then, it is transferred to the cache memory 8 like the data before the division (step 145). When the transfer of the combined data to the cache memory 8 is completed, the registers 1, 2, 3 are reset (step 146).

Next, as in the first embodiment, the value of the read counter is checked to see if all data has been read (step 147). If not completed, the process returns to step 141 to transfer the next data to the registers 1, 2,
Set to 3. If completed, the process ends.

Next, an arbitrary drive 1 in the logical group
When a failure occurs in 4 and one of the divided data cannot be read, the following processing is performed.

First, the divided data and ECC transferred from the Drive IF 13 to the C Adp 10 via the selector 12 are transferred to the parity generation circuit (PG) 11.
In PG11, the divided data stored in the failed drive 14 is restored. FIG. 20 shows a flowchart of the failure recovery process at this time. Note that, here, it is assumed that the drive # 1 has a failure.

In FIG. 20, the PG 11 receives the recovery instruction from the MP 9 (step 150), and then registers the data read from the drives # 2, # 3, # 4, and # 5 which are not in trouble with the registers 2, 3 respectively. Set to 4, 5 (step 151). The data to be set is 1 byte in the registers 2, 4 and 5 and 2 bytes in the register 3.

Next, each byte is read from the registers 2, 3, 4, and 5 (step 152). The exclusive OR is obtained using the data thus read, and the Driv
The data stored in e # 1 is recovered and set in register 1 (step 153). Further, the recovered data and the data involved in the recovery of the data are combined (step 153), and the combined data is transferred to the cache memory 8 (step 155). When the transfer to the cache memory 8 is completed, each register is reset (step 156).

Next, by the same algorithm as in the first embodiment, the value of the recovery counter is checked to see if the recovery of all data is completed (step 157). If not completed, the process returns to step 151 to recover the data. Continue recovery. Dri
When the recovery of all the data in ve # 1 is completed, the processing is ended.

In the present embodiment, Drive # 1, # is driven.
Two types of ECC are created for the data in 2 and # 3 as shown in FIGS. 14 and 15. Therefore, the data recovery in steps 152 and 153 may be performed using 1 byte of register 2, the first byte of 2 bytes of register 3, and 1 byte of register 4 (ECC1). 1 byte of 2, register 3
2nd byte of 2 bytes and 1 of register 5
You may perform using a byte (ECC1 '). Also,
Both methods may be used.

Furthermore, in the present embodiment, since two types of ECC are held, even if a failure occurs in Drive # 3, divided data 1, 2 and ECC1, ECC1 'are used to generate divided data 3, 4 (Drive #). (Data in 3) can be recovered.

When data is recovered as described above, C A
The dp 10 reports to the MP 9 that the data has been stored in the cache memory 8. Based on this report, the MP 9 reports to the logical group number 22 and the cache address 27 of the data name 23 that the CPU 1 of the address table 21 issued the read request. The address in the cache memory 8 storing the data is registered. After that, the data is transferred to the CPU 1 in the same procedure as the cache hit.

FIG. 21 is a diagram for explaining the data transfer time when reading or writing the divided data divided into equal capacities into each drive 14 in the logical group as in the conventional case. As can be seen from this figure, when the divided data has the same capacity, the drive 14 has the slowest transfer time (here, Drive # 1, # 2, # 3, # 5).
Determined by the transfer rate of.

FIG. 14 is a diagram for explaining the transfer time and capacity in the disk array device of this embodiment. As can be seen from this figure, when the data is divided according to the transfer speed ratio of each drive 14 in the logical group and the divided data is allocated as in the present embodiment, the data transfer time of each drive 14 in the logical group Are averaged and the processing performance is improved.

When the capacity of the divided data to be stored in each drive is changed according to the transfer speed ratio as described above, the capacity of the data to be stored between the drives constituting the logical group as shown in FIG. Will be different. In the example described in the present embodiment, as shown in FIG.
The transfer speed of ve # 3 is Drive # 1, # 2, # 4, #
Since the transfer rate is 5 times the transfer rate of 5, the division ratio is 2: 1 and the data capacity stored in Drive # 3 is Drive.
e # 1, # 2, # 4, and # 5. Therefore, if Drive # 1, # 2, # 3, # 4, and # 5 have the same capacity, Drive # 3 stores twice as much data as other drives, so Drive # 3 is full. Even if the data is stored in, Drive # 1, #
In 2, # 4 and # 5, there is still space available.

Therefore, since this free area is used, as shown in FIG. 23, when Drive # 3 becomes full,
After that, it is preferable to perform processing according to RAID level 3 using Drive # 1, # 2, # 4, and # 5. In the address table 21 shown in FIG. 16, Data # 4
After that, the drive address 26 of Drive # 3 is not registered. As described above, when the intra-drive address 26 is not registered in the address table 21, the MP 9 recognizes that the Drive # 1, # 2, # 4, and # 5 performs the RAID3 process.

In the above example, two types of ECC are stored separately for Drive # 4 and # 5. As a modified example, as shown in FIG. 24, if the transfer rate of Drive # 5 is 6 MB / s, which is the same as that of Drive # 3,
Two types of ECC can be stored together in Drive # 5.

[Third Embodiment] In the first embodiment, the method of sharing the drive 14 among a plurality of logical groups has been described. This is because when the transfer speeds of the drives 14 in the logical group are different and the data is divided according to the transfer speed ratio and the divided data is assigned, the data stored between the drives 14 forming the logical group Since the capacities are different, the drive 14 is shared by a plurality of logical groups.

In the third embodiment, a method of sharing the drive 14 among a plurality of logical groups even when the capacities of the drives 14 constituting the logical group are different will be described.

FIG. 25 shows two logical groups LG # 1,
It is shown that LG # 2 shares Drive # 4. The logical group LG # 1 includes Drive # 1, # 2, and
It is composed of five drives # 3, # 4, and # 5. Drive # 1, # 2, # 3, # 5 has a capacity of 2 GB
The capacity of Drive # 4 is doubled to 4 GB.

On the other hand, the logical group LG # 2 is
5 drives 14 # 6, # 7, # 8, # 4, # 9
It is composed of Drive # 6, # 7, # 8, # 9
Has a capacity of 2 GB, and Drive # 4 has a capacity of 4 GB and 2
Is doubled.

Therefore, in the logical group LG # 1, Dri
1/2 of the capacity of ve # 4 is used, and the remaining 1/2 capacity is used by the logical group LG # 2. Conventionally, the drives 14 forming the disk array have the same performance and the same capacity. However, if the drives 14 can be shared between the logical groups in this way, the disk array can be configured with the drives 14 having different capacities.

[Fourth Embodiment] In the first, second, and third embodiments,
The disk array using the drive (magnetic disk device) has been described. In the fourth embodiment, the drive 14
Instead of, a non-volatile semiconductor memory such as a flash memory (FMem) will be described as an example.

FIG. 26 shows the Drive IF in FIG.
A disk array device in which 13 is replaced with a Flash IF 30 and the drive 14 is replaced with a flash memory (FMem) 31 is shown.

Even if the drive 14 is changed to FMem31,
The initial setting method and the address conversion method are the same as those in the first and second embodiments. That is, the FMem 31 is used in the same manner as the drive 14. Also, the writing process of new data,
The update write processing for rewriting the already written data with new data is also the same as in the first and second embodiments. In addition, read processing and failure processing
This is the same as in Examples 1 and 2.

Address table 21 in this embodiment
In the address table 21 shown in FIG. 3 of the first embodiment and FIG. 9 of the second embodiment, the drive number 24 is FMe.
It becomes m number, and the address 26 in the drive is FMem31.
The other configuration, function, and usage are the same.

However, unlike the drive 14, the FMem31 does not require seek and rotation waiting and can be directly written. However, when writing in the FMem31, once the write address in the FMem31 is erased, It will be written.

As described above, in this embodiment, the first embodiment,
In 2 and 3, the case where the drive 14 is replaced by the FMem 31 is shown. Even if the FMem31 is replaced in this way, it is clear that the effects of the first, second and third embodiments can be exhibited.

In the first, second, third, and fourth embodiments, the present invention is applied to RAID3. That is, CPU
1 data from 1 drive 14 or FMem3
In this example, the division ratio is made variable according to the specification of 1. Not limited to this, the present invention can be applied to the case where data is not divided like RAID level 4 and level 5. That is,
Drive 1 having a low transfer rate in the first, second, and fourth embodiments
4 or FMem31 stores a small amount of data according to the transfer rate, and drives 14 or F with a high transfer rate.
Mem31 may store large data according to the transfer rate.

[0154]

As described above, according to the present invention,
Since the size of the data to be distributed is changed according to the processing speed of each storage device in the logical group, the data transfer time when performing parallel transfer in each storage device of the logical group is different between the storage devices. It becomes possible to average.
That is, when data is allocated to the storage devices in the logical group in equal capacity as in the conventional case, the transfer time is determined by the transfer speed of the storage device with the slowest transfer speed. Since the data transfer time when accessing in parallel is averaged, the processing performance is improved.

Further, the conventional disk array device is constructed by using the drives having the same performance and the same capacity.
However, by using the present invention, it is possible to improve the performance and configure the disk array device with drives having different capacities.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a disk array device according to an embodiment.

FIG. 2 is an explanatory diagram of data division in the first embodiment.

FIG. 3 is a block diagram of an address table in the first embodiment.

FIG. 4 is an explanatory diagram of an initial setting method in the first embodiment.

FIG. 5 is an explanatory diagram of a new write processing method according to the first embodiment.

FIG. 6 is an explanatory diagram of a read processing method from a cache memory according to the first embodiment.

FIG. 7 is an explanatory diagram of a parity creating method according to the first embodiment.

FIG. 8 is an explanatory diagram of a read processing method according to the first embodiment.

FIG. 9 is an explanatory diagram of a data combining method according to the first embodiment.

FIG. 10 is an explanatory diagram of a data recovery processing method according to the first embodiment.

FIG. 11 is an explanatory diagram of data transfer time and capacity in the first embodiment.

FIG. 12 is an explanatory diagram of data transfer time in the conventional method.

FIG. 13 is an explanatory diagram of drive sharing according to the first embodiment.

FIG. 14 is an explanatory diagram of a data transfer time in the second embodiment.

FIG. 15 is an explanatory diagram of ECC creation according to the second embodiment.

FIG. 16 is an address table configuration diagram according to the second embodiment.

FIG. 17 is an explanatory diagram of a read processing method from the cache memory according to the second embodiment.

FIG. 18 is an explanatory diagram of an ECC creating method according to the second embodiment.

FIG. 19 is an explanatory diagram of a data combining method according to the second embodiment.

FIG. 20 is an explanatory diagram of a data recovery processing method according to the second embodiment.

FIG. 21 is a conventional explanatory diagram for the second embodiment.

FIG. 22 is an explanatory diagram of the capacity in the second embodiment.

FIG. 23 is a mixed explanatory view according to the second embodiment.

FIG. 24 is an explanatory view of a modification of the second embodiment.

FIG. 25 is an explanatory diagram of the third embodiment.

FIG. 26 is an explanatory diagram of the fourth embodiment.

[Explanation of symbols]

1: CPU, 2: Array disk controller (AD
C), 3: external path, 4: interface adapter,
5: Channel interface (CH IF) circuit,
6: data control circuit (DCC), 7: channel side cache adapter (CAdp), 8: cache memory,
9: Microprocessor (MP), 10: Drive side cache adapter (C Adp), 11: Parity generation circuit (PG), 12: Selector, 13: Drive interface circuit (Drive IF), 14: Drive, 15: Logical group , 16: drive path, 21:
Address table, 22: logical group number, 23: data name, 24: drive number, 25: division ratio, 26: in-drive address, 27: cache address.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location G11B 20/18 H 8940-5D 572 B 8940-5D F 8940-5D

Claims (12)

[Claims] 1. A disk array device comprising a plurality of storage devices forming a logical group and a control device for controlling the storage devices, wherein the plurality of storage devices include storage devices of different processing speeds. The disk array device is characterized in that the amount of data to be stored is assigned to each storage device according to the processing speed of the storage device. 2. Data is created from m data storage devices (m is an integer of 2 or more) for storing data provided by a host device by striping and data stored in the m data storage devices. In a disk array device having a control unit for controlling these storage devices while forming a logical group from n (n is an integer of 1 or more) error correction code storage devices for storing error correction codes, In the m data storage devices and the n error correction code storage devices, the relative ratio of the processing speed of each storage device is in order.
Storage devices having different processing speeds such as k1: k2: ...: ki: ...: km + n are mixed, and when the striping unit is represented by u, the minimum access unit of each storage device is , A product of the relative ratio ki (i = 1 to m + n) of the processing speed of the storage device and the striping unit u, respectively, ki.multidot.u.multidot.u. 3. The control device comprises a logical group number for specifying a logical group, a data name given by a host device,
A field of a storage device number that identifies a storage device that configures a logical group, a division ratio that represents a relative ratio of processing speeds of the storage devices, and a storage device address field of each storage device in which the data of the data name is stored is set. 3. The disk array device according to claim 1, wherein data is managed by an address table included therein. 4. The error correction code is created by using a part or all of the data stored in each of the m data storage devices, and is stored in the n error correction code storage devices. Disk array device. 5. A plurality of types of error correction codes are created by using a part or all of the data respectively stored in the m data storage devices, and stored in the n error correction code storage devices. The disk array device according to 1. 6. The disk array device according to claim 1, wherein when data is stored in the entire storage area of one of the storage devices, a disk array is formed by the free space of the remaining storage devices. . 7. The disk array device according to claim 1, wherein a storage device is shared between the logical groups. 8. The disk array device according to claim 1, wherein the storage device is a disk drive. 9. The disk array device according to claim 1, wherein the storage device is a non-volatile semiconductor memory device. 10. m units (m is an integer of 2 or more) for striping and storing data provided from a host device.
A data storage device and n (n is an integer of 1 or more) error correction code storage device for storing error correction codes created from the data stored in the m data storage devices. In addition, in the disk array device including a control device for controlling these storage devices, the m data storage devices and the n error correction code storage devices have a relative ratio of storage capacities of the storage devices in order.
Storage devices having different storage capacities such as k1: k2: ...: ki: ...: km + n are mixed, and when the striping unit is represented by u, the minimum access unit of each storage device is A disk array device, wherein the product of the relative ratio ki (i = 1 to m + n) of the storage capacity of the storage device and the striping unit u is ki.multidot.u. 11. m units (m is an integer of 2 or more) for striping and storing data given from a host device.
A data storage device and n (n is an integer of 1 or more) error correction code storage device for storing error correction codes created from the data stored in the m data storage devices. A method of writing data in a disk array device having a control device for controlling these storage devices, wherein the processing speeds of the m data storage devices and the n error correction code storage devices are relative to each other. Ratio in order k
1: k2: ...: ki: ...: km + n, and the unit of striping is represented by u, then k1.u, k2.u ,. Reading each of them, creating an error correction code from the read data, reading the data of k1.u size, the data of k2.u size, ..., And the data of km.u size Is written in parallel to the corresponding data storage device, and the created error correction code is written in parallel to the error correction code storage device, the data writing method of the disk array device. 12. A data reading method of a disk array device for reading the data written by the data writing method according to claim 11, wherein k1 from each of the m data storage devices and the n error correction code storage devices are read.・ U, k2 ・ u, ...,
and a step of reading the data in units of km · u in parallel, and the read data of the size of k1 · u, the data of the size of k2 · u, ..., And the data of the size of km · u.
A method of reading data from a disk array device, comprising the steps of combining and transferring the combined data to a higher-level device.