JPH0868833A - Analog/digital hybrid integrated circuit and test method therefor - Google Patents

Abstract

PURPOSE: To shorten the test time while reducing the test cost and to promote the design of testability by employing a test circuit for analog/digital hybrid integrated circuit and a test method using only an LSI digital tester. CONSTITUTION: In addition to verify the reversibility of a D/A converter 4 and an A/D converter 3 by connecting them in series, an attenuator 9 is inserted into the post-stage of D/A conversion and a multiplication unit 12 having multiplication factor equal to the reciprocal of the attenuation factor of the attenuator 9 is inserted into the post-stage of the A/D converter 3. Consequently, the linearity can be verified and an analog/digital hybrid integrated circuit can be tested using only a common digital tester where a D/A converter having verified linearity can be used as a waveform generator 7 and an A/D converter 3 having verified linearity can be used as a measuring unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit in which an analog circuit and a digital circuit are mixedly mounted and a method for testing the integrated circuit.

[0002]

2. Description of the Related Art In recent years, an analog / digital mixed circuit technology, in which an analog circuit and a digital circuit are mixedly mounted on a single chip, has been regarded as promising as a means for increasing the functionality of an integrated circuit.

In order to realize this, it is necessary to perform a test using an LSI tester to determine whether the actually manufactured semiconductor chip can achieve desired characteristics. This was done by testing a conventional integrated circuit consisting of only digital circuits and selecting a chip with the desired characteristics.However, since analog circuits were mixed in the chip, in addition to the digital circuit test, operation as an analog circuit was also performed. Also need to be tested.

However, the conventional LSI tester for a digital circuit attaches importance to only the value of the logic signal and the timing at which it appears, and cannot consider the output waveform. LSI tester is required. This includes an LSI tester that verifies only analog circuits and an analog / digital LSI that can handle both analog and digital signals.
There are two types of testers.

In the former case, the digital test and the analog test must be performed separately and separately. This is troublesome, and the circuit must be configured so that the digital circuit and the analog circuit can be separated. This increases the chip area and the number of terminals. The configuration of an analog / digital hybrid circuit that minimizes this disadvantage and increases observability and controllability is disclosed in, for example, Japanese Patent Laid-Open No. 2-1978.
It is disclosed in Japanese Patent Publication No. 0 and the like. However, this configuration requires an analog tester to the end, and the test is twice as troublesome.

In the latter case, the output waveform must be taken into consideration in addition to the function of the digital tester.
I-testers are expensive and the number of units in operation must be extremely low. Therefore, the test time and test cost of the analog / digital circuit mixed chip are significantly increased as compared with the chip without the analog circuit, resulting in a dilemma of added value and high cost. It is very useful if the analog / digital circuit mixed chip can be tested only by the digital tester.

From such a point of view, conventionally, for example, Japanese Patent Laid-Open No.
An analog / digital hybrid circuit disclosed in Japanese Unexamined Patent Publication No. 1394478 has been proposed.

FIG. 6 shows a circuit configuration essentially equivalent to this.
Referring to FIG. 2, this circuit includes a digital circuit 62 and a D / A converter 64 connected to the output of the digital circuit 62.
It is assumed that the circuit is composed of and, and the function of outputting an analog signal is added to the function of a normal digital circuit.

In order to carry out the test of this circuit by a digital tester, this circuit further has a structure in which an analog output is branched and an A / D converter 63 is connected to one side of the analog output to restore the digital signal again. If the D / A converter 62 as a component and the A / D as an additional function dedicated to the test
If both of the converters 63 are normal, the digital signal x immediately before D / A conversion and the digital signal z immediately after A / D conversion should be exactly the same, and D / A can be detected by detecting this. The idea is to test the converter.

[0010]

However, the relationship between the digital signal x and the D / A-converted signal y is represented by y.
= F (x) and the relationship between the A / D converted signal z and the signal y is written as z = g (y), then z = g (f (x)), which is shown in FIG. The test method according to the method only verifies whether g is an inverse function of f.
The validity as the conversion and the D / A conversion, that is, the linearity is not guaranteed.

In the extreme case, the data bus of signal x and signal z
If the data bus of 1 is short-circuited, the test may pass as a good product regardless of the signal y. Further, since only the test method of the D / A converter 64 on the output side is provided, it is difficult to apply this test method to a general analog / digital mixed integrated circuit.

Therefore, an object of the present invention is to solve the above-mentioned difficulties of the prior art, to verify the linearity of each of the installed A / D converter and D / A converter, and to perform the digital circuit. Analog / digital mixed integration that can be applied to the verification of general analog circuits embedded together with and that can perform such tests only with digital LSI testers without using expensive analog testers It is to provide a circuit and a test method thereof.

[0013]

SUMMARY OF THE INVENTION An integrated analog / digital integrated circuit comprises a digital circuit, digital conversion means for converting an analog input signal to an input signal to the digital circuit, and an output signal from the digital circuit to an analog signal. An analog / digital hybrid integrated circuit including analog conversion means for converting, wherein two analog inputs are inserted between a first analog input terminal receiving the analog input signal and an analog input terminal of the digital conversion means. A first analog multiplexer whose one end is connected to the first analog input terminal and whose output end is connected to the analog input terminal of the digital conversion means; An attenuator attenuated by the analog output signal of the analog conversion means and the A second one of the output signals of the attenuator is selected and the selected analog signal is supplied to the other one of the two analog input terminals of the first analog multiplexer which is not connected to the analog input signal. Of the analog multiplexer, the digital multiplying means for multiplying the digital signal of the digital converting means by a multiplication rate equal to the reciprocal of the attenuation rate of the attenuator, the digital signal of the digital converting means and the output signal of the digital multiplying means. A digital multiplexer for selecting one of them, a first input means for inputting an input signal to a selection pin for determining the selection of the first analog multiplexer, and an input signal for a selection pin for determining the selection of the digital multiplexer. Input and determines the selection of said second analog multiplexer Second input means for inputting an input signal to the select pin that is configured to have a comparison means for comparing the output signal of the digital input signal that is input to said analog converting means and said digital multiplexer.

The test method for testing the analog / digital mixed integrated circuit of the present invention selects the output signal of the second analog multiplexer by controlling the input signal to the selection pin of the first analog multiplexer. Then, the analog output signal of the analog conversion means is selected by controlling the input signal to the selection pin of the second analog multiplexer, and the input signal to the selection pin of the digital multiplexer is controlled to control the digital conversion means. Reversibility confirmation method for confirming reversibility of the analog conversion means and the digital conversion means by selecting an output signal indicating the coincidence of the comparison means, and a selection pin of the first analog multiplexer. The input signal to the second analog circuit remains unchanged. Selecting the output signal of the attenuator by controlling the input signal to the select pin of the multiplexer and selecting the output signal of the digital multiplying means by controlling the input signal to the select pin of the digital multiplexer. A simultaneous linearity confirmation method for simultaneously confirming the linearity of the analog conversion means and the linearity of the digital conversion means by obtaining an output signal indicating the coincidence of the means.

Furthermore, another analog / digital mixed integrated circuit of the present invention is an analog / digital mixed integrated circuit including a digital circuit and a digital converting means for converting an analog input signal into an input signal to the digital circuit. Thus, one of the two analog input terminals inserted between the first analog input terminal for receiving the analog input signal and the analog input terminal of the digital converting means is the first analog input terminal. A first analog multiplexer having an output end connected to an analog input end of the digital conversion means, an analog conversion means, a digital input signal input means for inputting a digital input signal of the analog conversion means, and the analog An attenuator that attenuates the analog output signal of the conversion means at a constant attenuation rate; One of the analog output signal of the analog conversion means and the output signal of the attenuator is selected, and the selected analog signal is converted to the analog input signal of the two analog input terminals of the first analog multiplexer. A second analog multiplexer for supplying the other input terminal which is not connected, a digital multiplier for multiplying the digital signal of the digital converter by a multiplication factor equal to a reciprocal of an attenuation rate of the attenuator, and a digital converter for the digital converter. A digital multiplexer for selecting one of a signal and an output signal of the digital multiplying means; a first input means for inputting an input signal to a selection pin for determining selection of the first analog multiplexer; and the digital multiplexer Input signal to the selection pin that determines the selection of Second input means for inputting an input signal to a selection pin that determines the selection of the second analog multiplexer, and comparison for comparing a digital input signal input to the analog conversion means with an output signal of the digital multiplexer. And a means.

Further, another test method for testing an integrated analog / digital integrated circuit according to the present invention is characterized in that an output signal of the second analog multiplexer is controlled by controlling an input signal to a selection pin of the first analog multiplexer. And selecting an analog signal of the analog conversion means by controlling an input signal to a selection pin of the second analog multiplexer, and controlling an input signal to a selection pin of the digital multiplexer by controlling the input signal to the digital conversion means. A reversibility confirmation method for confirming the reversibility of the analog conversion means and the digital conversion means by selecting the digital signal of the above and obtaining an output signal indicating the coincidence of the comparison means; Of the second analog signal without changing the input signal of The output signal of the attenuator is selected by controlling an input signal to a selection pin of a multiplexer, and the output signal of the digital multiplication means is selected by controlling an input signal to a selection pin of the digital multiplexer. And a linearity confirmation method for confirming the linearity of the digital conversion means by obtaining an output signal indicating the coincidence of the two.

Still another analog / digital mixed integrated circuit of the present invention is an analog / digital mixed integrated circuit including a digital circuit and an analog converting means for converting an output signal of the digital circuit into an analog signal. An attenuator for attenuating the analog output signal of the analog converting means at a constant attenuation rate, an analog multiplexer for selecting one of the analog signal of the analog converting means and the output signal of the attenuator, and the analog multiplexer. A digital converting means for converting the output signal of the digital signal into a digital signal, a digital multiplying means for multiplying the digital signal of the digital converting means by a multiplication ratio equal to the reciprocal of the attenuation factor of the attenuator, a digital signal of the digital converting means, Of the output signal of the digital multiplication means A digital multiplexer for selecting one of them, input means for inputting an input signal to a selection pin for determining selection of the analog multiplexer and inputting an input signal to a selection pin for determining selection of the digital multiplexer, And a comparing means for comparing the output signal of the digital circuit with the output signal of the digital multiplexer.

Still further, a test method for testing still another analog / digital mixed integrated circuit according to the present invention comprises:
An analog signal of the analog conversion means is selected by controlling an input signal to a selection pin of the analog multiplexer, and a digital signal of the digital conversion means is selected by controlling an input signal to a selection pin of the digital multiplexer. A reversibility confirmation method for confirming the reversibility of the analog conversion means and the digital conversion means by obtaining an output signal indicating a match of the comparison means, and controlling the input signal to a selection pin of the analog multiplexer to control the reversibility. Selecting the output signal of the attenuator and controlling the input signal to the selection pin of the digital multiplexer, selecting the output signal of the digital multiplication means, and obtaining the output signal indicating the coincidence of the comparison means, thereby obtaining the analog conversion means Check linearity of linearity And a method.

Still another analog / digital mixed integrated circuit of the present invention is a digital circuit, a second digital converting means different from the digital converting means for giving a signal to the digital circuit, and the digital circuit. An analog / digital hybrid integrated circuit comprising: an analog circuit having an analog processing section, the second analog converting means being different from the analog converting means for receiving a signal from the circuit, and at least one fixed circuit An attenuator that attenuates at an attenuation rate of at least one, and at least one multiplication means having a multiplication rate equal to the reciprocal of the attenuation rate of the attenuator;
Comparing means for comparing the two sets of digital inputs, at least one 2-input output analog multiplexer, at least one 2-input 1-output digital multiplexer, the number of external input signals to the analog circuit, and When the sum of the number of the second analog converting means is 0, the number of the third analog converting means is one, and when the sum of the number of the second analog converting means is greater than 0, the number of the third analog converting means is equal to the number of input signals from the outside to the analog circuit, and the analog circuit. From the analog circuit to the outside and the number of the second digital converting means from the analog circuit is 0, the number is one, and when the sum is greater than 0, the number of output signals from the analog circuit to the outside is one. A third digital conversion means, and in a predetermined operation mode,
At least one of the second digital conversion means and the third digital conversion means can be determined for any one of the second analog conversion means and the third analog conversion means. At least one of the second analog conversion means and the third analog conversion means can be determined for any one of the second digital conversion means and the third digital conversion means, and further determined. 2 inputs to one of the determined second digital conversion means and the third digital conversion means, one of the second analog conversion means and the third analog conversion means determined. When one of the two inputs of the one-output analog multiplexer is selected, it is directly connected through one of the two-input one-output analog multiplexer or the other is selected. If the of the is connected to a digital multiplier means and said analog converting means output from one connected via the attenuator and the digital conversion means 1
The input signal to each of them and the output from the digital multiplying means can be connected to one of the comparing means, or in another predetermined operation mode, the output of each of the third analog converting means to the analog circuit. A configuration is possible in which instead of an input signal from the outside, it is input to the analog circuit, and an output signal from the analog circuit to the outside can be branched and input to each input terminal of the third digital conversion means. The configuration has a selection circuit network composed of a plurality of multiplexers to be taken, and input means for input signals to a sufficient number of selection pins for determining all selection states of the selection circuit network.

Further, according to still another test method for testing an analog / digital mixed integrated circuit of the present invention, each analog conversion means is converted into the second analog conversion means and the third analog using the selection circuit network. A digital converting means which is selected from the converting means and which can be connected to the selected analog converting means is selected from the second digital converting means and the third digital converting means in the selecting circuit network. (Step 1), the attenuator, the 2-input 1-output analog multiplexer, the multiplication unit, and the 2-input 1 that can be connected to the selected set of the analog conversion unit and the digital conversion unit.
By selecting the analog signal of the selected analog converting means by controlling the input signal to the select pin of the output digital multiplexer and controlling the input signal to the select pin of the selected 2-input 1-output digital multiplexer. By selecting the digital signal of the selected digital converting means (step 3) and obtaining the output signal indicating the coincidence of the selected comparing means, the selected analog converting means and the selected digital converting means are selected. Check the reversibility and then select the output signal of the selected attenuator by controlling the input signal to the select pin of the selected 2-input 1-output analog multiplexer to select the selected 2-input 1-output. By controlling the input signal to the select pin of the output digital multiplexer By selecting the output signal of the selected digital multiplying means (step 4) and obtaining the output signal indicating the coincidence of the selected comparing means, the linearity of the selected analog converting means and the selected digital converting means are selected. Simultaneously verifying the linearity of the means, performing steps 1 to 4 for all individual analog conversion means in the second analog conversion means and the third analog conversion means, and then , Step 1 to step 4 using the selection circuitry to the second step
Of the analog converting means and all the individual analog converting means of the third analog converting means, the digital converting means whose linearity has not been verified yet, are converted into the second digital converting means and An analog conversion means which is selected from the third digital conversion means and which can be connected to the selected digital conversion means is provided by using the selection network, the second analog conversion means and the third analog conversion means. Means (step 5), and the attenuator, the 2-input 1-output analog multiplexer, the multiplication means, and the multiplying means which can be connected to the selected set of the analog conversion means and the digital conversion means. A 2-input 1-output digital multiplexer is selected using the selection network (step 6) and the selected 2-input 1-output is selected. By selecting an analog signal of the selected analog converting means by controlling an input signal to a select pin of the analog multiplexer and controlling an input signal to a select pin of the selected 2-input 1-output digital multiplexer. Reversing the selected analog conversion means and the selected digital conversion means by selecting the digital signal of the selected digital conversion means (step 7) and obtaining an output signal indicating the coincidence of the selected comparison means. And then selecting the output signal of the selected attenuator by controlling the input signal to the select pin of the selected 2-input 1-output analog multiplexer.
Selecting the output signal of the selected digital multiplying means by controlling the input signal to the select pin of the input one output digital multiplexer (step 8) to obtain an output signal indicative of the match of the selected comparing means. Simultaneously confirms the linearity of the selected analog exchanging means and the linearity of the selected digital converting means,
Performing steps 5 to 8 for all individual digital converting means in the second digital converting means and the third digital converting means,
Next, a selection circuit is used to connect the output of each of the third analog conversion means so that it can be input to the analog circuit instead of an external input signal to the analog circuit, and the third digital conversion means is connected. The input terminals of the conversion means are connected so that the output signal from the analog circuit to the outside can be branched and input, and each of the second analog conversion means transmits the signal from the digital circuit to the analog circuit. The second digital conversion means are connected to each other so as to transmit a signal from the analog circuit to the digital circuit, and the digital circuit is externally provided to the analog circuit to the third analog conversion means. A digital signal equivalent to an analog input signal is output, and is output from the analog circuit via the second digital conversion means. Whether the signal input to the digital circuit is the expected value or not, and the signal input from the analog circuit to the digital circuit via the third digital converting means is output from the analog circuit to the outside. The configuration is such that a test is carried out using two items as to whether or not the signal is a digital signal equivalent to the signal.

[0021]

Next, the configuration of an analog / digital hybrid integrated circuit of the present invention and a test method using the same will be described.
The basic principle will be explained.

In the present invention, (1) not only the D / A converter but also the A / D converter can be tested by the digital tester. (2) Not only the reversibility of the D / A conversion and the A / D conversion, Three new points have been added: a linear tester can be tested by a digital tester, and (3) a D / A converter and analog circuit components other than an A / D converter can be tested by a digital tester. .

In order to make this possible, the signal input to the A / D converter is not limited to the analog signal output from the D / A converter, but the analog signal output from the D / A converter is fixed. The output of the D / A converter is branched so that the signal attenuated by the attenuation factor of can be selected, an attenuator is added to one side, and an analog multiplexer can be selected to select that signal or one of the original analog signals. When a signal is input to the A / D converter via the attenuator and a signal is input via the attenuator, a unit for multiplying by (1 / α) times is selected via the digital multiplexer after the A / D conversion. Is the basic configuration.

First, a first test is performed as follows.
Now, assume that the attenuation rate is α (0 <α <1). The relationship between the digital signal x input to the D / A converter and the analog signal y output from the D / A converter is represented by y = f (x), and A / D
The relation between the analog signal y input to the converter and the digital signal z output from the A / D converter is written as z = g (y).

As the test procedure, first, the analog multiplexer outputs the analog signal output from the D / A converter directly to the input of the A / D converter and outputs the output from the A / D converter as it is. As described above, the analog multiplexer and the digital multiplexer are selected, the test signal is applied to the input terminal of the D / A converter, and the output is compared with the input. Mathematically speaking, for all x, it is tested whether x = g (f (x)). If this is true, then g · f = 1, that is, f = g ⁻¹ has been verified. If this is not the case, it is treated as a defective product.

If the above first test passes, then a second test is performed as follows.

First, the analog signal output from the D / A converter is passed through an attenuator that multiplies by α, the analog signal output is input to the A / D converter, and the digital signal output is (1 / α ) An analog multiplexer and a digital multiplexer are selected so as to output through a digital multiplication means for multiplication, a test signal is applied to the input terminal of the D / A converter, and the output and the input are compared. If you write in mathematical formulas,
For all x, test if x = (1 / α) · g · (α · f (x)). If this holds, ((1 / α) · g) · (α · f) = 1, that is, a · f = ((1 / α) · g) ⁻¹ = g ⁻¹ · α is verified. It will be. Since f = g ⁻¹ was verified in the first test, it was verified that α × f (x) = f (α × x) holds for all x when both are combined. Is equivalent to that. It can be mathematically proved that this holds only when f (x) = a · x, that is, only when f is linear.
The linearity of the converter can be tested. At the same time, g (y) = (1 / a) · y can also be obtained, so that the linearity of the A / D converter can be verified at the same time.

If each of the first and second tests described above has passed, the third test is performed as follows.

First, by switching the multiplexer, a digital input signal from some digital circuit or from the outside is transmitted to the D / A converter which has just been verified, and its output is output to A / D converter.
It is sent to an analog circuit that is neither a D / A converter nor a D / A converter (for example, a low-pass filter), and its output is sent to the A / D converter that has just been verified. It is analyzed by the correlation with the digital input signal sent to.

The above analog circuit can be verified by determining whether or not the correlation between the obtained digital input signal and digital output signal is as designed.

Since each of the analog circuit and the digital circuit generally has a plurality of channels for exchanging signals with the outside, in such a case, an analog signal to be input from the outside into the analog circuit is determined by a multiplexer. By switching, the analog signal output from the D / A converter is switched, and the analog signal output from the analog circuit to the outside is branched and one of the signals is sent to the A / D converter. Can be prepared from the digital circuit side, and all the outputs from the analog circuit can be received by the digital circuit section.

As described above, by combining the first, second and third tests, it is possible to verify all analog circuits on the digital tester.

In the third test, so to speak, the D / A converter is used as a waveform generator and the A / D converter is used as a measuring device. In the second test, the A / D converter and the D / A converter are used. It is an essential feature of the present invention that the verification of the linearity of the transducers provides the basis for their ability to be used as waveform generators and measuring instruments in the third test.

[0034]

FIG. 1 is a block diagram showing a configuration of an analog / digital hybrid integrated circuit according to a first embodiment of the present invention.

The analog / digital mixed integrated circuit 1 of this embodiment is an integrated circuit capable of analog input and analog output in which all processing of the integrated circuit 1 is performed by the digital circuit 2, and the analog input is from the analog input terminal 5. A /
It is configured such that it is input to the digital circuit 2 via the D converter 3, and the analog output is output from the analog output terminal 6 via the D / A converter 4 to the outside.

In the digital LSI tester of this embodiment, the new test targets are the A / D converter 3 and the D / A converter 4. Since the other components are only the digital circuit 2, a digital LSI tester for a conventional digital circuit may be used for this purpose.

In the integrated analog / digital integrated circuit 1 according to the first embodiment of the present invention, all means necessary for testing the A / D converter 3 and the D / A converter 4 are added to the digital circuit 2 in addition to the additional circuit. It is a configuration to be introduced as.

The configuration of this additional circuit includes a digital waveform generator 7, a signal source switching digital multiplexer 8, an attenuator 9 having an attenuation factor α of 0.5, a first analog multiplexer 10, and a second analog multiplexer. 1
1, a digital multiplier 12 having a multiplication rate (x2) that is the reciprocal of the attenuation rate α, a digital multiplexer 13,
And the comparison circuit 14. Further, this additional circuit provides an analog test enable terminal (A) for controlling these circuits.
TE) 15 and a test mode switching terminal (ATM) 1
6 and a comparison output terminal 17 for outputting the output from the comparison circuit 14 to the outside. A clock at the time of the test uses a clock common to the clock at the time of the normal operation and is supplied from the clock input terminal 18. It is.

Next, the analog / digital converter according to the first embodiment of the present invention will be described.
An outline of the procedure of the test method for the digital embedded integrated circuit will be described.

First, the ATM 16 is turned off, the first analog multiplexer 10 is set to the output side of the D / A converter 4, and at the same time, the digital multiplexer 13 is set to the output side of the A / D converter 3. Next, the ATE 15 is turned on to switch the second analog multiplexer 11 from the analog input terminal 5 to the first analog multiplexer 10, and at the same time, switch the signal source switching digital multiplexer 8 from the digital circuit 2 to the digital waveform generator 7. Switch to

As a result, the signal generated by the digital waveform generator 7 is input to the D / A converter 4. The signal is converted to an analog signal by the D / A converter 4 and then sent to the A / D converter 3 via the first analog multiplexer 10 and the second analog multiplexer 11.

Further, it is converted back into a digital signal by the A / D converter 3, and is supplied to one input terminal of the comparison circuit 14 via the digital multiplexer 13.

On the other hand, the signal generated by the digital waveform generator 7 is directly supplied to the other input terminal of the comparison circuit 14 through another path.
The comparison result is output from the comparison circuit 14, and the comparison output terminal 1
7 is transmitted.

The digital tester counts the number of clock signals supplied to the clock input terminal 18 for a predetermined number of patterns, and if the comparison output terminal 17 does not output an H-level signal during that time, the first test is performed. Passes. That is, the reversibility of the A / D converter 3 and the D / A converter 4 is verified.

Next, the ATM 16 is turned on and the first analog multiplexer 10 is set to the output side of the attenuator 9 having the attenuation factor of 0.5, and at the same time, the digital multiplexer 13 is set to the output side of the (x2) digital multiplier 12. Set. As a result, the signal generated by the digital waveform generator 7 is transmitted through the signal source switching digital multiplexer 8 to the D / A
After being supplied to the converter 4 and converted into an analog signal here, the signal amplitude is attenuated to (1/2) by the attenuator 9 and the A / D is passed through the first analog multiplexer 10 and the second analog multiplexer 11. It is sent to the converter 3.

Further, the signal is returned to a digital signal by the A / D converter 3 and shifted to the 1-bit MSB side by the (x2) digital multiplier 12, and then to one input terminal of the comparison circuit 14 via the digital multiplexer 13. Supplied.

On the other hand, since the signal generated by the digital waveform generator 7 is directly supplied to the other input terminal of the comparison circuit 14 through another path, the comparison result is output from the comparison circuit 14 in accordance with the coincidence / mismatch of the signals at both input terminals. And the comparison output terminal 17
Is transmitted to The second test passes if the number of clock signals supplied to the clock input terminal 18 for a predetermined number of patterns is counted on the digital tester side and the comparison output terminal 17 does not output an H level signal during that time. . That is, the linearity of the A / D converter 3 and the D / A converter 4 is simultaneously verified. Finally, ATE15 is turned off. This completes the test process of the analog part of the circuit, that is, the A / D converter 3 and the D / A converter 4.

Next, the analog / analog of the second embodiment of the present invention will be described.
A digital hybrid integrated circuit will be described.

Referring to FIG. 2, this embodiment is an integrated circuit capable of analog input in which all the processing of the integrated circuit 1 is performed by the digital circuit 2, and the analog input is supplied from the analog input terminal 5 to the A / D converter 3. Digital circuit 2 through
It is a configuration input to.

In this embodiment, it is the A / D converter 3 that is a new test target in the digital LSI tester. Since the other components are only the digital circuit 2, in this respect, it is the same as in the first embodiment that the test method by the digital tester of the conventional digital circuit may be applied.

The integrated analog / digital integrated circuit according to the second embodiment of the present invention has a configuration in which all means necessary for testing the A / D converter 3 are introduced as additional circuits outside the digital circuit 2. That is, this additional circuit includes the digital waveform generator 7, the D / A converter 4, and the attenuation rate α0.5.
Attenuator 9, a first analog multiplexer 10, a second analog multiplexer 11, a digital multiplier 12 having a multiplication factor that is the reciprocal of the attenuation rate α, a digital multiplexer 13, and a comparison circuit 14. Further, an analog test enable terminal (ATE) 15 for controlling these circuits and a test mode switching terminal (A
TM) 16 and a comparison output terminal 17 for outputting the output from the comparison circuit 14 to the outside. The test clock uses the same clock as the normal operation clock, and is supplied from the clock input terminal 18.

Since the outline of the procedure of the test method of this embodiment is exactly the same as that of the test method of the first embodiment, detailed description of the procedure is omitted.

Next, the analog / analog of the third embodiment of the present invention will be described.
A digital hybrid integrated circuit will be described.

Referring to FIG. 3, the analog / digital mixed integrated circuit of this embodiment is an integrated circuit capable of analog output in which all processing of the integrated circuit 1 is performed by the digital circuit 2, and the analog output is D / A. The configuration is such that the analog output terminal 6 is connected to the outside via the converter 4.

In this embodiment, the D / A converter 4 is a new test target in the digital LSI tester. Since the other constituent elements are only the digital circuit 2, in this respect, it is the same as in the first or second embodiment that the test method by the digital tester of the conventional digital circuit may be applied.

In the analog / digital mixed integrated circuit of the third embodiment of the present invention, as means necessary for testing the D / A converter 4, in addition to the digital circuit 2, the digital waveform generator 7 and the signal source are switched. A digital multiplexer 8, an attenuator 9 having an attenuation factor α0.5, a first analog multiplexer 10, an A / D converter 3, a digital multiplier 12, a digital multiplexer 13, and a comparison circuit 14. ing. Further, an analog test enable terminal (ATE) 15 for controlling these circuits is provided.
And a test mode switching terminal (ATM) 16 and a comparison output terminal 17 for outputting an output from the comparison circuit 14 to the outside. The test clock uses the same clock as the normal operation clock, and is supplied from the clock input terminal 18.

Since the outline of the procedure of the test method of this embodiment is exactly the same as that of the test method of the first or second embodiment, detailed description of the procedure is omitted.

Next, the analog / analog of the fourth embodiment of the present invention will be described.
A digital hybrid integrated circuit will be described.

Referring to FIG. 4, an analog / digital hybrid integrated circuit 41 of this embodiment is a digital waveform generator capable of performing digital processing among the components of the analog / digital hybrid integrated circuit of the first embodiment shown in FIG. Vessel 7,
Digital multiplexers 8 and 13, a multiplier 12,
This is a configuration in which the comparator 14 and the digital circuit 2 are incorporated in the same digital circuit 42.

The digital circuit 42 of this embodiment has a CP
Cell-based A with advanced digital macros such as U macroblocks or memory macroblocks
It is composed of SIC. Therefore, the number of additional circuits of the first embodiment can be minimized.

Analog / digital mixed integrated circuit 41
Is an analog test enable terminal (ATE)
45 are provided. Whether to do an analog test is AT
This is realized by the digital circuit 42 monitoring whether E45 is on or off.

The clock at the time of the test is a digital circuit 42
Depending on the test specification, a clock signal supplied from the clock input terminal 18 to the digital circuit 42 may be used, or a clock signal newly generated for testing in the digital circuit 42 may be used.

Next, the outline of the procedure of the test method of this embodiment will be described.

First, the ATE 45 is turned on, and the digital circuit 42 is notified of the operation in the analog test mode. Upon receiving this signal, the digital circuit 42 performs program processing using a CPU macro (not shown) in accordance with a test sequence set in advance on a memory macro block (not shown) in the digital circuit 42 by software. do.

In the program, first, the switching signal line 20 of the second analog multiplexer 11 is turned on, and the input signal of the second analog multiplexer 11 is switched to the first analog multiplexer 10. Next, the switching signal line 19 of the first analog multiplexer 10 is turned off, and the input signal of the first analog multiplexer 10 is switched to the output signal from the D / A converter 4.

Next, the test data and test signal generation subprogram stored in advance in the memory macro block are called to sequentially output a series of test signals to the D / A converter 4. The output test signal is converted into an analog signal by the D / A converter 4 and then sent to the A / D converter 3 via each of the first analog multiplexer 10 and the second analog multiplexer 11. Further, the digital signal is returned by the A / D converter 3 and input to the digital circuit 42. The input signal is compared with the output signal, and the comparison result is output to the outside from the digital output terminal 21 as a report.

The digital LSI tester receiving the output report can change the test sequence or judge the defective product after receiving the report result.

After passing through this series of tests, the program next turns on the switching signal line 19 of the first analog multiplexer 10 to change the input signal of the first analog multiplexer 10 to the output signal from the attenuator 9. Switch to.

Next, the test data and the test signal generation subprogram previously stored in the memory macro block are called, and a series of test signals are sequentially output to the D / A converter 4. The output test signal is converted into an analog signal by the D / A converter 4 and then sent to the A / D converter 3 via the first analog multiplexer 10 and the second analog multiplexer 11. Furthermore, A
The digital signal is returned by the / D converter 3 and input to the digital circuit 42.

The input signal is SHL (shift left)
After being doubled by an ALU block (not shown) in the CPU macro block by an instruction, the signal is compared with the output signal, and the comparison result is output to the outside from the digital output terminal 21 as a report. The digital tester that has received the output report can change the test sequence and determine a defective product after receiving the report result. The analog test ends when this series of tests passes.

In the present embodiment, the additional circuit configuration outside the digital circuit 42 is the minimum configuration, and the additional pin is only one pin of the ATE 45, and the influence on the semiconductor chip configuration is extremely small. The feature is that there is.

Next, an integrated analog / digital integrated circuit 51 according to a fifth embodiment of the present invention will be described with reference to FIG. 5. In this embodiment, some of the processing of the integrated circuit 51 is performed by a digital circuit 52. However, the integrated circuit is configured so that a considerable amount of processing is also performed by an analog circuit, and the analog circuit includes an A / D converter 53 and a D / A converter 5.
4 and other three analog circuit 22 components.

All analog input / output with the outside is performed to the analog circuit 22 without loss of generality. A /
When there is no analog processing other than D conversion 53 and D / A conversion 54, the analog input from the outside is converted to digital circuit 52.
It is regarded as an analog circuit having a function of directly transmitting it to the A / D converter 53 that leads to the output and receiving the output received from the digital circuit 52 via the D / A converter 54 as it is to the outside.

In this regard, in the analog / digital mixed integrated circuit 51, all analog input / output is performed with respect to the analog circuit 22, and the analog circuit 22 includes an A / D converter and a D / A converter. There is no converter at all, while the A / D and D / A converters present in the integrated circuit 51 are all used only for signal conversion between the analog circuit 22 and the digital circuit 52. Can be treated as

In this embodiment, each analog input terminal 55 is
On the other hand, a digital signal line 23 for analog input signal emulation and an analog multiplexer 25 for analog input signal selection are prepared, and the output from each digital signal line 23 for analog input signal emulation is passed through a D / A converter 54. The signal from the analog input terminal 55 is paired and connected to the two input terminals of the analog input signal selecting analog multiplexer 25,
Further, for each analog output terminal 56, an analog output signal capturing digital signal line 24 and an analog output signal / test analog signal selection analog multiplexer 26 are prepared, and signals to the respective analog output terminals 56 are analog output. A signal / test analog signal selection analog multiplexer 26 and a corresponding analog output signal capturing digital signal line 24 via an A / D converter 53.
And is taken into the digital circuit 52.

Therefore, the A / D added for the test
Number of converters 53 and D / added for testing
The number of A converters 54 is equal to the number of analog signals output from the analog circuit 22 to the outside and the number of analog signals input to the analog circuit 22 from the outside.

However, as a result, the number of A / D converters 53 that need to be introduced as constituent elements in the entire integrated circuit is 0.
In the case of the above, at least one A / D converter 53 for inverse conversion is necessary in the process up to the linearity test of the D / A converter 54 based on the principle of the present invention, and this is added.

Similarly, when the number of D / A converters 54 that need to be introduced as components in the entire integrated circuit is 0, at least one D / A converter 54 is added. Digital components required for testing (x2 multiplication means, etc.)
Is a configuration prepared in the digital circuit 52 similarly to the fourth embodiment.

In this test method, the A / D converter 53 and the D / A converter 54 are grouped one by one to avoid duplication as much as possible. As a result, the test time can be reduced.

The procedure of the test method is the same as the procedure of the test method of the fourth embodiment, in which the reversibility verification and the linearity verification are performed in this order, and all the A / D converters 53 and the D / A converters 54 are performed. Repeat until verification is completed. Thereafter, the selection of the multiplexer is switched, and the A / D which originally exists for communicating the analog circuit 22 and the digital circuit 52 is provided.
The converter 53 and the D / A converter 54 function in the normal mode.

All the other D / A converters are for emulating analog input signals, and other A / A converters are also used.
Since all the / D converters are for capturing analog signals, a multiplexer is set so that these are selected.

Then, similarly to the fourth embodiment, the software configured on the memory block sends an analog input signal to all the analog input signal emulation digital signal lines 23 to emulate the analog input signal. D / A for communication of analog circuit 22
A signal set for the test is also output to the converter, and a complete test environment is set for the analog circuit 22.

That is, the obtained output to the A / D converter for communication is received as it is, while the analog signal output to the outside is received through all the analog output signal capturing digital signal lines 24. Upon receiving these data, the digital circuit 52 executes preset test processing by program processing, and transmits the test result from the digital output terminal 21 to the digital LSI tester. By adopting such a configuration, a general digital / analog mixed integrated circuit digital test method is realized.

A conventional technique as a test method for a general digital / analog mixed integrated circuit is disclosed in Japanese Patent Laid-Open No. 2-1978.
As shown in FIG. 1 of Japanese Patent Publication No. 0, the digital part is a digital tester and the analog part is a tester separately from the analog tester. Then mission Ai
n) from the digital circuit side, and a test in which the original analog output (called the mission Aout in the prior art) is taken into the digital circuit side and analyzed. It is not based on a method, and for this reason, performing all tests with a digital tester alone is the first realization of the present invention.

In the description of this embodiment, the method of inputting the information for forming the signal that emulates the analog input signal from the outside to the digital circuit (42, 52) side is not the essence of the invention. Although not mentioned, it is obvious that general digital circuit test facilitation methods such as a method using a scan chain or boundary scan can be used together in the circuit configuration and the present test method of the present invention, and simultaneous application of such a method is not possible. It goes without saying that the present invention is naturally included in the scope of the present invention as long as the present invention is used for the analog section test method.

In this embodiment, the A / D converter,
The amplification factor of the D / A converter was not mentioned, but in both cases, the verification of the amplification factor can be easily performed by performing a comparison process using a reference voltage, so that it is not mentioned. Obviously, the presence or absence does not affect the application range of the present invention.

[0087]

As described above, according to the present invention, a test method for a digital circuit having a conventional D / A converter using only a digital tester (Japanese Patent Laid-Open No. 1-138478).
Japanese Patent Application Laid-Open No. H10-177,1992) overcomes the drawback that only D / A converters can be verified, and that only reversibility with the A / D converter mounted for testing can be verified. Since it can be verified, it is possible to perform a complete test of a digital LSI tester of a general analog / digital hybrid integrated circuit as an application.

As a result, even a tester who does not have analog circuit expertise can easily execute a test of an analog / digital mixed integrated circuit in a digital test environment inexpensive and having a large number of operating units, thereby reducing the test time and the test cost. It is effective in promoting the design for reduction and testability.

[Brief description of drawings]

FIG. 1 is a block diagram of a mixed analog / digital integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block configuration diagram of an analog / digital hybrid integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a mixed analog / digital integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a block configuration diagram of an analog / digital hybrid integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a mixed analog / digital integrated circuit according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram of a conventional analog / digital hybrid integrated circuit.

[Explanation of symbols]

1, 41, 51, 61 Integrated circuit 2, 42, 52, 62 Digital circuit 3, 53, 63 A / D converter 4, 54, 64 D / A converter 5, 55 Analog input terminal 6, 56 Analog output terminal 7 Digital Waveform Generator 8 Digital Multiplexer for Signal Source Switching 9 (1/2) Attenuator 10 First Analog Multiplexer 11 Second Analog Multiplexer 12 (× 2) Multiplier 13 Digital Multiplexer 14,74 Comparison Circuit 15, 45, 65 Analog test enable terminal 16 Test mode switching terminal 17 Comparison output terminal 18 Clock input terminal 19 First analog multiplexer switching signal line 20 Second analog multiplexer switching signal line 21 Digital output terminal 22 Other than D / A converter and A / D converter Analog circuit 23 Digital signal output line for analog input signal emulation 24 Digital signal line for capturing analog output signal 25 Analog multiplexer for analog input signal selection 26 Analog output signal / test Analog signal selection analog multiplexer

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Claims (8)

[Claims] 1. An analog / digital hybrid circuit comprising: a digital circuit; digital conversion means for converting an analog input signal to an input signal to the digital circuit; and analog conversion means for converting an output signal of the digital circuit to an analog signal. An integrated circuit, wherein one of two analog input terminals inserted between a first analog input terminal for receiving the analog input signal and an analog input terminal of the digital conversion means has one of the first analog input terminals. A first analog multiplexer having an output terminal connected to an analog input terminal of the digital conversion means, an attenuator for attenuating an analog output signal of the analog conversion means at a constant attenuation rate, One of the analog output signal and the output signal of the attenuator is selected and the selected analog signal is output. A second analog input terminal of the first analog multiplexer, the second analog input terminal being connected to the other input terminal not connected to the analog input signal.
An analog multiplexer, digital multiplying means for multiplying the digital signal of the digital converting means by a multiplication factor equal to the reciprocal of the attenuation rate of the attenuator, and any one of the digital signal of the digital converting means and the output signal of the digital multiplying means Digital multiplexer for selecting one of them, first input means for inputting an input signal to a selection pin for determining selection of the first analog multiplexer, and input signal for a selection pin for determining selection of the digital multiplexer. A second input means for inputting an input signal to a selection pin for determining the selection of the second analog multiplexer, a digital input signal input to the analog conversion means, and an output signal of the digital multiplexer. And comparing means for comparing Analog / digital mixed integrated circuit. 2. A test method for testing an analog / digital hybrid integrated circuit according to claim 1, wherein
Selecting an output signal of the second analog multiplexer by controlling an input signal to a selection pin of the analog multiplexer, and controlling an input signal to a selection pin of the second analog multiplexer to control the analog conversion means. By selecting the analog output signal and controlling an input signal to a selection pin of the digital multiplexer, a digital signal of the digital conversion means is selected, and an output signal indicating a match of the comparison means is obtained. A reversibility confirmation method for confirming the reversibility of the digital conversion means;
The output signal of the attenuator is selected by controlling the input signal to the selection pin of the second analog multiplexer without changing the input signal to the selection pin of the analog multiplexer, and the input signal to the selection pin of the digital multiplexer is changed. Simultaneous linearity for simultaneously checking the linearity of the analog conversion means and the linearity of the digital conversion means by selecting the output signal of the digital multiplication means by controlling the signal and obtaining an output signal indicating the coincidence of the comparison means. A test method characterized by including a sex confirmation method. 3. An integrated analog / digital integrated circuit including a digital circuit and digital conversion means for converting an analog input signal into an input signal to the digital circuit, wherein the first analog input receives the analog input signal. One of the two analog input terminals inserted between the terminal and the analog input terminal of the digital conversion means is connected to the first analog input terminal and the output terminal is connected to the analog input terminal of the digital conversion means. A first analog multiplexer connected to the end, analog conversion means, digital input signal input means for inputting a digital input signal of the analog conversion means, and attenuating an analog output signal of the analog conversion means at a constant attenuation rate Attenuator, and the analog output signal of the analog conversion means and the attenuator. A second analog multiplexer that selects one of the output signals and supplies the selected analog signal to the other of the two analog input terminals of the first analog multiplexer that is not connected to the analog input signal; Digital multiplying means for multiplying the digital signal of the digital converting means by a multiplication factor equal to the reciprocal of the attenuation rate of the attenuator; and one of the digital signal of the digital converting means and the output signal of the digital multiplying means. A digital multiplexer for selection, and first input means for inputting an input signal to a selection pin for determining selection of the first analog multiplexer;
A second input means for inputting an input signal to a selection pin for determining selection of the digital multiplexer and an input signal for a selection pin for determining selection of the second analog multiplexer; An integrated analog / digital integrated circuit, comprising: comparing means for comparing an input digital input signal with an output signal of the digital multiplexer. 4. A test method for testing an integrated analog / digital integrated circuit according to claim 3, wherein
Selecting an output signal of the second analog multiplexer by controlling an input signal to a selection pin of the analog multiplexer, and controlling an input signal to a selection pin of the second analog multiplexer to control the analog conversion means. By selecting an analog signal and controlling an input signal to a selection pin of the digital multiplexer, a digital signal of the digital conversion means is selected, and an output signal indicating a match of the comparison means is obtained. A reversibility confirmation method for confirming the reversibility of the conversion means, and controlling the input signal to the selection pin of the second analog multiplexer without changing the input signal to the selection pin of the first analog multiplexer. Select the output signal of the attenuator and Linearity check for controlling the input signal to the select pin of the multiplexer and selecting the output signal of the digital multiplying means and obtaining the output signal indicating the coincidence of the comparing means to check the linearity of the digital conversion means. And a test method. 5. An integrated analog / digital integrated circuit including a digital circuit and analog conversion means for converting an output signal of the digital circuit into an analog signal,
An attenuator that attenuates an analog output signal of the analog conversion means at a constant attenuation rate; an analog multiplexer that selects one of the analog signal of the analog conversion means and an output signal of the attenuator; and an output of the analog multiplexer. Digital conversion means for converting a signal into a digital signal; digital multiplication means for multiplying the digital signal of the digital conversion means by a multiplication factor equal to the reciprocal of the attenuation rate of the attenuator; digital signal of the digital conversion means and the digital signal A digital multiplexer for selecting one of the output signals of the multiplying means;
Input means for inputting an input signal to a selection pin for determining the selection of the analog multiplexer and for inputting an input signal to a selection pin for determining the selection of the digital multiplexer; output signals of the digital circuit and the digital multiplexer; A mixed analog / digital integrated circuit, comprising: comparison means for comparing an output signal. 6. A test method for testing an analog / digital mixed integrated circuit according to claim 5, wherein an analog signal of said analog conversion means is selected by controlling an input signal to a selection pin of said analog multiplexer. The reversibility of the analog conversion means and the digital conversion means is confirmed by selecting the digital signal of the digital conversion means by controlling the input signal to the selection pin of the multiplexer and obtaining the output signal indicating the coincidence of the comparison means. And a digital multiplying means by controlling the input signal to the select pin of the analog multiplexer to select the output signal of the attenuator and controlling the input signal to the select pin of the digital multiplexer. Select the output signal of And a linearity confirmation method for confirming the linearity of the analog conversion means by obtaining an output signal indicating the coincidence of the comparison means. 7. A digital circuit, second digital conversion means other than the digital conversion means for giving a signal to the digital circuit, and the analog conversion means for receiving a signal from the digital circuit. An analog / digital hybrid integrated circuit including an analog circuit having an analog processing section composed of another second analog conversion means, comprising at least one attenuator that attenuates at a constant attenuation rate, and at least one attenuator. Multiplying means having a multiplying factor equal to the reciprocal of the attenuation factor of the attenuator, comparing means for comparing at least one two sets of digital inputs, and at least one
2 2-input output analog multiplexers, at least 1 2-input 1-output digital multiplexer, 1 if the sum of the number of input signals from the outside to the analog circuit and the number of the second analog converting means is 0. If the number is greater than 0, the number of third analog conversion means is equal to the number of input signals from the outside to the analog circuit, the number of output signals from the analog circuit to the outside, and the number of output signals from the analog circuit to the second. When the sum of the number of the digital converting means is 0, it is one, and when it is greater than 0, the third digital converting means is provided for the number of the output signals from the analog circuit to the outside, and in the predetermined operation mode. Is the second
At least one of the second digital conversion means and the third digital conversion means for any one of the analog conversion means and the third analog conversion means.
And the second digital conversion means and the third
And at least one of the second analog conversion means and the third analog conversion means can be determined for any one of the digital conversion means. One of the third analog conversion means is determined to the second digital conversion means and one of the third digital conversion means to one of the two inputs of the two-input one-output analog multiplexer. If one is selected, it is directly connected via one of the two-input one-output analog multiplexers, or if the other is selected, it is connected via the attenuator and the output from one of the digital conversion means is output to the Connected to a digital multiplying means and connected to one of the analog converting means and an output from the digital multiplying means to one comparing means Or in another predetermined operation mode, the output of each of the third analog conversion means is input to the analog circuit instead of an external input signal to the analog circuit, and the third digital conversion means. To determine all selection states of the selection circuit network and a selection circuit network having a plurality of multiplexers capable of branching and inputting an output signal from the analog circuit to each input terminal. An analog / digital mixed integrated circuit having a sufficient number of input signals to select pins. 8. A test method for testing an analog / digital mixed integrated circuit according to claim 7, wherein each analog conversion means is converted into said second analog conversion means and said third analog conversion using said selection circuit network. And selecting the digital conversion means connectable to the selected analog conversion means from the second digital conversion means and the third digital conversion means. Step 1), for the selected set of the analog conversion means and the digital conversion means, the attenuator, the 2-input 1-output analog multiplexer, the multiplication means, and the 2-input 1-output digital multiplexer connectable to both of them. The analog signal of the selected analog conversion means is selected by controlling the input signal to the selection pin. Selecting the digital signal of the selected digital converting means by controlling the input signal to the select pin of the selected 2-input 1-output digital multiplexer (step 3), and matching the selected comparing means. By confirming the reversibility of the selected analog conversion means and the selected digital conversion means, and then inputting the input signal to the selection pin of the selected 2-input 1-output analog multiplexer. By controlling the output signal of the selected attenuator, and controlling the input signal to the select pin of the selected 2-input 1-output digital multiplexer to control the output signal of the selected digital multiplying means. By selecting (step 4) and obtaining an output signal indicating the match of the selected comparing means. The linearity of the selected analog conversion means and the linearity of the selected digital conversion means are simultaneously confirmed, and steps 1 to 4 are performed for the second analog conversion means and the third analog conversion means. For each individual analog conversion means, and then using the selection circuitry to perform steps 1 to 4 of the second analog conversion means and the third analog conversion means. Among the second digital conversion means and the third digital conversion means, the digital conversion means whose linearity has not been verified when executed for all the individual analog conversion means therein are selected. An analog conversion means connectable to the selected digital conversion means is connected to the second analog conversion means using the selection circuit network. The attenuator and the 2-input 1-output analog multiplexer which are selected from the third analog conversion means (step 5) and can be connected to the selected combination of the analog conversion means and the digital conversion means. By selecting the multiplying means and the 2-input 1-output digital multiplexer using the selection network (step 6), and controlling the input signal to the select pin of the selected 2-input 1-output analog multiplexer. The analog signal of the selected analog conversion means is selected and the selected 2
Selecting the digital signal of the selected digital converting means by controlling the input signal to the select pin of the input 1 output digital multiplexer (step 7);
The reversibility of the selected analog conversion means and the selected digital conversion means is confirmed by obtaining an output signal indicating the coincidence of the selected comparison means, and then the selected 2-input 1-output analog Select the output signal of the selected attenuator by controlling the input signal to the select pin of the multiplexer to select the selected two inputs 1
Selecting the output signal of the selected digital multiplying means by controlling the input signal to the select pin of the output digital multiplexer (step 8) and obtaining the output signal indicative of the match of the selected comparing means; The linearity of the selected analog exchange means and the linearity of the selected digital conversion means are confirmed at the same time, and steps 5 to 8 are performed among the second digital conversion means and the third digital conversion means. For each individual digital conversion means, and then using a selection network to direct the output of each of the third analog conversion means to the analog circuit instead of an external input signal to the analog circuit. From the analog circuit to each input terminal of the third digital converting means. Each of the second analog converting means is connected so that an output signal to the unit can be branched and inputted, and each of the second analog converting means is connected so as to transmit a signal from the digital circuit to the analog circuit. Is connected so as to transmit a signal from the analog circuit to the digital circuit, and outputs a digital signal equivalent to an analog input signal externally given to the analog circuit from the digital circuit to the third analog converting means, Whether the signal input from the analog circuit to the digital circuit via the second digital converting means is as expected and whether the signal from the analog circuit to the digital circuit is passing through the third digital converting means. The input signal is a digital signal equivalent to the analog signal output from the analog circuit to the outside. Test wherein the testing the two items of whether or not as a criterion.