JPH086856A - Bus interface adapter - Google Patents

Abstract

PURPOSE:To improve the throughput of a system by lightening the load on an S bus at the time of DMA write transfer. CONSTITUTION:A decoder 11 decodes DMA transfer length which is sent from IO devices 2-1-2-n through a DMA transfer length indication bus 102. A comparator 13 compares the DMA transfer length from the decoder 11 with the cache block length value from a cache block length value holding part 12 and outputs the comparison result to an IO bus interface control part 14. The IO bus interface control part 14 drives a memory write-back control part 17 when the comparison result shows a coincidence to issue a memory write-back request, accompanying a request to invalidate a target block, on the S bus 100 through an S bus interface control part 19. The IO bus interface control part 14 changes the state of the target block in an IO cache 15 into an invalidated state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface adapter, and more particularly to a DMA from an input / output device to a memory device.
(Direct memory access) Control method of store-in type I / O cache in write transaction.

[0002]

2. Description of the Related Art A bus interface adapter of this type includes a processor having a store-in cache or a bus to which one or more bus interface adapters can be connected (hereinafter referred to as S bus), and an input / output device for performing DMA control. Are installed between a plurality of connectable buses (hereinafter referred to as IO buses), and have a store-in type cache (hereinafter referred to as IO cache) inside.

In the information processing apparatus having the above-mentioned bus interface adapter, since a plurality of store-in type caches exist in the apparatus, the consistency of the stored contents between the plurality of store-in type caches and the main memory can be determined. There is a question of how to keep it.

A protocol for maintaining the consistency of stored contents in a plurality of store-in caches and the main memory will be described below. Here, a case where data is written from the input / output device to the main memory by DMA control (hereinafter referred to as DMA write) will be described.

The target block to be DMA-written exists in the IO cache, the block stored in the IO cache is valid, and the same block as that block does not exist in the other store-in type cache. CE is a state in which the contents of the block match the contents of the corresponding block in the main memory.

Further, the target block to be DMA-written exists in the IO cache, the block stored in the IO cache is valid, and the same block as that block does not exist in other store-in type caches.
Further, the state in which the contents of the block do not match the contents of the corresponding block in the main memory is designated as DE.

When the state of the target block of the DMA write is CE or DE, the other store-in type cache and the main memory are not accessed at all, and the self I
Write data to the target block of the O-cache and change the state of the target block to DE.

On the other hand, the target block to be DMA-written exists in the IO cache, the block stored in that IO cache is valid, and the same block as that block also exists in other store-in type caches.
Further, a state in which the contents of the block match the contents of the corresponding block in the main memory is designated as SH.

Further, the target block to be DMA-written exists in the IO cache, the block stored in the IO cache is valid, and the same block as that block also exists in other store-in type caches.
Further, the state where the content of the block does not match the content of the corresponding block of the main memory is DS.

When the state of the target block of the DMA write is SH or DS as described above, a request to invalidate the same block as the target block of the other store-in type cache is issued and write data is written to the target block of the own IO cache. Is written to change the state of the target block to DE.

When the target block of the DMA write does not exist in the own IO cache, a read request accompanied by a request to invalidate the same block as the target block causes the target block to be moved to the own IO cache from another store-in type cache or main memory. After reading, the write data of DMA write is written.

In the read request accompanied by the invalidation request, immediately after the target block is read, the same block as the target block of the other store-in type cache is controlled to be invalidated. This invalid state is I
V.

When reading the target block of the DMA write, if the states of all the blocks in the own IO cache are DE, there is no storage destination for the data read from another store-in type cache or main memory. The operation of writing back an arbitrary block in the own IO cache to the main memory is performed.

After that, when the data read from another store-in type cache or the main memory is stored in the own IO cache, the write data of the DMA write is written to the target block and the state of the target block is changed to D.
Change to E and end the DMA write operation.

[0015]

In the conventional control system (hereinafter referred to as IO cache control system) for caching DMA transfer data in a system having a bus to which a plurality of store-in type caches can be connected, an S bus is used. For efficient use, the size of data transferred via the S bus is limited to a certain data length (hereinafter referred to as cache block length).

Therefore, an IO cache is provided in the bus interface adapter to improve the efficiency of the SBus. That is, when the size of the data transferred via the S bus is the cache block length or less, the data is temporarily stored in the IO cache and then S
Sending on the bus.

When a DMA write transfer having the same length as the cache block length is continuously performed, a read request accompanied by a request for invalidation is issued to the IO cache in order to maintain the consistency of the store-in type cache. At the same time, the write-back to the main memory of the data uniquely held in the IO cache occurs in the system every time.

That is, on the S bus, one DMA write transfer causes transfer of the DMA write transfer length via the IO cache twice, which increases the load on the S bus.

Therefore, an object of the present invention is to solve the above problems and provide a bus interface adapter capable of reducing the load on the S bus during DMA write transfer and improving the system throughput. It is in.

[0020]

A bus interface adapter according to the present invention comprises a bus to which a plurality of devices having a store-in type cache memory and a main memory are connected, and a plurality of input / outputs for direct memory access transfer. A bus interface adapter that is connected to a device and has the store-in type cache memory, the comparing means comparing the transfer length in the direct memory access transfer with a preset data length, and the comparison result of the comparing means. Means for writing the data of the direct memory access transfer to the main storage device via the bus and invalidating the contents of the cache memory of each of the plurality of devices corresponding to the data. ing.

In addition to the above configuration, another bus interface adapter according to the present invention stores the data of the direct memory access transfer in the cache memory by store-in control when the comparison result of the comparison means indicates a match. Then, a means for controlling to write to the main memory is provided.

Another bus interface adapter according to the present invention connects a bus to which a plurality of devices having a store-in type cache memory and a main storage device are connected, and a plurality of input / output devices for direct memory access transfer. And a bus interface adapter having the store-in type cache memory, the comparing means being provided in each of the plurality of input / output devices and comparing the transfer length in the direct memory access transfer with a preset data length. When the comparison result of the comparison means indicates a match, the data of the direct memory access transfer is written to the main memory device via the bus, and the contents of the cache memory of each of the plurality of devices corresponding to the data are written. And means for invalidating.

In addition to the above configuration, the bus interface adapter according to the present invention stores the data of the direct memory access transfer in the cache memory by store-in control when the comparison result of the comparison means indicates a match. Then, a means for controlling to write in the main memory is provided.

[0024]

When the DMA transfer length is compared with the cache block length value at the time of DMA write, and the comparison result shows a match,
Issue a memory writeback request with an invalidation request for the target block. At this time, if the target block is held in the IO cache, the state of the corresponding block is changed to IV indicating the invalidated state.

If the comparison result of the DMA transfer length and the cache block length value shows a mismatch, the target block is IO
Store-in control is performed for the IO cache depending on whether it exists in the cache.

As a result, the IO cache control system can be dynamically switched by adding a small amount of hardware, so that the load on the SBus 100 can be reduced according to the DMA write transfer from various IO devices. The system throughput can be improved.

[0027]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a bus interface adapter 1 and a main memory 3 are connected to an S bus 100, and a bus interface adapter 1 and IO devices 2-1 to 2-n having DMA transfer control are connected to an IO bus 101. Has been done.

Further, the bus interface adapters 1 and I
O devices 2-1 to 2-n are DMA transfer length instruction bus 102
Are connected by the DMA transfer length instruction bus 1
The DMA transfer length is output from the IO devices 2-1 to 2-n to the bus interface adapter 1 via 02.

The bus interface adapter 1 includes a decoder 11, a cache block length value holding unit 12, a comparator 13, an IO bus interface control unit 14, an IO cache 15, and a read control unit 16 with an invalidation request.
A memory write-back control unit 17 with an invalidation request, another cache invalidation instruction control unit 18, and an SBus interface control unit 19.

The decoder 11 is a DMA transfer length instruction bus 10
D sent from the IO devices 2-1 to 2-n via
The MA transfer length is decoded and the DMA transfer length is compared with the comparator 1.
Output to 3.

The cache block length value holding unit 12 holds a preset cache block length value and outputs the cache block length value to the comparator 13. Comparator 1
3 compares the DMA transfer length from the decoder 11 with the cache block length value from the cache block length value holding unit 12, and outputs the comparison result to the IO bus interface control unit 14.

The IO bus interface controller 14 is an IO
The data transfer by the bus 101 is controlled, and the read control unit 16 with the invalidation request, the memory writeback control unit 17 with the invalidation request, and the other cache invalidation instruction control unit 18 are controlled according to the comparison result of the comparator 13. Drive control respectively.

The read control unit 16 controls the issuance of a read request (coherent read EX request) accompanied by the invalidation request, and the memory write-back control unit 17 accompanied by the invalidation request (memory write-back request (write)). (IV request) issuance is controlled.

The other cache invalidation instruction control unit 18 controls the issuance of an invalidation request (IV request) to the corresponding block in another store-in type cache (not shown). The SBus interface control unit 19 controls the SBus protocol.

FIG. 2 is a flow chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

Here, the target block to be DMA-written exists in the IO cache 15, and the IO cache 1
5 is valid, and the same block as that block does not exist in another store-in type cache, and the content of the block is the main memory 3
CE is a state in which the contents of the corresponding block of (1) match.

Further, the target block to be DMA-written exists in the IO cache 15, and the IO cache 15 has the target block.
The block stored in is valid, the same block as that block does not exist in another store-in type cache, and the content of the block does not match the content of the corresponding block of the main memory 3. Is DE.

Further, the target block to be DMA-written exists in the IO cache 15, and the IO cache 1
The block stored in 5 is valid, and the same block as that block exists in another store-in type cache, and the content of the block is stored in the main memory 3
The state that matches the contents of the corresponding block of is designated as SH.

Furthermore, the target block to be DMA-written exists in the IO cache 15, the block stored in the IO cache 15 is valid, and the same block as that block is also stored in another store-in type cache. A state in which the block exists and the contents of the block do not match the contents of the corresponding block of the main memory 3 is DS. The state in which the block of the store-in type cache is invalid is IV.

The IO devices 2-1 to 2-n issue the DMA transfer length to the DMA transfer length instruction bus 102 at the time of DMA write. The decoder 11 of the bus interface adapter 1 is D
The DMA transfer length on the MA transfer length instruction bus 102 is decoded, and the DMA transfer length is output to the comparator 13.

The comparator 13 compares the DMA transfer length from the decoder 11 with the cache block length value held in the cache block length value holding unit 12 (step S in FIG. 2).
1), the comparison result is the IO bus interface control unit 1
4 is output.

When the comparison result of the comparator 13 indicates a match, the IO bus interface control unit 14 drives the memory write back control unit 17 to control the memory write back request accompanied with the invalidation request for the target block by the S bus interface control. It is issued on the SBus 100 via the unit 19 (step S2 in FIG. 2).

At this time, the IO bus interface control unit 14 determines whether or not the target block is held in the IO cache 15 (step S3 in FIG. 2), and when the target block is held in the IO cache 15, Changes the state of the corresponding block to IV (step S4 in FIG. 2).

When the comparison result of the comparator 13 indicates disagreement, the IO bus interface control unit 14 determines whether or not the target block exists in the IO cache 15 (step S5 in FIG. 2).

If the target block exists in the IO cache 15, the IO bus interface control unit 14 executes the DMA.
The write data of the write is written in the corresponding block in the IO cache 15 (step S6 in FIG. 2), and it is determined whether the state of the corresponding block is SH or DS (step S7 in FIG. 2).

The IO bus interface controller 14 is an IO
The state of the corresponding block in the cache 15 is SH or D
When it is determined to be S, the other cache invalidation instruction control unit 18 is driven, and an invalidation request for the corresponding block in another store-in type cache is issued by the S bus interface control unit 19.
Issued on the S bus 100 via the (step S in FIG. 2).
8).

The IO bus interface control unit 14 changes the state of the block in the IO cache 15 in which the write data is written to DE indicating that the data is the only data existing in the system (step S9 in FIG. 2).

The IO bus interface controller 14 is an IO
The state of the corresponding block in the cache 15 is SH or D
If it is not judged as S, I which has written the write data
The state of the corresponding block in the O-cache 15 is changed to DE indicating that the data is the only data existing in the system (step S9 in FIG. 2).

On the other hand, the IO bus interface controller 14
If the target block does not exist in the IO cache 15, it drives the read control unit 16 and issues a read request accompanied by an invalidation request onto the S bus 100 via the S bus interface control unit 19 (step in FIG. 2). S10). After that, the target block of DMA write is read and write data is written.

The IO bus interface control unit 14 is DM
When reading the target block of A write, it is determined whether all the states of the blocks in the IO cache 15 are DE (step S11 in FIG. 2).

The IO bus interface controller 14 is an IO
When it is determined that all the blocks in the cache 15 are in the DE state, the memory write-back control unit 17 is driven and the memory write-back request accompanied by the invalidation request is issued (step S12 in FIG. 2).

The IO bus interface controller 14 is an IO
When write-back of an arbitrary block in the cache 15 to the main memory 3 is performed, a target block for DMA write is read and stored in that block, and write data for DMA write is written in that block (step S13 in FIG. 2). .
At the same time, the state of the block is changed to DE (step S9 in FIG. 2).

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a bus interface adapter 4 and a main memory 3 are connected to the S bus 100, and a bus interface adapter 4 and IO devices 2-1 to 2-n having DMA transfer control are connected to the IO bus 101.
And are connected.

The bus interface adapter 4 and I
O devices 2-1 to 2-n are DMA transfer length-cush block length coincidence report line (hereinafter referred to as report line) 103-1
This report line 10
The match / mismatch between the DMA transfer length and the preset cache block length value is reported from the IO devices 2-1 to 2-n to the bus interface adapter 4 via the 3-1 to 103-n.

The bus interface adapter 4 includes an IO bus interface control unit 41, an IO cache 42,
It is composed of a read control unit 43 with an invalidation request, a memory write-back control unit 44 with an invalidation request, another cache invalidation instruction control unit 45, and an S bus interface control unit 46.

The IO bus interface control unit 41 is an IO
The data transfer by the bus 101 is controlled, and the read control unit 43 with the invalidation request, the memory writeback control unit 44 with the invalidation request, and the other cache invalidation instruction control unit 45 are reported to the report lines 103-1 to 103-. Drive control is performed according to the match / mismatch between the DMA transfer length and the cache block length value input from the IO devices 2-1 to 2-n via n.

The read control unit 43 controls the issuance of the read request accompanied by the invalidation request. The memory write-back control unit with an invalidation request 44 controls the issuance of the memory write-back request with an invalidation request.

The other cache invalidation instruction control unit 45 controls the issuance of the invalidation request to the corresponding block in the other store-in type cache. The SBus interface control unit 46 controls the SBus protocol.

In another embodiment of the present invention, the IO devices 2-1 to 2-1
In 2-n, the DMA transfer length is compared with a preset cache block length value, and the match / mismatch is reported to the bus interface adapter 4 via the report lines 103-1 to 103-n. Other than that, the operation of each step of the flowchart of FIG. 2 is performed as in the embodiment of the present invention.

As described above, the DMA transfer length and the cache block length value are compared at the time of the DMA write by the IO devices 2-1 to 2-n, and when the comparison result shows a match, the memory write-back control unit 17 is operated. To drive and issue a memory write-back request accompanied by an invalidation request for the target block onto the SBus 100 via the SBus interface control unit 19 and write the write data of the DMA write into the main memory 3. Since the IO cache control method can be dynamically switched by adding a small amount of hardware, various IO devices 2-1 to 2-n can be used.
The load on the SBus 100 can be reduced according to the incoming DMA write transfer, and the system throughput can be improved.

[0062]

As described above, according to the present invention, when the comparison result of the transfer length in the direct memory access transfer and the preset data length show a match, the data of the direct memory access transfer is transferred to the bus. By writing the data to the main memory via the cache memory and invalidating the contents of the cache memory of each of the plurality of devices corresponding to the data, the load on the S bus at the time of DMA write transfer can be reduced, and the system throughput can be improved. There is an effect that it can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention.

[Explanation of symbols]

1,4 Bus interface adapter 2-1 to 2-n IO device having DMA control 3 Main memory 11 Decoder 12 Cache block length value holding unit 13 Comparator 14,41 IO bus interface control unit 15,42 IO cache 16,43 Read control unit with invalidation request 17,44 Memory write-back control unit with invalidation request 18,45 Other cache invalidation instruction control unit 19,46 S bus interface control unit 100 S bus 101 IO bus 102 DMA transfer length instruction Bus 103-1 to 103-n DMA transfer length-cache block length match report line

Claims (4)

[Claims] 1. A store-in type cache which connects a bus to which a plurality of devices having a store-in type cache memory are connected to a main storage device and a plurality of input / output devices for direct memory access transfer. A bus interface adapter having a memory, the comparing means comparing the transfer length in the direct memory access transfer with a preset data length, and the direct memory access transfer of the direct memory access transfer when the comparison result of the comparing means indicates a match. A bus interface adapter comprising means for writing data to the main memory via the bus and invalidating the contents of the cache memory of each of the plurality of devices corresponding to the data. 2. When the comparison result of the comparison means indicates a match, the direct memory access transfer data is stored in the cache memory by store-in control and then written in the main storage device. The bus interface adapter according to claim 1, wherein: 3. A store-in cache which connects a bus to which a plurality of devices having a store-in type cache memory are connected to a main storage device and a plurality of input / output devices for direct memory access transfer A bus interface adapter having a memory, comprising: a comparison unit provided in each of the plurality of input / output devices, for comparing a transfer length in the direct memory access transfer with a preset data length, and a comparison result of the comparison unit. A means for writing the data of the direct memory access transfer to the main memory device via the bus and indicating the contents of the cache memory of each of the plurality of devices corresponding to the data when the coincidence is shown. Bus interface adapter characterized by. 4. When the comparison result of the comparison means indicates a match, the direct memory access transfer data is stored in the cache memory by store-in control and then written in the main storage device. The bus interface adapter according to claim 3, characterized in that: