JPH086602A - Fail-safe circuit and security protection device - Google Patents

Abstract

PURPOSE:To continue the operation of a controlled system when the controlled system is operated on the safe side. CONSTITUTION:The fail-safe circuit and security protection device are equipped with a latch means 3 which maintains the output of a trip signal 2a for operating the controlled system 9 on the safe side when the trip signal 2a is outputted from a logical operation means 2, an oscillator 10 which outputs an alternating signal 10a, an amplifying circuit 4 which amplifies the latch output signal 3a, a transformer 5 which passes the AC component of the output signal of the amplifying circuit 4, and a rectifying circuit 6 which rectifies its output. A switch 8 is placed in opening/closing operation with the DC voltage 6 outputted from the rectifying circuit 6 to control the driving of the controlled system 9. The output signal (2a and 2b) of the logical operation means 2 and the output signal 10a of the oscillator are inputted to an AND gate 31, and a frequency monitor means 32 monitors the frequency of the output signal of the AND gate 32 and feeds a latch decision signal as its monitor result back to the AND gate 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fail-safe circuit for operating a controlled object to a safe side when a failure occurs and a safety protection device using the fail-safe circuit, and more particularly to maintaining the state when the safe side is operated. The present invention relates to a fail-safe circuit and a safety protection device that are suitable for operating.

[0002]

2. Description of the Related Art Fail-safe circuits have been applied to various fields including railways. As an example thereof, there is a "fail-safe load control device using a microcomputer" described in JP-A-60-229102.

In this prior art, as long as a pulse signal of relatively low frequency is output from the microcomputer,
The oscillator that outputs a high-frequency signal is controlled to continue operating. Therefore, if the pulse signal which is the output of the microcomputer is stopped and the output signal is stuck at a logic "1" or "0", the output of the oscillator is stopped. When the output of the oscillator is a pulse signal, a DC voltage rectified by the rectifier circuit and the smoothing circuit is obtained via the pulse transformer. If the control circuit is configured to drive the load by this DC voltage and operate the load on the safe side by the disappearance of the DC voltage, the above DC voltage will be obtained when the microcomputer fails and the output of its pulse signal stops. The load will operate safely. The pulse output from this prior art microcomputer is not directly input to the oscillator, but is input via a filter having a constant time constant.

[0004]

The above-mentioned conventional technique is
A filter is provided between the output of the microcomputer and the input of the oscillator. Therefore, there is a problem that the response of the entire system is delayed by the time constant of the filter.

Further, in the safety protection device, even if the signal from the sensor exceeds the predetermined value and the state in which the controlled object should be operated to the safe side occurs even once, even if the signal from the sensor returns to the predetermined value or less, It is necessary to have a function to keep the controlled object operating safely until the reset operation is entered. Therefore, it is required to provide the latch means. In order to achieve fail-safe, it is effective to adopt a method of controlling a controlled object using a pulse signal as in the conventional technique. However, when the pulse signal is input to the safety protection device having the latch means, the latch means operates due to the logic "1" or the logic "0" of the pulse signal, and the control target is operated to the safe side. There is a problem that the controlled object is operated without being held.

An object of the present invention is to provide a fail-safe circuit which has a fast control response and can continue its operation when the controlled object is operated to the safe side, and a safety protection device using the fail-safe circuit. It is in.

[0007]

The above object is to provide a latch means for monitoring the frequency or cycle of an input alternating signal or an AC signal and continuing to stop the output of the input signal when it deviates from a reference value, This is achieved by driving the controlled object with the output of this latch means.

[0008]

In the present invention, normally, the input signal of the latch means is output as it is, and when the controlled object is driven, the alternating signal or the AC signal becomes DC and the frequency or period deviates from the reference value. Can be latched, and fail-safe property can be secured.

Further, since the latch means is configured to output the input signal as it is as the output signal, the output of the latch means also becomes the DC signal at the moment when the input signal becomes the DC signal, and then the frequency or Since the output is latched according to the result of monitoring the cycle, the latch function for the controlled object operation can be secured and the high speed operation at the time of driving the controlled object becomes possible.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a fail-safe type safety protection device according to an embodiment of the present invention. This safety protection device includes sensors S1 to SN for detecting the state of a plant, comparison and determination means 1 for determining whether or not output signals from the sensors S1 to SN exceed a predetermined value, and outputs from the comparison and determination means 1. Logic operation means 2 for performing logic processing of the signal, and latch means 3 for maintaining the output of this signal when the trip signal for operating the controlled object 9 to the safe side is output from the logic operation means 2. , An oscillator 10 that outputs an alternating signal 10a
And a latch output signal 3a which is an output signal of the latch means 3.
Amplifier circuit 4 for amplifying the voltage, transformer 5, and rectifier circuit 6
And a switch 8 which is provided between the power source 7 and the controlled object 9 and which is opened and closed by the output of the clearing circuit 6.

The transformer 5 propagates only the AC component signal of the output signal of the amplifier 4 to the rectifier circuit 6 and cuts the DC component. The rectifier circuit 6 rectifies an input AC component signal to generate a DC voltage 6 a and outputs the DC voltage 6 a to the switch 8. The switch 8 controls the power supply from the power source 7 to the controlled object 9 by its opening / closing function, and controls the driving of the controlled object 9. In FIG. 1, a solenoid valve is shown as an example of the controlled object 9. This solenoid valve comprises an exciting coil 91 and a valve 92. The controlled object 9 is normally excited by the closing operation of the switch 8, but when the voltage of the power supply 7 is lost, the open failure of the switch 8 occurs, or the latch means fails (stops the output of the alternating signal). The so-called fail-safe configuration is provided in which the excitation is released and the protective operation is performed.

The operation of each unit will be described below with reference to FIG. The sensors S1 to SN measure major parameters and equipment states of the plant. For example, assume that the output signal of the sensor S1 exceeds the reference level in the period from time t1 to t2, as shown in FIG. 2 (i). . The comparison means 1 includes sensors S1 to SN.
Judgment whether the output signal from exceeds the reference level,
When the reference level is exceeded, a signal (first trip signal: not shown) for operating the controlled object 9 to the safe side (opening the switch 8 to release the excitation of the solenoid valve) It outputs to the logical operation means 2. The logical operation means 2 is
Although not shown, a majority decision process is performed on the output signal from the other comparison means 1 which is redundant, and each sensor S1 to S
The trip signal 2a (second trip signal) is obtained by performing the logical sum processing of the output signals from the comparison means 1 output for each N.
Is output. In this case, since the output signal of the sensor S1 exceeds the reference level during the period t1 to t2, the comparison means 1 outputs a signal (first trip signal) to that effect, and the logical operation means 2 displays As shown in 2 (ii), a trip signal 2a for operating the controlled object 9 on the safe side.
(Logic “0” signal) is output.

The logical operation means 2 has a self-diagnosis function, and outputs an abnormality detection signal 2b of logic "0" at the time of abnormality, and at the time of normality, as shown in FIG. 2 (iii), logic "1".
And outputs the abnormality detection signal 2b. When the abnormality detection signal 2b is logical "0", that is, when the logical operation means 2 is abnormal, a fail-safe operation is performed to ensure the safety protection function. As shown in FIG. 2 (iv), the oscillator 10 is an alternating signal (rectangular wave signal) that repeats logic "1" and logic "0" in a constant cycle.
Is continuously output.

When the controlled object 9 is set to the protection operation mode, it is necessary to output the logic "0" from the latch means 3 and to output the alternating signal from the latch means 3 in the normal mode. For this purpose, the latch means 3 performs signal monitoring, latches the alternating signal of the input signals, and latches the alternating signal.
The situation in which the controlled object 9 is operated to the safe side while the signal is output from the above (the situation in which the signals 2a and 2b are "0")
When the error occurs, the output of the latch means 3 is immediately set to the logic "0". In this embodiment, the following measures are taken so that the fail-safe property and the high-speed responsiveness are compatible by devising the signal monitoring method. In other words, it is not always required to secure high-speed response with respect to the fail-safe property itself. Therefore, as shown in FIG. 1, the output signals 2a and 2b of the logic operation means 2 and the output signal of the oscillator 10 are 10a is input to the AND gate 31 and the frequency monitoring means 32 monitors whether the output signal of the AND gate 31 is an alternating signal, and the latch determination signal 32a which is the monitoring result is fed back to the AND gate 31. It is configured.

The frequency monitoring means 32 monitors the frequency of the output signal of the AND gate 31 and, as shown in FIG. 2 (vi), if the frequency is within a predetermined value, a logic "1" is output to the latch determination signal 32a.
Is output, and if it deviates from a predetermined value, a logical "0" is output. When the frequency monitoring means 32 outputs the logic "0", the AND gate 31 always outputs the latch output signal 3a of the logic "0" regardless of the logic values of other input signals. Since the frequency of the latch output signal 3a of logic "0" deviates from the above-mentioned predetermined frequency, the frequency monitoring means 3
The output of 2 remains the logic "0", and the latch means 3 continues to output the latch output signal 3a of the logic "0". Even if the trip signal 2a becomes logic "0", the output of the latch means 3 immediately becomes logic "0", but after a delay of a period T until the deviation of the frequency is detected, the latch means 3
Latch operation is completed. As a result, even if the signal of the sensor S1 returns to the reference level or less at time t2 and the trip signal 2a from the logical operation means 2 becomes logic "1" again, the latch output signal 3a output from the latch means 3 becomes logic. The state of "0" is held. As a result, the DC voltage 6a, which is the output of the rectifier circuit 6, is a predetermined voltage V1 (v) until time t1, as shown in FIG. 2 (vii), becomes 0v after time t1, and the switch 8 is opened. It becomes a state. However, as shown in FIG. 2 (viii), even if the trip signal 2a becomes "1" at time t2, the controlled object 9 will continue the protection operation mode.

The frequency monitoring means 32 of FIG. 1 is composed of a well-known retriggerable monostate multivibrator, and comprises a basic circuit A, a resistor R, and a capacitor C. This retriggerable monostate multivibrator outputs a pulse signal for a predetermined period T when a single input pulse is applied, for example, as shown in FIG. 3, but the pulse signal is input again within this predetermined period T. Then, a pulse is output from that time to the period T. Therefore, if a pulse is input in a cycle shorter than the period T, the
As described above, the logic "1" is continuously output, and the logic "0" is output after the period T from the time when the pulse is not input. Here, this period T is determined based on the time constant of the resistor R and the capacitor C, and may be determined in advance so that it has a value longer than the cycle of the alternating signal.

With such a configuration, when the trip signal 2a becomes logic "0", the latch determination signal 32a becomes logic "0" after the period T, and the latch operation of the latch means 3 is completed. This period T corresponds to the delay time T shown in FIG. In this way, the frequency is monitored by monitoring the cycle of the alternating signal. This is because the period is expressed as the reciprocal of the frequency.

As described above, since the latch operation is completed with a delay of the period T, even if the input of the latch means 3 temporarily becomes the logic "0" due to the external electric noise, the period T becomes.
If it is restored within the range, the latch function does not work and there is a great effect that it is excellent in noise immunity. This effect can also be applied to other embodiments described below.

As the frequency monitoring means 32, a PLL for detecting the frequency can be applied as it is. P
Regarding LL, there are various books, but for example, "Basics and Applications of PLL" published by Tokyo Denki University Press (March 15, 1978, 1st edition, 1st edition) can be used as a reference. . When the PLL is applied as the frequency monitoring means 32, a logic "1" is output as the latch determination signal 32a when the latch output signal 3a is within a predetermined frequency range, and a logic "1" is output when the frequency exceeds the predetermined frequency range. Output "0".
In Figure 4.1 on page 98 of the above book, the latch output signal 3a is input to the input terminal and the latch judgment signal 32
will output a.

Further, the frequency monitoring means 32 may be realized by an integrating circuit as shown in FIG. This configuration is also a system for monitoring the cycle, and has a resistor R and a capacitor C.
When the period of the alternating signal becomes longer than the time constant due to
The output of the frequency monitoring means 32, which is an integrating circuit, is a logical "0".
Then, the latch function of the latch circuit operates.

As described above, according to the embodiment of the present invention,
When the trip signal 2a from the logical operation means 2 becomes a logic "0", the latch output signal 3a of the latch means 3 can be immediately made a logic "0", and the latch function of the latch means 3 is operated after a predetermined period T. Therefore, it is possible to secure the original latch function of the latch means and to realize the fail-safe property that can satisfy the high-speed responsiveness during the operation of the controlled object.

In FIG. 1, the trip signal 2a, the abnormality detection signal 2b, and the latch output signal 3a are set to the logic "0" to perform the fail-safe operation. However, when these signals become the logic "1", the fail-safe operation is performed. When operating, the AND gate 31 is changed to an OR gate, and the frequency monitoring means 32 outputs a logic "0" during normal operation, and when the controlled object is operated to the safe side, that is, the frequency of the latch output signal is a predetermined value. When it deviates from the above, it may be configured to output the logic "1". This idea is the same in other embodiments.

FIG. 6 shows another embodiment of the latch means 3. The latch means 3 is different from that of FIG. 1 in that the frequency monitoring means 35 is provided in the feedforward portion.
The feature is that a flip-flop 34 is provided so that the latch function is activated. The frequency monitoring means 35 may be the same as that of FIG. 1 or other means described above. The operation of the latch means 3 will be described with reference to FIG.

As in the case of FIG. 1, assuming that the output signal of the sensor S1 is as shown in FIG. 7 (i), the trip signal 2a input to the main latch means 3 is as shown in FIG. 7 (ii). Like Also in this case, the abnormality detection signal 2b is set to the logic "1" (the logic operation means 2 is normal) as shown in FIG. 7 (iii). As shown in Fig. 7 (iv), alternating signal (square wave signal)
As 10a, pulses with a constant cycle are continuously output. The output signal of the AND gate 36 is as shown in FIG.
In the period t1 to t2, the output of the alternating signal becomes a stopped signal. As a result, the latch determination means 35 determines that the frequency deviates from the reference value after the period T has elapsed from the time t1 and outputs the latch determination signal 3a of logical "0".

When the trip signal 2a returns to logic "1" at time t2, the latch determination signal 35a becomes logic "1" again after the period T from time t2. However, since the flip-flop 34 outputs the logic "0" and continues the output when the latch determination signal 35a changes from the logic "1" to the logic "0" even once, the signal shown in FIG. Is output. As a result, the latch output signal 3a, which is the output of the AND gate 33, becomes a logic "0" even after the time t2 as shown in FIG. 7 (viii), and the controlled object 9 becomes as shown in FIG. 7 (ix). The protection operation mode is retained.

As described above, also in this embodiment, both the high speed response operation and the fail safe operation can be achieved. further,
According to this embodiment, as shown in FIG.
By inputting b to the AND gate 332 and operating the flip-flop 34 with the output signal of this AND gate, when the abnormality detection signal 2b becomes logical "0", that is, the logical operation means 2 When it becomes abnormal, the latch function can be operated immediately, and the fail-safe property against the abnormality of the logical operation means 2 can be enhanced. If the logical operation unit 2 becomes abnormal even once, the reliability of the subsequent operation is low and there is a possibility that the function of the protection operation may not be fulfilled during the protection operation, but this can be prevented in advance.

In the above-described embodiment, the logic operation means 2 and the comparison means 1 are constituted by hardware logic. However, the functions of the logic operation means 2, the logic operation means 2 and the comparison means 1 are
It can also be realized by software of a microprocessor. Moreover, instead of the oscillator 10 shown in FIG.
It is also possible to output the alternating signal directly from the microprocessor by software processing of the microprocessor.

FIG. 9 shows the comparison means 1 and the logical operation means 2 as one.
7 is a flowchart showing a processing procedure when the device is configured by one microprocessor. The process shown in FIG. 9 is periodically executed. First, in STEP 1, the sensor S
It is judged whether the output signals of 1 to SN are within the reference level, and Y
If ES, go to STEP2, if NO, STEP
Proceed to 6. In STEP 2, the variable i is incremented. This is because in the case of YES in STEP 1, that is, when the controlled object 9 is in the normal mode, the microprocessor outputs an alternating signal of a predetermined cycle as described later. In STEP 3, if the variable i is an odd number, STE
Proceed to P4, and if not odd, proceed to STEP5. Since the initial value of the variable i is zero, i in STEP2 is "1", and the process proceeds to STEP4. As a result, the microcomputer outputs a signal of logic "0" in STEP4. This completes the first processing. If the result of STEP1 is YES in the second processing, STEP2
Proceed to. Since the variable i is counted up here, the variable i becomes "2". As a result, the determination result in STEP3 is NO, and the process proceeds to STEP5. In STEP 5, a signal of logic "1" is output from the microprocessor. Similarly, this process is repeated as long as the outputs of the sensors S1 to SN are within the reference level. However, since this process is periodically executed, the microprocessor outputs S
An alternating signal is output by alternately executing TEPs 4 and 5.

When the output signals of the sensors S1 to SN exceed the reference level, the determination result of STEP1 becomes NO and STE
The process proceeds to P6, where a signal of logic "0" is output. While the output signals of the sensors S1 to SN exceed the reference level,
The process proceeds from STEP1 to STEP6, and the signal of logic "0" is continuously output from the microprocessor.

Therefore, the alternating signal is normally output,
When the controlled object 9 should be operated on the safe side, a signal of logic "0" is output. In this embodiment, the oscillator 10 of FIG. 1 is unnecessary, and the signal input of the alternating signal 10a in FIGS. 1, 6 and 8 is unnecessary. In this embodiment, the trip signal 2a in the "1" state itself is an alternating signal during normal operation, and becomes a logical "0" signal when the controlled object 9 should be operated safely. The abnormality detection signal 2b is output as a result of the self-diagnosis function of the microcomputer (for example, watchdog timer error detection, parity error detection, etc.).

As described above, according to this embodiment, the alternating signal and the signal for operating the controlled object on the safe side are directly output by the software processing of the microcomputer.
The oscillator 10 is unnecessary, and a system configuration with higher reliability can be provided.

FIG. 10 is a diagram showing the configuration of the latch means when the signal output from the oscillator 10 of FIG. 1 is an AC signal. The latch means 3'includes an AND gate 38, a switch 37 for outputting and stopping the input AC signal 10a 'based on the output signal of the AND gate 38, and a latch output signal 3a' output from the switch 37. It comprises frequency monitoring means 39 for monitoring the frequency. Frequency monitoring means 39
When the frequency or cycle of the latch output signal 3a 'deviates from a predetermined value, the switch 37 is opened to stop the output of the AC signal from the latch means 3'.

According to this embodiment, as in the case of FIG. 2, when the output signal of the sensor S1 exceeds the reference level from time t1 to t2 as shown in FIG. 11 (i), the trip signal 2a changes to the level shown in FIG. (i
As in i), it is "0" between times t1 and t2, and is "1" at other times. As a result, the output signal of the AND gate 38 becomes a logic "0". Therefore, the switch 37 is opened, and the latch means 3'cannot output the AC signal as shown in FIG. 11 (v). The frequency monitoring means 39 is time t1.
Since the latch output signal 3a 'becomes zero, the signal of logic "0" is output after the period T from then. Then, even if the trip signal 2b returns to the logic "0" at the time t2, the latch determination signal 3a 'is held at the logic "0", and when the controlled object 9 starts the protection operation at the time t1, it is maintained. It

FIG. 12 is a view showing another embodiment of the latch means 3'of FIG. This embodiment corresponds to FIG. 6, but is largely different in that an AC signal 10a 'is input. The function of this latch means 3'is the same as in FIG.
The AND gate 312 controls opening / closing of the switch 310, but when the output of the AND gate 312 is logic "1", the switch 310 is closed. Therefore, FIG. 13 (ii), (iii)
If the trip signal 2a becomes the logic "0" only during the period between the times t1 and t2 and the abnormality detection signal 2b is the logic "1", the output signal of the switch 310 is as shown in FIG. 13 (v). Then, the output of the AC signal 10a 'is stopped only during the period of t1 and t2.

The frequency monitoring means 39 has a period T from time t1.
After a lapse of time, it is determined that the frequency (or cycle) of the output signal of the AND gate 310 has deviated from a predetermined value, and FIG.
As in i), a signal of logic "0" is output. This output signal causes the flip-flop 34 to operate, and FIG. 13 (vii)
, The signal of logic "0" is continuously output. As a result,
The switch 37 is in the open state after the output of the flip-flop 34 becomes logic "0", and the latch output signal 3
As shown in FIG. 13 (viii), a ′ continues to be zero after time t1. Therefore, when the controlled object 9 enters the protection operation mode at time t1, it continues to maintain this mode thereafter.

As described above, by monitoring the frequency (or cycle) of the AC signal and operating the latch means when the frequency deviates from a predetermined value, both the high speed operation and the fail-safe property of the controlled object are satisfied. It becomes possible.

[0037]

According to the present invention, normally, the input signal of the latch means is output as it is, and when the output of the latch means becomes a DC signal for driving the controlled object to the safe side, this DC signal output Since it latches, fail-safe property can be secured.

Further, since the latch means is configured to output the input signal as it is, the output of the latch means also becomes the DC signal at the moment when the input signal becomes the DC signal,
After that, the output is latched according to the monitoring result of the frequency or the period, so that the high speed operation at the time of driving the controlled object can be achieved.

That is, in the device having the latch function for the controlled object operation, high-speed response at the controlled object operation,
It is possible to achieve both the fail-safety of the device, including the latching means.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a safety protection device according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of each part of the safety protection device shown in FIG.

FIG. 3 is a diagram showing an output result for a single pulse input of a retriggerable monostate multivibrator.

FIG. 4 is a diagram showing an output result for a continuous pulse input of the retriggerable monostate multivibrator.

FIG. 5 is a diagram showing an example in which the frequency monitoring means is composed of an integrating circuit.

FIG. 6 is a view showing another embodiment of the latch means.

FIG. 7 is a diagram showing an operation of the latch means shown in FIG.

FIG. 8 is a diagram showing an embodiment of a latch means with improved fail-safety with respect to an abnormality detection signal.

FIG. 9 is a flowchart showing a processing procedure when the logic operation means is configured by software of a microprocessor.

10 is a diagram showing a configuration example of latch means when an output signal from the oscillator shown in FIG. 1 is an AC signal.

11 is a diagram showing an operation of the latch means shown in FIG.

12 is a diagram showing another embodiment of the latch means shown in FIG.

13 is a diagram showing an operation of the latch means shown in FIG.

[Explanation of symbols]

2 ... Logical operation means, 3, 3 '... Latch means, 32a, 35
a, 39a ... Latch determination signal, 3a ... Latch output signal, 3
2, 35, 39 ... Frequency monitoring means, 5 ... Transformer, 6 ... Rectifier circuit, 6a ... DC voltage, 11 ... Rectifier circuit, 9 ... Control object, 10 ... Oscillator, 10a ... Alternate signal, 10a '... AC signal.

Claims (14)

[Claims] 1. A fail-safe circuit for driving a controlled object using an alternating signal or an AC signal as an input signal,
A frequency monitoring means for inputting the input signal and monitoring the frequency of the input signal is provided, and when the frequency is within the reference range, the input signal is output as it is and when the frequency deviates from the reference range. A fail-safe circuit comprising latch means for stopping the subsequent output of the input signal. 2. A fail-safe circuit for driving a controlled object using an alternating signal or an AC signal as an input signal,
A fail-safe circuit for driving a controlled object, comprising latch means for stopping the output of the input signal when the frequency of the input signal deviates from the reference range even once. 3. An apparatus for controlling on / off of a controlled object by an output signal of a signal processing apparatus, wherein when an output signal of the signal processing apparatus and an alternating signal from an oscillator are inputted to operate the controlled object, A fail safe circuit provided with a latch means for stopping the output of the alternating signal when the output of the alternating signal is in a mode in which the frequency of the alternating signal deviates from a predetermined value. 4. The latch means according to claim 3, further comprising means for inputting an abnormality detection signal output as a self-diagnosis result of the signal processing device. When the abnormality detection signal is input, the alternating signal is output. Fail-safe circuit characterized by continuing to stop. 5. A fail-safe circuit that drives an object to be controlled by using an AC signal as an input signal, continues to output a predetermined logic signal when the frequency of the input signal deviates from a reference range, and the output signal A fail-safe circuit characterized in that the output of an input signal is cut off by a switching means. 6. A fail-safe circuit that drives an object to be controlled by using an alternating signal as an input signal, and continues to output a predetermined logic signal when the frequency of the input signal deviates from a reference range. A fail safe circuit comprising means for stopping the output of the input signal by a logic circuit. 7. The fail-safe circuit according to claim 1, wherein the frequency monitoring means is a PLL circuit or an integrating circuit,
Alternatively, a fail-safe circuit characterized by being a retriggerable monostate multivibrator. 8. A signal processing device which continues to output a drive signal for operating a controlled object even when an output signal from a sensor deviates from a reference value even once, and when the drive signal is input, stops outputting an alternating signal. A fail-safe circuit comprising a means for operating the controlled object when the alternating signal from this means stops. 9. A plurality of sensors and a comparison means for outputting a first trip signal for operating the controlled object when the output signals from these sensors exceed a reference value are provided for each sensor. Calculating means for inputting a first trip signal from the means to perform a calculation process for operating the controlled object, and an oscillator when a second trip signal for operating the controlled object output from the calculating means is input Latch means for continuing to stop the output of the alternating signal from the latch means, the latch means comprising means for continuing to stop the output of the alternating signal even when the frequency of the alternating signal deviates from a reference value. A transformer for inputting an output signal, a rectifying means for rectifying the output signal of the transformer, and a switching element for controlling the operation of a controlled object by a DC voltage output from the rectifying means are provided. Safety protection device characterized by 10. A plurality of sensors and a comparison means for outputting a first trip signal for operating a controlled object when the output signals from these sensors exceed a reference value are provided for each sensor. Arithmetic means for inputting a first trip signal from the means to perform arithmetic processing for operating the controlled object, and the arithmetic means outputs a second trip signal when operating the controlled object, When not operating, it is equipped with means for outputting an alternating signal, inputs the output signal of the arithmetic means, monitors the frequency of the alternating signal, and outputs the alternating signal when this frequency deviates from the reference value. A transformer that includes latch means that continues to stop, a transformer that inputs the output signal of the latch means, a rectifying means that rectifies the output signal of the transformer, and an operation to be controlled by a DC voltage that is the output of the rectifying means. A safety protection device having a switching element for controlling the. 11. The fail according to claim 1, wherein the frequency monitoring means determines whether or not the frequency of the input signal deviates from the reference range by monitoring the cycle of the input signal. Safe circuit. 12. The latch means according to claim 9 or 10, wherein the latch means determines whether or not the frequency of the input signal deviates from a reference value by monitoring the cycle of the input signal. Safety protection device. 13. A logic means for outputting one signal of a binary signal in a normal state and the other signal in an abnormal state, an oscillating means for outputting the binary alternating signal, and an alternating signal within a predetermined period. When inputting, the frequency monitoring means for outputting the one signal, and the output of the logic means, the output of the oscillating means and the output of the frequency monitoring means are logically ANDed to obtain the logical product signal as the frequency monitoring means. And a rectifying means for extracting and rectifying an AC component from the output of the ANDing means, and a switching means for controlling the opening and closing of the connection between the power source and the controlled object by the output of the ANDing means. Fail-safe circuit. 14. A logic means for outputting an AC signal or an alternating signal in a normal state and a DC signal in an abnormal state, and a frequency for outputting one of the signals when an AC signal or an alternating signal within a predetermined period is input. Monitoring means, a logical product means for taking a logical product of the output of the logical means and the output of the frequency monitoring means and outputting the logical product signal to the frequency monitoring means, and an AC component is extracted from the output of the logical product means for rectification A fail-safe circuit comprising: a switching means for controlling the opening and closing of the connection between the power source and the controlled object by the output of the switching means.