JPH03147002A - Majority logic circuit - Google Patents

Majority logic circuit

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Publication number
JPH03147002A
JPH03147002A JP28300889A JP28300889A JPH03147002A JP H03147002 A JPH03147002 A JP H03147002A JP 28300889 A JP28300889 A JP 28300889A JP 28300889 A JP28300889 A JP 28300889A JP H03147002 A JPH03147002 A JP H03147002A
Authority
JP
Japan
Prior art keywords
output
outputs
alternating signal
input
alternating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28300889A
Other languages
Japanese (ja)
Inventor
Eiichi Toyoda
瑛一 豊田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP28300889A priority Critical patent/JPH03147002A/en
Publication of JPH03147002A publication Critical patent/JPH03147002A/en
Pending legal-status Critical Current

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  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To output alternating signals as output when there are alternating signals in more than two systems by combining the outputs for triple systems in a comparison part when a real speed and an allowable speed are compared so as to adopt majority logic. CONSTITUTION:Speed checking parts 1-3 comparing the real speed with the allowable speed are constituted in such a way that they output the alternating signals at the time of detecting a safety-side, and a direct current at the time of detecting a danger-side. When the outputs are inputted to majority logic 4 and when there are the alternating signals of more than two systems, the alternating signals are outputted and only an alternating component is amplified by an AC amplifier 5, Ryo is driven and Ryo is picked up by signifying that it detects the safety-side as the triple system. Pulse generation circuits detecting 41, 42 and 43 detect the edge of the change of an input signal and generate pulses, and they generate pulse strings (d)-(f) when there are input signals (a)-(c).

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は自動列車制御装置にかかわり、特に、多重系出
力を1つにまとめる論理構成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic train control system, and particularly to a logical configuration method for combining multiple system outputs into one.

〔従来の技術〕[Conventional technology]

自動列車制御装置は先行列車の位置に関係して定まる列
車の許容速度信号を地上より、車上に伝達し、車上では
列車の実速度を検出し、上記の許容速度信号と比較し実
速度が許容速度を越えると自動的にブレーキを出力する
システムである。車上の装置は上記のように許容速度と
実速度を比較しているが、安全のための3重系構成され
ているものが多い、これら3重系の出力を一つにまとめ
るため従来は、各県の出力を継電器出力とし、第4図に
示すように2つ以上の系が出力に最終出力が一致するよ
う構成されている。これは、全体の構成は3重系が基本
となっているがこの最終出力を出す部分のみは一重系に
なってしまうため、継電器の故障モードの発生率の非対
称性を利用し。
The automatic train control device transmits the train's permissible speed signal, which is determined in relation to the position of the preceding train, from the ground to the onboard train.The onboard system detects the train's actual speed, compares it with the above permissible speed signal, and determines the actual speed. This system automatically applies the brakes when the speed exceeds the allowable speed. The on-board device compares the allowable speed and the actual speed as described above, but most of them have a triple system configuration for safety. , the output of each prefecture is used as the relay output, and as shown in FIG. 4, two or more systems are configured so that the output coincides with the final output. This is because although the overall configuration is basically a triple system, only the part that outputs the final output is a single system, so we take advantage of the asymmetry in the incidence of relay failure modes.

最終出力部分をフェイルセーフ化しているものである。The final output part is made fail-safe.

しかし、非対称性の大きい継電器は復帰バネ力の大きい
ものでなくてはならず、したがって励磁コイルなども大
きい物にならざるを得ないため超小形継電器は使用でき
ず、ある程度の大きさのものにならざるを得ない。
However, a relay with large asymmetry must have a large return spring force, and therefore the excitation coil must also be large, so ultra-small relays cannot be used, and a relay of a certain size is required. I have no choice but to do so.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記のように従来技術では外形2重量等大きいものにな
らざるを得ない。
As mentioned above, the conventional technology inevitably results in a large size and weight.

本発明は、この最終出力部分を電子回路化し、かつフェ
イルセーフ性の高い構成法を提供するものである。
The present invention provides a configuration method in which this final output portion is made into an electronic circuit and has a high fail-safe property.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、許容速度と実速度を比較す
る部分、すなわち速度照査部の出力を従来の様に継電器
出力とせず、安全側すなわち実速度が許容速度以下の場
合、ディジタルのON。
In order to achieve the above purpose, the part that compares the allowable speed and the actual speed, that is, the output of the speed checking section, is not used as a relay output as in the conventional case, but on the safe side, that is, when the actual speed is less than the allowable speed, the output is digitally turned ON.

OFF値を繰返す交番信号、危険側の場合すなわち、実
速度が許容速度を越える場合は直流すなわちディジタル
のON又はOFFの一部レベルとなるよう定義づけ出力
させ、これらの出力3重系分を組合わせ、2系以上に交
番信号がある場合、出力として交番信号が出力されるよ
うにしたものである。
In the dangerous case of an alternating signal that repeats an OFF value, that is, when the actual speed exceeds the allowable speed, it is defined and output as a partial level of DC, that is, digital ON or OFF, and these output triple system components are assembled. In addition, if there is an alternating signal in two or more systems, the alternating signal is output as an output.

〔作用〕[Effect]

電子回路の場合、故障が発生すると、内部の素子等スイ
ッチングが不能となり出力が特定のレベルに固定される
場合が多いため上記のように交番信号が出る時安全側出
力とする事により故障モードの発生率の非対象性は大き
く、高いフェイルセーフ性が確保できる。
In the case of electronic circuits, when a failure occurs, switching of internal elements becomes impossible and the output is often fixed at a specific level. Therefore, by setting the output to the safe side when an alternating signal is generated as described above, the failure mode can be avoided. The occurrence rate is highly asymmetric, and high fail-safety can be ensured.

〔実施例〕〔Example〕

第1図に本発明になる自動列車制御装置のブロック図を
示す0図に示すように実速度と許容速度の比較を行う速
度照査部1〜3からは前述したように安全側を検出して
いる時交番信号、危険側を検出している時、直流の出力
を行うように構成されている。
FIG. 1 shows a block diagram of the automatic train control system according to the present invention.As shown in FIG. It is configured to output an alternating signal when the sensor is detected, and output a DC signal when detecting a dangerous situation.

これらの出力が、多数決論理4に入力され、2系以上交
番信号がある時は交番信号が出力されこの交流成分のみ
が交流増幅器5により増幅されRyoを駆動し、3重系
として安全側の検出をしているという意味でRy oを
ピックアップする構成とする。
These outputs are input to the majority logic 4, and when there is an alternating signal from two or more systems, an alternating signal is output, and only this alternating current component is amplified by the AC amplifier 5 to drive Ryo, resulting in safe detection as a triple system. The configuration is such that it picks up Ryo in the sense that it is doing so.

第2図に第1図4に示す本発明になる多数決論理を示す
。また、第3図に第2図番部の動作波形を示す。
FIG. 2 shows the majority logic according to the present invention shown in FIG. 1. Further, FIG. 3 shows the operating waveforms of the numbered part in the second figure.

第2図の41.42.43は入力信号の変化のエツジを
検出しパルスを発生するパルス発生回路であり第3図a
−cのような入力信号がある時d〜fのようなパルス列
を発生する。これらパルス列は、論理和回路44〜46
により2系分のパルス列の合せたものが生成され第3図
g = iのパルス列とされる。これらのパルス列は、
エツジトリガタイプのラッチ回路47,48.49によ
り構成される交番信号伝達回路のトリガ入力に入力され
る。一方この交番信号の最初のデータ入力端子には、速
度照査部(1)〜(3)が発生する第1の交番信号より
も1/2以上周波数の低い第2の交番信号が入力しであ
る。したがって47〜49のトリガ端子にパルスがある
時のみ第2の交番信号が後段に伝送される。
41, 42, and 43 in Figure 2 are pulse generation circuits that detect edges of changes in the input signal and generate pulses, and Figure 3a
When there is an input signal like -c, pulse trains like d to f are generated. These pulse trains are processed by OR circuits 44 to 46
Thus, a combination of two systems of pulse trains is generated, and the pulse train of g=i in FIG. 3 is generated. These pulse trains are
The signal is input to a trigger input of an alternating signal transmission circuit constituted by edge trigger type latch circuits 47, 48, and 49. On the other hand, a second alternating signal whose frequency is more than half lower than that of the first alternating signal generated by the speed verification units (1) to (3) is input to the first data input terminal of this alternating signal. . Therefore, the second alternating signal is transmitted to the subsequent stage only when there is a pulse at the trigger terminals 47-49.

第3図に示す様に各速度照査部の出力は2系ずつが1つ
のトリガ端子の系に入っているので、2系以上が交番信
号を出力すれば、47〜49のラッチ回路は入力の第2
の交番信号が最終段の出力まで伝達されて、最終出力に
交番信号を出力できる。
As shown in Figure 3, two systems of the outputs of each speed checking section are connected to one trigger terminal system, so if two or more systems output an alternating signal, the latch circuits 47 to 49 will be connected to the input signal. Second
The alternating signal is transmitted to the output of the final stage, and the alternating signal can be output as the final output.

これが出力されれば第1図の交流増幅器に交番信号が入
力され出力のRyoが駆動される。
When this signal is output, an alternating signal is input to the AC amplifier shown in FIG. 1, and the output Ryo is driven.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明した様に構成されているので構成回路
の一部が機能を停止すると、出力の交番信号が出力でき
ない方向に作用し、入出力の短絡のような故障が発生し
ないかぎり速度照査部が2系以上直流出力をしていると
き交番出力を最終出力に出力する事はない。
Since the present invention is constructed as described above, if a part of the constituent circuits stops functioning, the output alternating signal acts in a direction that makes it impossible to output, and unless a failure such as a short circuit between the input and output occurs, the speed check will continue. When two or more systems are outputting DC output, the alternating output will not be output as the final output.

すなわち故障の場合でも誤って交番信号が出力される事
がなくフェイルセーフ性が容易に保てる。
In other words, even in the event of a failure, no alternating signal is erroneously output, and fail-safe properties can be easily maintained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の自動列車制御装置のブロッ
ク図、第2図は本発明になるフェイルセフ多数決論理回
路図、第3図はフェイルセーフ多数決論理回路の動作説
明図、第4図は従来の多数決論理を用いた自動列車制御
装置のブロック図を示す。 1.2.3・・・速度照査部、4・・・多数決論理部、
5・・・交流増幅部、41,42.43・・・パルス発
生回路、44,45.46・・・論理和回路。 第 因 萬 2
Fig. 1 is a block diagram of an automatic train control device according to an embodiment of the present invention, Fig. 2 is a fail-safe majority logic circuit diagram of the present invention, Fig. 3 is an operation explanatory diagram of the fail-safe majority logic circuit, and Fig. 4 shows a block diagram of an automatic train control device using conventional majority logic. 1.2.3...Speed check section, 4...Majority logic section,
5... AC amplifier section, 41, 42.43... Pulse generation circuit, 44, 45.46... OR circuit. No. 2

Claims (1)

【特許請求の範囲】[Claims] 1、制御の対象の状態を監視し、定められた状態以上に
対象の状態が危険状態側になつた事を検出し安全側にあ
る場合には出力に交番信号を出力し、危険側にある場合
は直流の一定レベルの論理値を出力する第一の検出器と
、これと同機能の第二、第三の検出器と、前記第一から
第三検出器の各出力を入力して、各々の入力に対し交番
信号が入力される時は、その変化エッジを検出し、パル
スを各々出力するパルス発生回路と、前記交番信号の周
波数の1/2以下の周波数の交番周波数を入力とし、エ
ッジトリガタイプのラッチ回路を複数段直列に接続した
交番信号伝達回路と、このラッチ回路のトリガ端子に上
記パルス発生回路を組合せ入力し前記交番信号伝達回路
の出力に交番信号がある時のみ安全側を検出していると
して出力することを特徴とする多数決論理回路。
1. Monitors the state of the object to be controlled, detects when the state of the object has become dangerous beyond a predetermined state, and outputs an alternating signal to the output if it is on the safe side. In this case, input the first detector that outputs a logic value of a certain level of DC, the second and third detectors that have the same function, and the outputs of the first to third detectors, When an alternating signal is input to each input, a pulse generating circuit detects the changing edge thereof and outputs a pulse, and an alternating frequency having a frequency of 1/2 or less of the frequency of the alternating signal is input, A combination of an alternating signal transmission circuit in which multiple stages of edge trigger type latch circuits are connected in series and the above-mentioned pulse generation circuit are input to the trigger terminal of this latch circuit, and the safe side is achieved only when there is an alternating signal at the output of the alternating signal transmission circuit. A majority logic circuit that outputs an output indicating that it has detected.
JP28300889A 1989-11-01 1989-11-01 Majority logic circuit Pending JPH03147002A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28300889A JPH03147002A (en) 1989-11-01 1989-11-01 Majority logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28300889A JPH03147002A (en) 1989-11-01 1989-11-01 Majority logic circuit

Publications (1)

Publication Number Publication Date
JPH03147002A true JPH03147002A (en) 1991-06-24

Family

ID=17660033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28300889A Pending JPH03147002A (en) 1989-11-01 1989-11-01 Majority logic circuit

Country Status (1)

Country Link
JP (1) JPH03147002A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06217606A (en) * 1993-01-25 1994-08-09 Marunaka Seisakusho:Kk Irrigator for turf
WO2000005630A1 (en) * 1998-07-23 2000-02-03 Hitachi, Ltd. Fail-safe controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06217606A (en) * 1993-01-25 1994-08-09 Marunaka Seisakusho:Kk Irrigator for turf
WO2000005630A1 (en) * 1998-07-23 2000-02-03 Hitachi, Ltd. Fail-safe controller

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