JPH0865136A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE: To make the operation of the circuit stable by using a logic circuit to apply logic arithmetic operation to an input signal and outputting an output signal corresponding to the result of arithmetic operation from a control means to avoid the oscillation of the logic circuit with power consumption saving at a high speed. CONSTITUTION: Different threshold voltages are set to an input signal Vin to avoid loop operation at an input voltage between both the threshold voltages. Thus, the oscillation on the circuit operation is avoided independently of a change state of the input voltage. Furthermore, drive transistors(TRs) Q7, Q17 are operated in a different timing and the flowing of a through-current is prevented by avoiding simultaneous turn-on state. Thus, a low threshold voltage logic circuit 6 and a high threshold voltage logic circuit 7 with small power consumption are obtained. Furthermore, TRs with less ON-resistance are adopted for TRs Q8, Q18, to set an output logic level to be sufficiently closer to a power supply voltage and a defect of the TRs with a large capacitance whose on- resistance tends to be increased usually is corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit and a semiconductor integrated circuit device using the logic circuit, and more particularly to a semiconductor logic circuit and a semiconductor integrated circuit device having an output section of CMOS structure.

In recent years, with the increase in scale and integration of LSIs, semiconductor integrated circuits, which are one of the main constituent elements of LSIs, are required to have greater driving capability and higher speed. In order to meet this demand, a circuit configuration which has low power consumption and can maintain high driving capability and high speed has been devised and realized.

[0003]

2. Description of the Related Art FIG. 6 is a diagram showing an example of a conventional logic circuit which can satisfy such a requirement. In this example, the input signal V
A buffer circuit that outputs a signal V _out having the same phase as _in ,
The buffer circuit comprises an even number of inverter stages, eg two stages of CMOS inverter gates in the example shown.

The input signal V _in is inverted by the CMOS inverter gate 30 in the input stage, and the inverted output (expressed as “V _inx ” for convenience) drives the CMOS inverter gate 32 in the output stage.

Output stage CMOS inverter gate 32
Is p between the high potential side power supply V _CC and the low potential side power supply V _SS.
Channel transistor (hereinafter abbreviated as "pMOS") 3
2a and n-channel MOS transistors (hereinafter "nMO"
Abbreviated as "S". ) 32b is connected in series.

When V _inx is L level, pMOS32
When a is turned on, the load capacitance (parasitic capacitance of wiring, gate capacitance of the next stage, etc.) C _L is charged (ia represents a charging current),
When V _{in x} is at H level, the nMOS 32b is turned on to discharge the load capacitance C _L (ib represents a discharge current).

In order to achieve greater driving capability and higher speed, it is sufficient to increase the size of the pMOS 32a and the nMOS 32b between the CMOS inverters in the output stage. By doing this, the drive currents ia and ib become large,
A large load capacity C _L can be charged and discharged without any trouble, and the charging speed can be increased.

[0008]

However, in order to increase the speed in the above-mentioned conventional logic circuit, the transistor size of the output stage is simply increased, so that there is an effect of improving the driving capability and the high speed, but the power saving is achieved. In terms of sex, it was insufficient, and there were technical issues to be improved.

Since the CMOS inverter gate generally turns on only one of the pMOS and the nMOS as long as the potential of the input signal is constant at the H level or the L level, power is supplied only for charging / discharging the load capacitance C _L. It is said that the power consumption is extremely low. However, during the transition period of the logic level of the input signal, the potential of the input signal is almost V _CC / 2.
When it is near the level (however, V _SS = 0 [V]), both pMOS and nMOS are turned on, and V _CC →
Since a so-called through current (current ic in FIG. 6) flows between V _SS , simply increasing the sizes of the pMOS and nMOS increases the through current ic corresponding to the increase in the transistor size. There is a drawback that the increase in consumption cannot be prevented.

As one idea for solving this problem, depending on the logic state of the output signal, the pMOS or nMOS of the output stage
It is conceivable that the circuit is configured so that only one of them is driven so that a through current does not flow. However, due to the large scale of integrated circuits in recent years, the current to be supplied to the load has increased,
Since the time during which the output voltage has a transient potential that does not reach the stable level immediately increases, there is a risk that the output potential may be erroneously detected.

For example, as shown in FIG. 7, in the circuit elements in the logic circuit, variations often occur between the highest input threshold and the lowest input threshold. At this time, if the input voltage changes more slowly than expected, oscillation sometimes occurs because the input threshold levels to which each logic circuit responds are different. This is a problem caused by forming a closed loop of detecting the logic state of the output signal and controlling the output signal.

Therefore, an object of the present invention is to provide a semiconductor logic circuit which suppresses power consumption, has a larger driving capability and higher speed, and operates stably regardless of the state of an input signal. .

[0013]

According to the first aspect of the present invention,
A logic circuit that performs a logical operation on the input signal, an output means that drives the output signal based on the result of the logical operation output by the logic circuit under the control of the control means, and a logic level of the input signal is the first threshold value. When the voltage is lower than the voltage or higher than the second threshold voltage which is set higher than the first threshold voltage, the detecting means outputs the detection signal, and the output means is driven when the detection signal is detected. And a control means.

According to a second aspect of the present invention, there is provided a logic circuit for performing a logical operation on the input signal, and an output means for supplying an output signal based on the operation logic of the logic circuit, and the output is based on the logic of the output signal. It has a circuit configuration that pulls up or pulls down the signal, and makes the threshold value of the logic circuit different during pull-up operation and pull-down operation, and prohibits the pull-up operation or pull-down operation of the output means between both threshold values. It is characterized by doing so.

FIG. 1 shows the configuration of the invention according to claim 3. As shown in FIG. 1, the invention according to claim 3 performs the same logical operation as that of the low threshold logic circuit 6 having the first threshold value and the low threshold logic circuit 6 and the first threshold value. High threshold logic circuit 7 having a second threshold value higher than the threshold value, first switch means 3 interposed between the high potential side power supply 1 and the output terminal 2, the output terminal 2 and the low The second switch means 5 interposed between the power supply 4 on the potential side and the third switch which has a larger on-resistance than the first switch means 3 and is connected in parallel to the first switch means 3. Means 12 and a second
The ON resistance is larger than that of the switch means 5 and the second
The fourth switch means 13 connected in parallel to the switch means 5 and the operation logic of the low threshold logic circuit 6 or the high threshold logic circuit 7 causes the signal level of the output signal to be the first threshold value. When the value is below or equal to or higher than the second threshold value, the loop cutting means 11 for supplying the output signal to the detecting means 10, and the detecting means 10 for latching the output signal supplied by the loop cutting means 11 and outputting the detection signal, When the operation logic of the threshold logic circuit 6 is different from the logic of the output signal and the logic of the output signal is high level, the first switch means 3 is driven, and the operation logic of the low threshold logic circuit 6 and the output signal. Are the same and the logic of the output signal is at a low level, the first control means 8 for driving the third switch means 12 and the operation logic of the high threshold logic circuit 7 are different from the logic of the output signal. , And the logic of the output signal When the logic level of the high threshold logic circuit 7 is equal to the logic of the output signal and the logic of the output signal is high level, the fourth switch means 13 is driven by driving the second switch means 5 at the low level. And second driving means 9 for driving.

According to a fourth aspect of the present invention, in the logic circuit according to the third aspect, the low threshold logic circuit generates the gate area of the transistor on the low potential side larger than the gate area of the transistor on the high potential side. Is configured to have the first threshold value lower than the intermediate potential between the potential of the high potential side power source and the potential of the low potential side power source, the high threshold logic circuit is By generating the gate area larger than the gate area of the low potential side transistor, the second threshold value higher than the intermediate potential between the high potential side power source potential and the low potential side power source potential is provided. Composed.

According to a fifth aspect of the invention, in the logic circuits according to the first to fourth aspects, each of the logic circuits is composed of a CMOS transistor.

[0018]

According to the first aspect of the invention, the logic circuit performs a logical operation on the input signal, and the output signal outputs the output signal corresponding to the result of the logical operation under the control of the control means.
The detection signal monitors the logic level of the input signal, and when the logic level of the input signal is lower than the first threshold voltage or higher than the first threshold voltage, the second threshold voltage is set. When it is higher, the detection signal is output to the control means.
The control means drives the output means based on the operation result of the logic circuit when the detection signal is detected, and outputs the output signal.

According to the second aspect of the invention, the circuit configuration for pulling up or pulling down supplies a small current to the output signal to stabilize the output signal. Since the threshold value of the logic circuit is made different during the pull-up operation and the pull-down operation, it is possible to detect a circuit that pulls up or pulls down between the threshold values where the input voltage is not stable. Therefore, the voltage of the input signal is detected, and the pull-up or pull-down operation of the output means is prohibited between the two threshold values.

According to the third aspect of the invention, the low threshold logic circuit 6 has a low first threshold voltage. The high threshold logic circuit 7 is a logic circuit that performs substantially the same logical operation as the low threshold logic circuit 6, but only the threshold value is higher than the first threshold value.

The loop disconnecting means 11 has the signal level of the input signal equal to or lower than the first threshold value or the second threshold value based on the operation logic of the low threshold logic circuit 6 or the high threshold logic circuit 7. In the above case, the output signal is sent to the first control means 8 and the second
To the control means 9. The first control means 8 is different from the logic of the output signal to which the operation logic of the low threshold logic circuit 6 is supplied and the logic of the output signal is at the high level.
The switch means 3 is driven. Also, the first control means 8
Is the third when the operation logic of the low threshold logic circuit 6 is equal to the logic of the output signal and the logic of the output signal is low level.
The switch means 12 is driven. The second control means 9
The second switch means 5 is driven when the operation logic of the high threshold value logic circuit 7 is different from the logic of the supplied output signal and the logic of the output signal is at a low level. Further, the second control means 9 drives the fourth switch means 13 when the operation logic of the high threshold logic circuit 7 is equal to the logic of the output signal and the logic of the output signal is at the high level.

According to the fourth aspect of the present invention, the low threshold logic circuit generates the gate area of the transistor on the low potential side larger than the gate area of the transistor on the high potential side, so that the intermediate voltage between both power supply voltages is generated. The high-threshold logic circuit is configured to have a first threshold value lower than the potential, and the high-threshold logic circuit generates the gate area of the transistor on the high-potential side wider than the gate area of the transistor on the low-potential side, so To have a second threshold value higher than the intermediate potential of.

According to the invention described in claim 5, in the logic circuit according to any one of claims 1 to 4, each logic circuit is a CM.
Since it is composed of the OS transistor, the threshold value can be easily set, and it is applied to the logic circuit of the CMOS process.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the logic circuit of the present invention will be described with reference to the drawings. (I) First Embodiment FIG. 2 shows the circuit configuration of the logic circuit according to the first embodiment of the present invention. The circuit shown in FIG. 2 will be described in comparison with FIG. 1. In the logic circuit of the first embodiment, the transistors Q ₁ and Q ₂ that form a low level logic circuit and the transistor Q ₃ that forms the first control means. To Q ₆ , the transistor Q ₇ as the first switch means, and the transistor Q ₈ as the third switch means perform pull-up operation and supply of high-potential-side power. Further, the transistors Q ₁₁ and Q ₁₂ which form the high level logic circuit, the transistors Q _{13 to} Q ₁₆ which form the second control means, the transistor Q ₁₇ which is the second switch means, and the fourth switch means. And the transistor Q ₁₈ which is a pull-down operation supplies the low-potential-side power supply. Further, the logic circuit comprises transistors Q ₉ and Q ₁₉ which are loop breaking means, and inverter gates 15 and 16 which are detecting means. In the following description, the high-potential side power source is V _CC and the low-potential side power source is GND.
Level.

Next, the operation will be described with reference to the timing chart of FIG. The logic circuit of the first embodiment constitutes an inverter circuit. The input signal V _in has a short rise time and a short fall time unless the connected load is heavy, and due to the transient potential of the input signal V _in ,
Other logic circuits do not malfunction. However, when the number of inputs connected to one output terminal, so-called fan-out, is large, the amount of current to be supplied is large, and V _in shown _in FIG.
As described above, the time during which the transient potential is present increases at the time of rising and falling. The logic circuit of this embodiment prohibits the operation of the internal circuit _in the transient state of the input signal V _in .

Transistors Q ₁ and Q ₂ and Q ₁₁ and Q ₁₂
Acts as an original logic circuit (inverter gate).
Here, in a semiconductor integrated circuit such as a CMOS, a large current capacity (referred to as “large size”) CMOS can be generated by increasing a contact area of a gate when integrated on a substrate. P with the same current capacity, that is, with the same size
When the MOS and the nMOS are connected in series between the high potential side power source V _CC and the low potential side power source V _SS , the threshold of the input voltage becomes the intermediate potential ((V _CC −V _SS / 2 = V _CC / 2)). However, if a CMOS with a small current capacity, that is, a CMOS with a small size and a CMOS with a large size are combined, the threshold of the input voltage is C with a large size.
Deviates to the MOS side. In other words, the threshold of the logic circuit can be set arbitrarily by adjusting the gate area of the transistors forming the logic circuit.

[0027] In the transistor Q ₁ and the transistor Q ₂ is, are configured so that the people of the size of the transistor Q ₂ increases. Also, transistor Q ₁ and transistor Q
₂ is configured so that the size of the transistor Q ₂ is larger. Therefore, the transistors Q ₁ and Q
_The inverter composed of ₂ has a threshold V _thL lower than the intermediate potential, and the inverter _composed of the transistors Q ₁₁ and Q ₁₂ has a threshold V _thH higher than the intermediate potential.

In the initial state, the H level which is the opposite logic of the input signal V _in is the output signal V _out . When the input signal V _in is at L level, the transistor Q ₉ to which this inverted signal is supplied is turned on and the transistor Q ₁₉ is turned off. Serving control signal, by the operation of inverters 15 and 16 which form a latch circuit, the output signal V _{ou t}
Inversion logic of L level. Control signal is first
It functions to enable / disable the operations of the control means 8 and the second control means. When the control signal is at L level, the transistor Q ₁₅ is turned on, so that the second control means 9 can operate. Since the transistor Q ₅ is off, the first control means 8 is in a resting state, while the transistor Q ₆ is on and pulls up the gate electrode of the transistor Q ₇ . Further, since the transistor Q ₈ is turned on, the output signal V _out is pulled up to the high potential side power source V _CC . Input signal V _in is from L level to H level Now, consider a case where the input signal V _in slowly changes from L level to H level as shown in FIG. Initially, the operating state of the circuit does not change until the threshold V _thL of the inverter gates of the transistors Q ₁ and Q ₂ .

At time t _A , when the threshold V _thL of the transistors Q ₁ and Q ₂ is exceeded, the output () logic of this inverter is inverted by the operation of the inverter and becomes L level. The transistor Q ₉ is turned off by this output, and the inverters 15 and 16 are connected from the output terminal 2.
The loop feeding back to the first and second control means via is cut off. In other words, the inverter 15 that works as a latch circuit
And 16 maintain the control state when V _{th L} is reached and then do not change until the transistors Q ₉ and Q ₁₉ are turned on and the loop is closed.

Time t_BAt the input signal V_inIs Trang
Jista Q₁₁And Q₁₂Inverter gate threshold
Field V_thHOver. The output of this inverter is inverted
Becomes L level. Transistor Q₁₉This inverter
It is turned on by the output of the gate, and the output signal V_outBut
Input to the latch circuits 15 and 16 and output signal V_outof
The level is monitored. On the other hand, the second control means 9
Since the control line is at the H level,
Q₁₇Transistor Q to the gate terminal of₁₅→ Q₁₃Sutra
Current is supplied for this reason. Therefore, connect it to the output terminal 2.
Transistor Q from the external load₁₇Via charge
Discharge starts. Transistor Q₇And Q ₁₇Has a current capacity
Since it is large, it is suitable for charging and discharging large currents. This discharge is negative
When the amount of charge accumulated in the load is large Transistor Q₁₇of
The time constant element due to the on-resistance works, and it takes time to complete the discharge.
Takes.

When the voltage of the output signal V _out decreases with discharge and exceeds a predetermined potential, for example, an intermediate potential between V _{CC and} V _SS (= V _CC / 2), the level of the output signal V _out is monitored. The threshold potential of the latch circuit composed of the inverters 15 and 16 (for example, (V _CC −V _SS ) /
2 = _Vcc / 2 vicinity), the logic of the control signal is inverted. When the logic of the control signal is inverted, the operating state of the first control means 8 and the operating state of the second control means 9 change. That is, the pull-up operation of the transistor Q ₆ is stopped and the pull-down operation of the transistor Q ₁₆ is started in response to the control signal becoming the H level. Further, since the transistor Q ₅ is turned on, the operation of the first control means 8 starts. Since the transistor Q ₁₅ is turned off,
The operation of the second control means 9 is stopped. Transistor Q ₁₇
Completely stops the discharging operation by the pull-down operation of the transistor Q ₁₆ . Since the transistor Q ₁₈ is turned on, the output terminal is pulled down to stabilize the output signal V _out at the L level. On the other hand, the first control circuit 8 inverts the logic of the inverter output composed of the transistors Q ₁ and Q ₂ and outputs the H level. Transistors Q ₇ and Q ₈ are off. The operation when the input signal V _in changes from the H level to the L level and the input signal V _in slowly changes from the H level to the L level will be described.

At time t _C , the input signal V _in reaches the threshold V _thH of the inverter composed of the transistors Q ₁₁ and Q ₁₂ . This inverter has an input signal V _in
Is inverted and the output logic is set to H level. In response to this output, the transistor Q _{19 as} a loop disconnection means is turned off, and the latch circuit composed of the inverters 15 and 16 is turned on until either the transistor Q ₉ or Q ₁₉ becomes conductive next time.
The state of the control signal at the time of V _thH is maintained.

At time t _D , the input signal V _in reaches the threshold V _thL of the inverter composed of the transistors Q ₁ and Q ₂ . This inverter sets the output to H level. In response to this, the transistor Q ₉ becomes conductive, and the latch circuit composed of the inverters 15 and 16 monitors the level of the output signal V _out . Further, since the first control means 8 is in an operating state, the output of the inverter composed of the transistors Q ₁ and Q ₂ is inverted in the control line, and the gate terminal of the transistor Q ₇ is connected via the transistor Q ₄ → transistor Q _5. It becomes the L level and the transistor Q ₇
Turns on. The large-capacity transistor Q ₇ supplies current from the output terminal to an external load.

The voltage of the output signal V _out starts to rise from the L level with the accumulation of charges in the external load, and reaches a predetermined potential,
For example, beyond an intermediate potential between _{V CC -V SS (= V CC} / 2), threshold sucrose hold the potential of the latch circuit comprised of the inverters 15 and 16 monitors the level of the output signal V _out (e.g., ( Since V _CC -V _SS ) / 2) is exceeded, the logic of the control signal is inverted again. When the logic of the control signal is inverted and becomes L level, the pull-down operation of the transistor Q ₁₆ is stopped and the pull-down operation of the transistor Q ₆ is started. Further, the transistor Q ₁₅ is turned on and the operation of the second control means 9 is started, and the transistor Q ₅ is turned off and the operation of the first control means 8 is stopped. The transistor Q ₇ is completely turned off by the pull-up operation of the transistor Q ₆ . Since the transistor Q ₈ is turned on, the output terminal 2 is pulled up and the output signal V
Stabilize _out at H level. The second control circuit 9 inverts the logic of the inverter output composed of the transistors Q ₁₁ and Q ₁₂ , and becomes an L level output. Transistor Q ₁₇ and Q ₁₈ are turned off.

As can be seen from the above operation, the first embodiment
According to the input signal V_inAgainst different thresholds
Threshold by setting the threshold voltage.
Loop operation does not occur at an intermediate input voltage between voltages.
Yes. Therefore, the circuit operation is not affected by the change of the input voltage.
It does not oscillate. In addition, Q which is a drive transistor
₇And Q₁₇Operate at different timings and are on at the same time
Therefore, it is possible to prevent through current from flowing.
Therefore, a suitable logic circuit with low power consumption can be provided. Well
Transistor Q₈And Q₁₈Tiger with low on-resistance
If you use a transistor, you can set the output logic level to the power supply voltage.
Can be close to each other and the on-resistance usually tends to increase.
Can compensate for the drawbacks of high-capacity large-capacity transistors
It (Ii)Second embodiment The logic circuit of the second embodiment of the present invention is applied to the first embodiment.
The above circuit is further applied to a NAND gate.

FIG. 4 shows the circuit configuration of the logic circuit of the second embodiment.
Show. The logic circuit shown in FIG. 4 is compared with the principle diagram shown in FIG.
The logic circuit of the second embodiment has a low threshold value.
And a NAND gate 21 having a
Transistor Q_{twenty one}~ Q _{twenty four}And the first to drive the load
Transistor Q which is the switch means of_{twenty five}And output signal V
_outAs a third switch means to pull up
Star Q₂₆And, by pull-up operation, high potential side power supply
Supply. In addition, the threshold value higher than the NAND gate
Comprising the NAND gate 22 having the second control means 9
Transistor Q₃₁~ Q₃₄And the second to discharge the load
Transistor Q which is the switch means of₃₅And output signal V
_outIs the fourth switch means for pulling down
Star Q₃₆With, pull-down operation, low potential side power supply
Supply. Further, the logic circuit has a loop cutting means.
Barrel transistor Q₂₇And Q₃₇And the latch circuit
And inverters 17 and 18 as detecting means.

FIG. 5 shows a circuit example of a NAND gate used in the second embodiment. FIG. 5A shows a low threshold NAND2.
1B is a circuit diagram of the high threshold NAND 22. FIG. Low threshold NAND21 is constituted by transistors Q ₄₁ to Q _44, high threshold NAND22 is constituted by the transistors Q ₅₁ to Q _54.

Next, the operation will be described. The operations of the first control means, the second control means, and the first to fourth switch means have exactly the same circuit configuration as that of the first embodiment, and the operation is also exactly the same.

As shown in FIG. 5A, the low threshold NA
In ND21, transistor Q ₄₁And Q₄₄Tran
The transistor size is small and the transistor Q₄₂And Q₄₃To
The size of the transistor is large. Therefore, the input signal V_inA
Is transistor Q₄₁And Q₄₂Sresshi to reverse the logic of
Hold is an intermediate potential ((V_CC-V_SS) /
2 = V_CCLower than / 2). Also, the input signal V_inBIs
Langista Q₄₃To switch the on / off state
The threshold potential is also lower than the intermediate potential between the power supply potentials.
Both threshold voltages adjust transistor area
And set them so that they have almost the same potential.

Similarly, the high threshold value shown in FIG.
In the NAND22, the threshold voltage of each transistor
The fields are set up in opposite relations. In other words,
Transistor Q₅₁And Q₅₄Transistor size is large
Transistor Q₅₂And Q ₅₃Transistor size is
small. Therefore, the input signal V_inAIs transistor Q ₅₁
And Q₅₂The threshold that inverts the logic of
Intermediate potential ((V _CC-V_SS) / 2 = V_CCFrom / 2)
High, input signal V_inBIs transistor Q₅₃ON state
・ Power supply for threshold potential to switch off state
Higher than the intermediate potential between the potentials. Both threshold voltage
The voltage adjusts the area of the transistor and becomes almost the same potential
To set.

N for adjusting this threshold voltage
The AND circuit has two inputs, but like the input stage inverter of the first embodiment, when the voltage level of either the input signal V _inA or V _inB reaches its adjusted threshold potential. , The output is changed according to the input logic at that time. For example, in the low threshold NAND 21, the output signal is set to the L level when both input signals exceed the low threshold V _thL, and the output signal is set to the H level when at least one of the both input signals is V _thL. And

The operation of this embodiment can be considered similar to the operation of the first embodiment. In other words, the output of the low threshold NAND21 is directly replaced by the signals of FIGS. 2 and 3, and the output of the high threshold NAND22 is directly replaced by the signals of FIG. 2 and FIG. Can be followed as in the first embodiment. Also, the transistor Q
Turning on and off of ₉ and Q _{19 corresponds} to turning on and off of transistors Q ₂₇ and Q ₃₇ . Turning on / off of the transistors Q ₆ and Q ₁₆ corresponds to the transistors Q ₂₄ and ₃₄ .

[0043] In the NAND circuit, the logic becomes the L-level when both input signals V _inA and V _inB exceeds a threshold sucrose hold V _thL low level NAND 21,
The transistor Q ₂₇ is turned off and the control state at that time is maintained. Then, both the input signals V _inA and V _inB are at the threshold V _{th H of the} high level NAND 22.
, The logic of becomes L level, the transistor Q ₃₇ is turned on, and the transistor Q ₃₅ discharges the electric charge accumulated in the load corresponding to the output of the second control means 9. The output voltage V _out is a predetermined threshold value (for example,
When the intermediate potential between both power supply potentials falls below V _CC / 2), the control signal is inverted and the second control means 9 is deactivated,
The first control means 8 is put into operation. At the same time, since the transistor Q ₂₄ is turned on, the transistor Q ₂₅ is completely turned off. The transistor Q ₃₆ is turned on, the output signal V _out is a pull-down state.

_Either the input signal V _inA or V _inB is the threshold V of the high level NAND 22.
_{When it becomes} lower than _thH , the logic of becomes H level, the transistor Q ₃₇ is turned off, and the latch circuit including the inverters 17 and 18 remains in the latched state.
Further, when either one of the input signals V _inA or V _{inB falls} below the threshold V _thH of the high level NAND 22, the logic also becomes H level, the transistor Q ₂₇ is turned on and the first control means. Transistor Q ₂₅ supplies current to the load corresponding to the output of 8.
When the output voltage V _out exceeds a predetermined threshold value (for example, an intermediate potential between both power supply potentials = V _CC / 2), the control signal is inverted and the first control means 8 is deactivated, The control means 9 is put into operation. At the same time, since the transistor Q ₃₄ is turned on, the transistor Q ₃₅ is completely turned off. Also, the transistor Q ₂₆ is turned on,
The output signal V _out is pulled up.

As described above, according to the second embodiment, it is possible to maintain the internal state at the input signal level of the input unstable of the present invention for the NAND gate by making the threshold value different, thus saving power. It is possible to provide a logic circuit that performs stable operation. Modifications of Other Embodiments Not limited to the above-described embodiments of the present invention, various modifications are possible.

For example, in the above embodiment, the output of the logic circuit
The loop cutting means and the detecting means were driven based on
However, these loop disconnection means and detection means use the input signal V_inTo
Direct input and two thresholds V_thHAnd V
_thLMay be detected. In this case, logical times
It is no longer necessary to change the threshold of the
Change the threshold of the transistor, which is the breaking means.
To change. For example, the transistor Q of the first embodiment₉Lower
A transistor having a threshold value, and a transistor Q ₁₉To
Similar operation with a transistor with high threshold
Is performed.

Further, although the inverter gate and the NAND gate are disclosed, the logic circuit may be another one. For example, a transistor configuration can be divided into a high-potential side power source and a low-potential side power source such as a NOR gate, and the threshold itself of the gate for arithmetic operation of the input stage can be changed only by the area ratio of the transistors. The present invention can be applied if it is one. Other Mode (1) A logic circuit that performs a logical operation of an input signal and an output unit that drives an output signal based on the arithmetic logic of the logic circuit are provided, and the logic circuit has two different threshold values. A logic circuit comprising two logic sections, wherein a current supply operation to the load of the output means or a discharge operation from the load is prohibited between the two threshold values. (2) A logic circuit that performs a logical operation on an input signal, an output means that drives an output signal based on the arithmetic logic of the logic circuit, and an output signal that is supplied to a detection means according to a change in the input signal. Loop disconnecting means, a detecting means for detecting the logic of the output signal supplied from the loop disconnecting means, and a control means for controlling the output means, the loop disconnecting means having two different threshold values. A logic circuit having a threshold value, and prohibiting the supply operation of the output signal of the detecting means between both threshold values.

[0048]

According to the first aspect of the present invention, since the threshold values of different input signals are set and detected, it is possible to prohibit the change of the circuit operation state in the case of unstable logic state input. Therefore, a logic circuit that performs stable circuit operation can be provided.

According to the second aspect of the present invention, since the pull-up operation or the pull-down operation is prohibited between the threshold values of the input voltage, the load due to the pull-up operation / pull-down operation is applied only to a stable input signal level. Charging and discharging are performed, and stable operation enables power saving of the logic circuit.

According to the third aspect of the invention, the threshold values are made different in the two logic circuits, the indefinite region of the input signal is detected, and the output signal is fed back only in the stable region of the input signal. With this configuration, stable current supply / discharge and pull-up / pull-down operations can be performed without oscillation due to the feedback loop.

According to the fourth aspect of the invention, by changing the gate area of the transistor, the threshold value of the logic circuit formed by combining the transistors having different gate areas can be changed, and the input stage of the logic circuit can be changed. A logic circuit suitable for use in

According to the fifth aspect of the invention, since each logic circuit is composed of a CMOS transistor, the threshold value can be easily adjusted by adjusting the gate area, and a monolithic IC is integrated on one chip. Suitable for manufacturing the logic circuit.

[Brief description of drawings]

FIG. 1 is a principle diagram of a logic circuit of the present invention.

FIG. 2 is a circuit diagram of a logic circuit according to a first embodiment of the present invention.

FIG. 3 is a timing chart of a logic circuit.

FIG. 4 is a circuit diagram of a logic circuit according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a NAND gate according to a second embodiment,
(A) is a low threshold NAND, (B) is a high threshold NA
It is ND.

FIG. 6 is an explanatory diagram of an operation of a conventional logic circuit.

FIG. 7 is an explanatory diagram of a problem that occurs in a logic circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... High potential side power supply 2 ... Output terminal 3 ... 1st switch means 4 ... Low potential side power supply 5 ... 2nd switch means 6 ... Low threshold logic circuit 7 ... High threshold logic circuit 8 ... 1st Control means 9 ... second control means 10 ... detection means 11 ... loop disconnection means 12 ... third switch means 13 ... fourth switch means 15-18 ... inverter gate 21 ... low threshold NAND 22 ... higher Threshold NAND 30 ... Input side inverter gate 32 ... Output side inverter gate V _CC ... High potential side power source potential V _SS ... Low potential side power source potential Q _{1 to} Q ₉ , Q _{11 to} Q ₁₉ , Q _{21 to} Q ₂₇ , Q _{31 to} Q ₃₇ , Q
_{41 ~Q 44, Q 51 ~Q 54} ... CMOS transistor

Claims (5)

[Claims] 1. A logic circuit for performing a logical operation on an input signal, an output means for driving an output signal based on the result of the logical operation output by the logic circuit under the control of a control means, and a logic level for the input signal. Is lower than a first threshold voltage or higher than a second threshold voltage that is set higher than the first threshold voltage, a detection unit that outputs a detection signal, and the detection signal is detected. And a control means for driving the output means when the semiconductor logic circuit is operated. 2. A logic circuit for performing a logical operation of an input signal, and output means for supplying an output signal based on the operational logic of the logical circuit, wherein the output signal is pulled based on the logic of the output signal. And a pull-up operation or a pull-down operation of the output means between the two thresholds, the threshold value of the logic circuit is made different between the pull-up operation and the pull-down operation. The semiconductor logic circuit is characterized by being prohibited. 3. A low-threshold logic circuit having a first threshold, and performing the same logical operation as the low-threshold logic circuit,
High threshold logic circuit having a second threshold value higher than the threshold value, first switch means interposed between the high potential side power supply and the output terminal, the output terminal and the low potential Second switch means interposed between the side power source, and third switch means having an ON resistance larger than that of the first switch means and connected in parallel to the first switch means, Fourth switch means having a larger on-resistance than the second switch means and connected in parallel to the second switch means, and operation of the low threshold logic circuit or the high threshold logic circuit Loop disconnecting means for supplying the output signal to the detecting means when the signal level of the output signal is below the first threshold value or above the second threshold value based on logic; The level of the output signal And a detecting means for outputting a switch detection signal, and driving the first switch means when the operation logic of the low threshold logic circuit is different from the logic of the output signal and the logic of the output signal is high level. However, when the operation logic of the low threshold logic circuit and the logic of the output signal are equal and the logic of the output signal is at a low level, the first control means for driving the third switch means, and the high control means When the operation logic of the threshold logic circuit is different from the logic of the output signal and the logic of the output signal is at a low level, the second switch means is driven to operate as the operation logic of the high threshold logic circuit. A second driving means for driving the fourth switch means when the logics of the output signals are equal and the logics of the output signals are at a high level, and a semiconductor logic circuit. 4. The logic circuit according to claim 3, wherein the low-threshold logic circuit generates a gate area of a low-potential-side transistor larger than a gate area of a high-potential-side transistor, thereby increasing the high-potential-side transistor. The high threshold logic circuit is configured to have the first threshold value lower than an intermediate potential between the potential of the power source and the potential of the low potential side power source, And a second threshold value higher than an intermediate potential between the potential of the high-potential side power source and the potential of the low-potential side power source. Characteristic semiconductor logic circuit. 5. The semiconductor logic circuit according to claim 1, wherein each logic circuit is composed of a CMOS transistor.