JP7438037B2 - charge pump device - Google Patents

Description

The present invention relates to a charge pump device.

Patent Documents 1 to 3 describe charge pump type boosting devices. For example, in Patent Document 1, a booster circuit has switching transistors TR1 to TR4 (paragraph 0004), transistor TR2 is an N-channel field effect transistor (N-channel FET), and transistors TR1, TR3, and TR4 are P-channel transistors. It is a field effect transistor (P-channel FET) (paragraph 0006). The same applies to Patent Documents 2 and 3 (see FIG. 1 of Patent Document 2, FIG. 1 of Patent Document 3, etc.).
[Prior art documents]
[Patent document]
[Patent Document 1] JP-A-6-351229 [Patent Document 2] JP-A-2008-283794 [Patent Document 3] JP-A-2011-30327

Since the on-resistance of the P-channel FET is higher than that of the N-channel FET of the same size, the P-channel FET must be larger in size than the N-channel FET in order to flow the same amount of current.

In a first aspect of the invention, a charge pump device is provided. The charge pump device may include a charge pump booster circuit that outputs a boosted voltage obtained by boosting an input voltage input from an input terminal. The charge pump device may include an output circuit that outputs the boosted voltage as an output voltage. The charge pump device may include a comparison circuit that compares the input voltage and the output voltage. The charge pump device includes a switching circuit that switches between the input voltage and the output voltage to generate a control signal for controlling at least one semiconductor switch in the charge pump booster circuit, depending on the comparison result. It's fine.

The switching circuit may use the higher of the input voltage and the output voltage to generate the control signal.

The switching circuit may output either the input voltage or the output voltage depending on the comparison result. The charge pump device may further include a drive circuit that generates a control signal using the voltage output by the switching circuit.

The at least one semiconductor switch may be an N-type MOSFET. The drive circuit may generate a control signal that turns on at least one semiconductor switch using the voltage output by the switching circuit.

The charge pump booster circuit may include a first capacitor. The charge pump booster circuit may include a positive side charging switch that is a semiconductor switch connected between the input terminal and one end of the first capacitor. The charge pump booster circuit may include a negative side charging switch that is a semiconductor switch connected between the other end of the first capacitor and ground. The charge pump booster circuit may include a negative side transfer switch that is a semiconductor switch connected between the input terminal and the other terminal of the first capacitor. The drive circuit may supply a control signal generated using the voltage output by the switching circuit to at least one control terminal of the positive side charging switch or the negative side transfer switch.

The output circuit may include a positive transfer switch that is a semiconductor switch that switches whether or not to output the boosted voltage as an output voltage. The charge pump device may further include a gate control circuit that boosts the control signal for the positive side transfer switch and supplies it to the control terminal of the positive side transfer switch when outputting the boosted voltage as the output voltage.

The gate control circuit may charge the offset voltage using the input voltage during at least part of the off period of the positive transfer switch. When turning on the positive transfer switch, the gate control circuit may add an offset voltage to the voltage of the control signal for the positive transfer switch and supply the voltage to the control terminal of the positive transfer switch.

In a second aspect of the invention, a charge pump device is provided. The charge pump device may include a charge pump booster circuit that outputs a boosted voltage obtained by boosting an input voltage input from an input terminal. The charge pump device may include an output circuit including a positive transfer switch that switches whether or not to output the boosted voltage as an output voltage. The charge pump device charges the offset voltage using the input voltage during at least part of the off period of the positive transfer switch, and when the positive transfer switch is turned on, the voltage of the control signal for the positive transfer switch is increased. A gate control circuit may be provided that applies an offset voltage and supplies it to the control terminal of the positive transfer switch.

The gate control circuit may include a second capacitor, one end of which receives a control signal for the positive transfer switch, and the other end of which is connected to a control terminal of the positive transfer switch. The gate control circuit may include a rectifying element that is connected between the input terminal and the other end of the second capacitor and prevents current from flowing backward from the other end of the second capacitor to the input terminal.

The positive transfer switch may be an N-type MOSFET.

The charge pump device may include a current limiting circuit that limits at least one of the current input to the charge pump booster circuit or the current output from the charge pump booster circuit in response to the output voltage being lower than the input voltage.

Note that the above summary of the invention does not list all the necessary features of the invention. Furthermore, subcombinations of these features may also constitute inventions.

1 shows a configuration of a charge pump device 100 according to this embodiment. 5 is a timing chart showing an example of the operation of the charge pump device 100 according to the present embodiment. The configuration of a switching circuit 160 according to this embodiment is shown. The configuration of a drive circuit 165 according to this embodiment is shown. 5 is a timing chart showing an example of the operation of the drive circuit 165 according to the present embodiment. The configuration of a gate control circuit 170 according to this embodiment is shown. 5 is a timing chart showing an example of the operation of the gate control circuit 170 according to the present embodiment. The configuration of current limiting circuits 140a to 140c according to this embodiment is shown. The configuration of a gate control circuit 900 according to a first modification of the present embodiment is shown. The configuration of a gate control circuit 1000 according to a second modified example of this embodiment is shown. The configuration of a gate control circuit 1100 according to a third modification of the present embodiment is shown. The configuration of a gate control circuit 1200 according to a fourth modification of the present embodiment is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential to the solution of the invention.

FIG. 1 shows the configuration of a charge pump device 100 according to this embodiment. The charge pump device 100 according to the present embodiment is configured such that the positive side charging switch 120, the negative side transfer switch 135, and the positive side transfer switch 150 in the charge pump device 100 can be N-type. generates an appropriate control voltage to be supplied to the control terminal (gate terminal) of the

The charge pump device 100 includes a charge pump booster circuit 110, an output circuit 145, a comparison circuit 155, a switching circuit 160, a drive circuit 165, and a gate control circuit 170. The charge pump booster circuit 110 charges the first capacitor 115 with the input voltage VDD input from the input terminal VDD in the charging phase, and boosts the input voltage VDD by the voltage charged in the first capacitor 115 in the transfer phase. A boosted voltage is output from the positive charge pump terminal CPP. Here, for convenience of explanation, the voltage of the input terminal VDD is indicated as "voltage VDD". The same applies to other terminals. Charge pump booster circuit 110 includes a first capacitor 115, a positive charging switch 120, a bulk control circuit 125, a negative charging switch 130, a negative transfer switch 135, and current limiting circuits 140a to 140c.

The first capacitor 115 is connected between the positive charge pump terminal CPP (also referred to as "terminal CPP") and the negative charge pump terminal CPN (also referred to as "terminal CPN"). The first capacitor 115 charges the input voltage VDD for boosting the charge pump booster circuit 110, and discharges when outputting the boosted voltage.

The positive side charging switch 120 is a semiconductor switch whose main terminals are connected between the input terminal VDD and the terminal CPP as one end (positive side terminal) of the first capacitor 115. The positive side charging switch 120 inputs the control signal CHCP ("a" in the figure) from the drive circuit 165 to the control terminal (gate) via the current limiting circuit 140a, and controls the voltage between the gate and the source (gate-source voltage). When Vgs is below the threshold voltage, the main terminals are electrically disconnected (off state), and when the gate-source voltage Vgs exceeds the threshold voltage, the main terminals are electrically connected (on state). In this embodiment, the positive side charging switch 120 is an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Alternatively, the positive side charging switch 120 may be a semiconductor switch such as another type of N-channel FET that is turned on in response to the control voltage exceeding a threshold value.

The bulk control circuit 125 is connected to the main terminal on the terminal CPP side of the positive side charging switch 120, the ground VSS, and the drive circuit 165. Bulk control circuit 125 receives a control signal CHCP ("a" in the figure) for controlling on/off of positive side charging switch 120 from drive circuit 165. The bulk control circuit 125 switches which of the ground voltage VSS and the voltage of the terminal CPP is to be the bulk voltage of the positive side charging switch 120 based on the control signal CHCP. The bulk control circuit 125 according to the present embodiment uses the voltage of the terminal CPP as the bulk voltage of the positive side charging switch 120 and uses the terminal CPP side of the positive side charging switch 120 as the source in the charging phase (control signal CHCP is logic H). Make it work. Further, in the transfer phase (control signal CHCP is logic L), the bulk control circuit 125 uses the ground voltage VSS as the bulk voltage of the positive side charging switch 120, and causes the input terminal VDD side of the positive side charging switch 120 to function as a source. Prevents the boosted voltage of terminal CPP from flowing back to the input terminal. As an example, the bulk control circuit 125 is connected between the main terminal on the terminal CPP side of the positive charging switch 120 and the bulk, is turned on when the control signal CHCP is logic H, and is turned on when the control signal CHCP is logic L. a switching element that is connected between the bulk of the positive charging switch 120 and ground VSS, that is turned off when the control signal CHCP is logic H, and turned on when the control signal CHCP is logic L; It may have.

In the charging phase, such a bulk control circuit 125 can set the source and bulk of the positive side charging switch 120 at the same potential and cause the positive side charging switch 120 to function as a low threshold switching element such as a low threshold MOS. The on-resistance can be made smaller than when a switching element of the same size and normal threshold value is used. Thereby, the charge pump device 100 can use the positive side charging switch 120 which is smaller in size compared to the case where a switching element with a normal threshold value is used. Further, in the transfer phase, the bulk control circuit 125 increases the potential difference between the bulk and the source by setting the bulk voltage of the positive side charging switch 120 to the ground voltage VSS. As a result, even if a low threshold switching element is used as the positive side charging switch 120, the bulk control circuit 125 increases the threshold of the positive side charging switch 120 due to the substrate bias effect and reliably cuts off between the terminal VDD and the terminal CPP. can do.

The negative side charging switch 130 is a semiconductor switch whose main terminals are connected between the terminal CPN as the other end (negative side terminal) of the first capacitor 115 and the ground VSS. The negative side charging switch 130 inputs the control signal CHCN ("b" in the figure) from the drive circuit 165 through the current limiting circuit 140b to the control terminal (gate), and when the gate-source voltage Vgs is below the threshold voltage, The main terminals are electrically disconnected, and when the gate-source voltage Vgs exceeds a threshold voltage, the main terminals are electrically connected. In this embodiment, the negative side charging switch 130 is an N-type MOSFET like the positive side charging switch 120, and has a drain connected to the terminal CPN side and a source connected to the ground VSS side. Here, the ground VSS has a ground potential, and input voltage VDD>ground voltage VSS. Negative side charging switch 130 may be a semiconductor switch such as another type of N-channel FET.

The negative side transfer switch 135 is a semiconductor switch whose main terminals are connected between the input terminal VDD and the terminal CPN as the other end of the first capacitor 115. The negative side transfer switch 135 inputs the control signal TRCN ("c" in the figure) from the drive circuit 165 through the current limiting circuit 140c to the control terminal (gate), and when the gate-source voltage Vgs is below the threshold voltage, The main terminals are electrically disconnected, and when the gate-source voltage Vgs exceeds a threshold voltage, the main terminals are electrically connected. In this embodiment, the negative side transfer switch 135 is an N-type MOSFET like the positive side charging switch 120, and has a drain connected to the input terminal VDD side and a source connected to the terminal CPN side. Alternatively, negative side charging switch 130 may be a semiconductor switch such as another type of N-channel FET.

Current limiting circuits 140a-c are connected between drive circuit 165 and positive side charging switch 120, negative side charging switch 130, and negative side transfer switch 135, respectively. Current limiting circuits 140a to 140c receive a signal UVDET_N indicating the comparison result of input voltage VDD and output voltage CPOUT from comparison circuit 155, and in response to output voltage CPOUT being lower than input voltage VDD, charge pump booster circuit 110 At least one of the current that is input from the input terminal VDD or the current that the charge pump booster circuit 110 outputs from the terminal CPP to the output circuit 145 is limited. Note that the current limiting circuits 140a to 140c according to this embodiment limit at least one of these currents even when the output voltage CPOUT is lower than the input voltage VDD.

The output circuit 145 is connected between the terminal CPP and the output terminal CPOUT, and outputs the boosted voltage output from the terminal CPP by the charge pump booster circuit 110 as an output voltage from the output terminal CPOUT. The output circuit 145 includes a positive side transfer switch 150.

The positive side transfer switch 150 is a semiconductor switch whose main terminals are connected between the terminal CPP of the first capacitor 115 and the output terminal CPOUT. The positive side transfer switch 150 inputs the control signal TRCP ("d" in the figure) from the drive circuit 165 to the control terminal (gate) via the gate control circuit 170, and when the gate-source voltage Vgs is below the threshold voltage, The main terminals are electrically disconnected, and when the gate-source voltage Vgs exceeds a threshold voltage, the main terminals are electrically connected. Thereby, the positive side transfer switch 150 switches whether or not to output the boosted voltage that the charge pump booster circuit 110 outputs from the terminal CPP as an output voltage from the output terminal CPOUT. In this embodiment, the positive side transfer switch 150 is an N-type MOSFET like the positive side charging switch 120, and has a drain connected to the output terminal CPOUT side and a source connected to the terminal CPP side. Alternatively, the positive transfer switch 150 may be a semiconductor switch such as another type of N-channel FET.

Comparison circuit 155 is connected to input terminal VDD and output terminal CPOUT. Comparison circuit 155 compares input voltage VDD and output voltage CPOUT, and outputs a signal UVDET_N indicating the comparison result of input voltage VDD and output voltage CPOUT. In this embodiment, the signal UVDET_N becomes logic H when the output voltage CPOUT is less than or equal to the input voltage VDD, and becomes logic L when the output voltage CPOUT exceeds the input voltage VDD. Alternatively, the comparison circuit 155 may set the signal UVDET_N to logic H when the difference obtained by subtracting the input voltage VDD from the output voltage CPOUT exceeds a predetermined threshold.

Switching circuit 160 is connected to input terminal VDD, output terminal CPOUT, and comparison circuit 155. The switching circuit 160 changes the logic H level of the control signal for controlling at least one semiconductor switch in the charge pump booster circuit 110 and the output circuit 145 to the input voltage VDD and the output voltage according to the result of the comparison by the comparison circuit 155. Switch whether to use one of the CPOUTs to generate the signal.

The switching circuit 160 according to the present embodiment is configured as a control signal generation source to generate a control signal using the higher voltage of the input voltage VDD and the output voltage CPOUT based on the signal UVDET_N from the comparison circuit 155. Outputs voltage VDD_SEL. The switching circuit 160 may output either the input voltage VDD or the output voltage CPOUT as the voltage VDD_SEL based on the signal UVDET_N.

Drive circuit 165 is connected to switching circuit 160. The drive circuit 165 inputs a clock signal CPCLK used for switching the charge pump booster circuit 110 and the positive transfer switch 150, and uses the voltage VDD_SEL output from the switching circuit 160 to generate control signals CHCP(a), CHCN(b), TRCN (c) and TRCP (d) are generated. The drive circuit 165 controls the positive side charging switch 120, the negative side charging switch 130, the negative side transfer switch 135, and the positive side transfer switch 150 using control signals CHCP, CHCN, TRCN, and TRCP generated using the voltage VDD_SEL. Supplied to each terminal.

Gate control circuit 170 is connected to input terminal VDD, terminal CPP, and comparison circuit 155. The gate control circuit 170 boosts the control signal TRCP for the positive transfer switch 150 to output the boosted voltage from the terminal CPP of the charge pump booster circuit 110 as the output voltage CPOUT. and turns on the positive side transfer switch 150.

FIG. 2 is a timing chart showing an example of the operation of the charge pump device 100 according to this embodiment. This figure shows, in order from the top, the output voltage CPOUT, the result of power monitoring by the comparator circuit 155 (the value of the signal UVDET_N), the state of current limiting by the current limiting circuits 140a to 140c, and the state of switching the power supply of the control signal by the switching circuit 160. , respectively, show temporal changes in the state of gate control by the gate control circuit 170.

(1) Output voltage CPOUT
Charge pump device 100 is powered on and starts operating at time 0. Drive circuit 165 repeats the charging phase and transfer phase based on clock signal CPCLK. In the charging phase, drive circuit 165 sets control signals CHCP and CHCN to logic H to turn on positive side charging switch 120 and negative side charging switch 130, and sets control signals TRCN and TRCP to logic L to turn on negative side transfer switch 135 and positive side charging switch 130. Transfer switch 150 is turned off. As a result, the terminal CPP of the first capacitor 115 is connected to the input terminal VDD, and the terminal CPN of the first capacitor 115 is connected to the ground VSS. Thereby, the first capacitor 115 is gradually charged in the charging phase until the voltage across the first capacitor 115 reaches the input voltage VDD.

In the transfer phase, drive circuit 165 sets control signals CHCP and CHCN to logic L to turn off positive side charging switch 120 and negative side charging switch 130, and sets control signals TRCN and TRCP to logic H to turn off negative side transfer switch 135 and positive side charging switch 135. Transfer switch 150 is turned on. Thereby, the terminal CPN of the first capacitor 115 is connected to the input terminal VDD, and the terminal CPP of the first capacitor 115 is connected to the output terminal CPOUT. As a result, a boosted voltage obtained by boosting the input voltage VDD by the charging voltage of the first capacitor 115 is output to the output terminal CPOUT.

By repeating the charging phase and the transfer phase, the output voltage CPOUT increases and reaches the input voltage VDD at time t1. After time t1, output voltage CPOUT rises above input voltage VDD. The output voltage CPOUT reaches twice the input voltage VDD at maximum.

When the output load current flowing through the load connected to the output terminal CPOUT becomes larger than the rated output current of the charge pump device 100, the output voltage CPOUT decreases. The charge pump device 100 according to the present embodiment imposes a current limit on the charge pump to reduce the driving capability in response to the output voltage CPOUT decreasing to the input voltage VDD or lower. Alternatively, the charge pump device 100 may enter a power-down state and stop outputting.

(2) Power supply monitoring Comparison circuit 155 monitors input voltage VDD and output voltage CPOUT. Comparison circuit 155 sets signal UVDET_N to logic H while output voltage CPOUT is equal to or lower than input voltage VDD (from time 0 to time t1 and after time t2). Comparison circuit 155 sets signal UVDET_N to logic L while output voltage CPOUT exceeds input voltage VDD (from time t1 to time t2).

(3) Current Limiting The current limiting circuits 140a to 140c are configured to operate the positive side charging switch 120, the negative side charging The current flowing through switch 130 and negative side transfer switch 135 is limited. Thereby, the current limiting circuits 140a to 140c can prevent an excessive inrush current from flowing to the first capacitor 115 during startup of the charge pump device 100, and can also prevent a short circuit in the load connected to the output terminal CPOUT. This can prevent overcurrent from flowing to the load.

(4) Power supply switching The switching circuit 160 outputs the input voltage VDD as the voltage VDD_SEL during a period in which the output voltage CPOUT is equal to or lower than the input voltage VDD (from time 0 to time t1 and after time t2). The switching circuit 160 outputs the output voltage CPOUT as the voltage VDD_SEL during a period in which the output voltage CPOUT exceeds the input voltage VDD (from time t1 to time t2).

As described above, in this embodiment, NMOS switches are used as the positive side charging switch 120, the negative side transfer switch 135, and the positive side transfer switch 150. Here, the PMOS switch can be turned on by setting the control voltage supplied to the control signal to the ground voltage VSS. However, in order to turn on the NMOS switch, the control voltage must be increased so that the gate-source voltage Vgs exceeds the threshold voltage. In the positive side charging switch 120, when the first capacitor 115 is charged to near the input voltage VDD, the source voltage approaches the input voltage VDD. Therefore, in order to cause a sufficient current to flow through the positive side charging switch 120, it is desirable to make the control voltage (gate voltage) of the positive side charging switch 120 higher than the input signal VDD. Therefore, during normal operation, the switching circuit 160 sets the voltage of the signal VDD_SEL as the output voltage CPOUT in order to generate the control signal CHCP for the positive side charging switch 120 using the output voltage CPOUT boosted from the input voltage VDD (in the figure). "CPOUT" from time t1 to time t2).

However, when the charge pump device 100 is started, the output voltage CPOUT does not rise, and especially immediately after the charge pump device 100 is started, the output voltage CPOUT becomes 0V. Therefore, when the output voltage CPOUT is less than or equal to the input voltage VDD, the switching circuit 160 sets the voltage of the signal VDD_SEL to the input voltage VDD in order to generate the control signal CHCP for the positive side charging switch 120 using the input voltage VDD ( "VDD" from time 0 to time t1 and after time t2 in the figure).

Further, the negative side transfer switch 135 is turned on in the transfer phase, and causes an output current to flow from the input terminal VDD to the output terminal CPOUT via the first capacitor 115 and the positive side transfer switch 150. Since the negative side transfer switch 135 connects the input terminal VDD and the terminal CPN in the on state, the source voltage becomes approximately equal to the input voltage VDD. In order to cause a sufficient current to flow through the negative side transfer switch 135 in this state, the switching circuit 160 also uses the output voltage CPOUT to change the control signal TRCN when the output voltage CPOUT exceeds the input voltage VDD. If the output voltage CPOUT is less than or equal to the input voltage VDD, the input voltage VDD is used to generate the control signal TRCN.

Note that in this embodiment, the switching circuit 160 also generates the control signal CHCN for the negative side charging switch 130 in the same manner. Since the source of negative side charging switch 130 is connected to ground VSS, drive circuit 165 may always use input voltage VDD to generate control signal CHCN without using output voltage CPOUT.

(5) Gate control of the positive transfer switch 150 The positive transfer switch 150 is turned on in the transfer phase and connects the output terminal CPOUT and the terminal CPP. Therefore, the source voltage of the positive transfer switch 150 becomes approximately equal to the output voltage CPOUT in the on state. In order to cause sufficient current to flow through the positive side transfer switch 150 in this state, the switching circuit 160 and the drive circuit 165 control the output voltage CPOUT when the output voltage CPOUT exceeds the input voltage VDD (between time t1 and time t2). A control signal TRCP is generated using CPOUT, and the gate control circuit 170 boosts the control signal TRCP and supplies it to the positive transfer switch 150. When the output voltage CPOUT is less than or equal to the input voltage VDD (from time 0 to time t1 and after time t2), the switching circuit 160 and the drive circuit 165 generate the control signal TRCP using the input voltage VDD, The gate control circuit 170 boosts the control signal TRCP and supplies it to the positive transfer switch 150. Here, when the output voltage CPOUT exceeds the input voltage VDD, the gate control circuit 170 boosts the control signal TRCP using the input voltage VDD, and when the output voltage CPOUT is equal to or lower than the input voltage VDD, the gate control circuit 170 boosts the control signal TRCP using the input voltage VDD. The control signal TRCP may be boosted using the voltage of CPP. The function and configuration of the gate control circuit 170 for this purpose will be described later with reference to FIG.

According to the charge pump device 100 described above, depending on the result of comparing the input voltage VDD and the output voltage CPOUT, either the input voltage VDD or the output voltage CPOUT is used to control the positive side charging switch 120 and the negative side transfer switch 135. , and whether to generate a control signal for the forward transfer switch 150 can be switched. As a result, even when N-channel FETs or the like are used as the positive charging switch 120, negative transfer switch 135, and positive transfer switch 150, the charge pump device 100 can supply a sufficiently high voltage control signal to these. can be turned on.

In the present embodiment, the switching circuit 160 uses either the input voltage VDD or the output voltage CPOUT to send a control signal to all of the positive side charging switch 120, the negative side transfer switch 135, and the positive side transfer switch 150. A configuration is adopted in which it is possible to switch whether or not to generate a logic H voltage level. Instead, the switching circuit 160 uses this method to generate a control signal only for at least one semiconductor switch among the positive side charging switch 120, the negative side transfer switch 135, and the positive side transfer switch 150. You may also do so. In this case, the remaining semiconductor switches may be P-channel FETs.

FIG. 3 shows the configuration of the switching circuit 160 according to this embodiment. The switching circuit 160 includes a logic inverter 310, a level shifter 320, a semiconductor switch MP_CPO, a semiconductor switch MP_B1, a semiconductor switch MP_B2, a semiconductor switch MP_VDD, a semiconductor switch MP_B3, and a semiconductor switch MP_B4.

The logic negation element 310 inverts the logic value of the signal UVDET_N and outputs an inverted value that becomes logic L when the output voltage CPOUT is less than or equal to the input voltage VDD, and becomes logic H when the output voltage CPOUT exceeds the input voltage VDD. do. Level shifter 320 is connected to logical negation element 310. The level shifter 320 inputs the output voltage CPOUT and level-shifts the inverted value of the signal UVDET_N, which takes the voltages VDD and VSS, to the signal UVDET_LS, which takes the voltages CPOUT and VSS. Here, the level shifter 320 can output logic L even when the output voltage CPOUT is lower than the input voltage VDD.

The main terminals of the semiconductor switch MP_CPO are connected between the output terminal CPOUT and the output terminal of the voltage VDD_SEL. The semiconductor switch MP_CPO inputs the signal UVDET_N to its control terminal, and turns off when the signal UVDET_N is logic H (output voltage CPOUT≦input voltage VDD). Further, the semiconductor switch MP_CPO is turned on when the signal UVDET_N is logic L (output voltage CPOUT>input voltage VDD) and outputs the output voltage CPOUT as the voltage VDD_SEL.

The main terminals of semiconductor switches MP_B1 and MP_B2 are connected between the terminal on the output terminal CPOUT side of semiconductor switch MP_CPO and the bulk, and between the terminal on the drive circuit 165 side of semiconductor switch MP_CPO and the bulk. When the signal UVDET_N is logic H and the signal UVDET_LS is logic L (output voltage CPOUT≦input voltage VDD), semiconductor switch MP_B1 is turned off, semiconductor switch MP_B2 is turned on, and the bulk voltage of semiconductor switch MP_CPO is equal to the voltage on the drive circuit 165 side. Become. When the signal UVDET_N is logic L and the signal UVDET_LS is logic H (output voltage CPOUT>input voltage VDD), semiconductor switch MP_B1 is on, semiconductor switch MP_B2 is off, and the bulk voltage of semiconductor switch MP_CPO is equal to the voltage on the output terminal CPOUT side. Become.

The main terminals of the semiconductor switch MP_VDD are connected between the input terminal VDD and the output terminal of the voltage VDD_SEL in the switching circuit 160. The semiconductor switch MP_VDD inputs the signal UVDET_LS to its control terminal, and turns off when the signal UVDET_LS is logic H (output voltage CPOUT>input voltage VDD). Further, the semiconductor switch MP_VDD is turned on when the signal UVDET_LS is logic L (output voltage CPOUT≦input voltage VDD) and outputs the input voltage VDD as the voltage VDD_SEL.

The main terminals of semiconductor switches MP_B3 and MP_B4 are connected between the input terminal VDD side of semiconductor switch MP_VDD and the bulk, and between the drive circuit 165 side of semiconductor switch MP_VDD and the bulk. When the signal UVDET_N is logic H and the signal UVDET_LS is logic L (output voltage CPOUT≦input voltage VDD), semiconductor switch MP_B3 is on, semiconductor switch MP_B4 is off, and the bulk voltage of semiconductor switch MP_VDD is equal to the voltage on the input terminal VDD side. Become. When the signal UVDET_N is logic L and the signal UVDET_LS is logic H (output voltage CPOUT>input voltage VDD), semiconductor switch MP_B3 is turned off, semiconductor switch MP_B4 is turned on, and the bulk voltage of semiconductor switch MP_VDD is equal to the voltage on the output terminal CPOUT side. Become.

According to the switching circuit 160 described above, the voltage VDD_SEL can be set as the output voltage CPOUT when the signal UVDET_N is logic L, and the voltage VDD_SEL can be set as the input voltage VDD when the signal UVDET_N is logic H. In this embodiment, the switching circuit 160 uses P-channel MOSFETs as semiconductor switches MP_CPO, MP_VDD, and MP_B1 to MP_B4. These semiconductor switches do not flow a large current to be supplied to the load like the positive side charging switch 120, negative side transfer switch 135, and positive side transfer switch 150, so the positive side charging switch 120 and the negative side transfer switch 135 and the forward transfer switch 150, it can be realized with a very small size. Therefore, by using N-channel FETs as positive side charging switch 120, negative side transfer switch 135, and positive side transfer switch 150, the size of charge pump device 100 can be reduced even if a circuit such as switching circuit 160 is added. be able to.

FIG. 4 shows the configuration of the drive circuit 165 according to this embodiment. Drive circuit 165 includes a timing generator 410 and a clock buffer section 420.

Timing generator 410 receives clock signal CPCLK and generates control signals for positive side charging switch 120, negative side charging switch 130, negative side transfer switch 135, and positive side transfer switch 150. The control signals generated by timing generator 410 have voltage VDD at logic high and voltage VSS at logic low. In the charging phase, timing generator 410 sets the control signals for positive side charging switch 120 and negative side charging switch 130 to logic H, and sets the control signals for negative side transfer switch 135 and positive side transfer switch 150 to logic L. . Further, in the transfer phase, timing generator 410 sets the control signals for positive side charging switch 120 and negative side charging switch 130 to logic L, and sets the control signals for negative side transfer switch 135 and positive side transfer switch 150 to logic H. shall be.

Clock buffer section 420 is connected to timing generator 410. The clock buffer unit 420 receives the voltage VDD_SEL and converts the voltage level of the control signal output by the timing generator 410 using the voltage VDD_SEL. Clock buffer section 420 includes buffers 430a-d. Buffers 430a to 430d level-convert the logic H voltage of the input control signal to voltage VDD_SEL, and output a control signal CHCP ("a" in FIG. 1) that sets voltage VDD_SEL to logic H and voltage VSS to logic L. , CHCN ("b" in FIG. 1), TRCN ("c" in FIG. 1), and TRCP ("d" in FIG. 1).

FIG. 5 is a timing chart showing an example of the operation of the drive circuit 165 according to this embodiment. The upper side of the figure shows the time change in the voltages of the control signals CHCP and CHCN, and the lower side of the figure shows the time change in the voltages of the control signals TRCP and TRCN.

Drive circuit 165 alternately sets control signals CHCP and CHCN and control signals TRCP and TRCN to logic H. Here, when the output voltage CPOUT is less than or equal to the input voltage VDD (from time 0 to time t1 in the figure), the buffers 430a to 430d receive the input voltage VDD as the voltage VDD_SEL, and the logic H becomes the input voltage VDD. Outputs a control signal. When the output voltage CPOUT exceeds the input voltage VDD (after time t2 in the figure), the buffers 430a to 430d receive the output voltage CPOUT as the voltage VDD_SEL and output a control signal whose logic H becomes the output voltage CPOUT. In this way, the drive circuit 165 uses the voltage VDD_SEL output by the switching circuit 160 to turn on the positive side charging switch 120, the negative side charging switch 130, the negative side transfer switch 135, and the positive side transfer switch 150. A control signal can be generated.

FIG. 6 shows the configuration of the gate control circuit 170 according to this embodiment. The gate control circuit 170 charges the offset voltage using the input voltage VDD during at least part of the off period of the positive transfer switch 150. Then, when turning on the positive transfer switch 150 , the gate control circuit 170 adds an offset voltage to the voltage of the control signal TRCP for the positive transfer switch 150 and supplies the voltage to the control terminal of the positive transfer switch 150 .

Gate control circuit 170 includes a second capacitor 610 and a rectifying element 620. The second capacitor 610 has one end (terminal on the negative side) connected to the buffer 430d and inputted with the control signal TRCP, and the other end (terminal on the positive side) connected to the control terminal of the positive transfer switch 150. . The rectifying element 620 is connected between the input terminal VDD and the other end of the second capacitor 610.

FIG. 7 is a timing chart showing an example of the operation of the gate control circuit 170 according to this embodiment. This diagram shows, in order from the top, control signals CHCP and CHCN, control signals TRCP and TRCN, terminal CPP, and voltage times of the boosted control signals supplied to the control terminal (gate) of the positive transfer switch 150. Show change.

In the charging phase, drive circuit 165 sets control signals CHCP and CHCN to logic H and control signals TRCP and TRCN to logic L. As a result, the positive side charging switch 120 and the negative side charging switch 130 are turned on, and the negative side transfer switch 135 and the positive side transfer switch 150 are turned off. As a result, the first capacitor 115 is charged with the input voltage VDD, and the voltage at the terminal CPP becomes almost the same as the input voltage VDD.

In the charging phase, the second capacitor 610 receives the logic L (voltage VSS) control signal TRCP at one end and receives the input voltage VDD through the rectifying element 620 at the other end. Thereby, the second capacitor 610 is charged with the input voltage VDD as an offset voltage.

In the transfer phase, drive circuit 165 sets control signals CHCP and CHCN to logic L and control signals TRCP and TRCN to logic H. When the output voltage CPOUT exceeds the input voltage VDD, the gate control circuit 170 inputs the output voltage CPOUT to one end of the second capacitor 610 as a logic H control signal TRCP. As a result, the control terminal of the positive side transfer switch 150 is supplied with a control signal obtained by boosting the output voltage CPOUT by the offset voltage charged in the second capacitor 610. The rectifying element 620 allows current to flow in a direction from the input terminal VDD to the other end of the second capacitor 610, and prevents current from flowing backward from the other end of the second capacitor 610 to the input terminal VDD.

Note that since the positive side transfer switch 150 has a parasitic capacitance at its gate, in response to one end of the second capacitor 610 reaching the output voltage CPOUT, the parasitic capacitance of the second capacitor 610 and the positive side transfer switch 150 is reduced. Charge is redistributed between the two. As a result, the control terminal of the positive side transfer switch 150 becomes a voltage CPOUT+VDD×α, which is the output voltage CPOUT plus a voltage VDD×α (0<α<1) obtained by redistributing the offset voltage VDD.

According to 170 shown above, a control signal of voltage VDD is supplied to the control terminal of positive side transfer switch 150 while charging second capacitor 610 with input voltage VDD in the charging phase. Here, since the source of the positive side transfer switch 150 becomes the input voltage VDD during the charging phase, the positive side transfer switch 150 can be sufficiently turned off without dropping the control terminal to the voltage VSS. By supplying the voltage VDD to the control terminal in the charging phase, the gate control circuit 170 can charge the parasitic capacitance of the positive transfer switch 150 to an amount equivalent to the voltage VDD. This eliminates the need for the gate control circuit 170 to charge the parasitic capacitance of the positive side transfer switch 150 from the voltage VSS equivalent due to charge redistribution in the transfer phase, and allows the gate control circuit 170 to charge the parasitic capacitance of the positive side transfer switch 150 from the voltage equivalent to the voltage VSS. It becomes possible to sufficiently increase the voltage at the control terminal.

In addition, by inputting the control signal TRCP from the buffer 430d to one end of the second capacitor 610, the gate control circuit 170 operates as a semiconductor switch, etc. for supplying an offset voltage from the second capacitor 610 to the positive side transfer switch 150. It is no longer necessary to provide such a semiconductor switch, and timing control of such a semiconductor switch can be made unnecessary.

FIG. 8 shows the configuration of current limiting circuits 140a to 140c according to this embodiment together with a positive side charging switch 120, a negative side charging switch 130, and a negative side transfer switch 135. In this embodiment, the positive side charging switch 120 includes a plurality of positive side charging switches 120a to 120b connected in parallel. The positive side charging switch 120a, which is a part of the plurality of positive side charging switches 120a to 120b, inputs the control signal CHCP to a control terminal and switches on/off according to the control signal CHCP. The remaining positive side charging switch 120b among the plurality of positive side charging switches 120a to 120b inputs the output of the current limiting circuit 140a to a control terminal, and switches on/off according to the output of the current limiting circuit 140a.

Current limiting circuit 140a receives control signal CHCP from drive circuit 165 and signal UVDET_N from comparison circuit 155. The current limiting circuit 140a forcibly sets the control signal CHCP to logic L when the signal UVDET_N is logic H (output voltage CPOUT≦input voltage VDD). As a result, the current limiting circuit 140a prevents the positive side charging switch 120b from being turned on in response to the fact that the output voltage CPOUT is lower than the input voltage VDD, and the current limiting circuit 140a prevents the positive side charging switch 120b from turning on, and connects the input terminal VDD to the first terminal in the charge pump booster circuit 110. Limits the current flowing into capacitor 115.

The current limiting circuit 140a according to this embodiment includes a NOR element that NORs the inverted value of the control signal CHCP and the signal UVDET_N. As a result, when the signal UVDET_N is a logic H, the current limiting circuit 140a outputs a logic L regardless of the logic value of the control signal CHCP.

Negative side charging switch 130 includes a plurality of negative side charging switches 130a-b connected in parallel. The negative side charging switch 130a, which is part of the plurality of negative side charging switches 130a to 130b, inputs the control signal CHCN to a control terminal and switches on/off according to the control signal CHCN. The remaining negative side charging switch 130b among the plurality of negative side charging switches 130a to 130b inputs the output of the current limiting circuit 140b to a control terminal, and switches on/off according to the output of the current limiting circuit 140b.

Current limiting circuit 140b receives control signal CHCN from drive circuit 165 and signal UVDET_N from comparison circuit 155. The current limiting circuit 140b forcibly sets the control signal CHCN to logic L when the signal UVDET_N is logic H (output voltage CPOUT≦input voltage VDD). Thereby, the current limiting circuit 140b prevents the negative side charging switch 130b from turning on in response to the fact that the output voltage CPOUT is lower than the input voltage VDD, and the current limiting circuit 140b prevents the negative side charging switch 130b from turning on, and connects the input terminal VDD to the first terminal in the charge pump booster circuit 110. Limits the current flowing into capacitor 115. The configuration of the current limiting circuit 140b is similar to the current limiting circuit 140a, so a description thereof will be omitted.

The negative side transfer switch 135 includes a plurality of negative side transfer switches 135a to 135b connected in parallel. The negative side transfer switch 135a, which is part of the plurality of negative side transfer switches 135a to 135b, inputs the control signal TRCN to its control terminal and switches on/off according to the control signal TRCN. The remaining negative side transfer switch 135b among the plurality of negative side transfer switches 135a to 135b inputs the output of the current limiting circuit 140c to a control terminal, and switches on/off according to the output of the current limiting circuit 140c.

Current limiting circuit 140c receives control signal TRCN from drive circuit 165 and signal UVDET_N from comparison circuit 155. The current limiting circuit 140c forcibly sets the control signal TRCN to logic L when the signal UVDET_N is logic H (output voltage CPOUT≦input voltage VDD). As a result, the current limiting circuit 140c prevents the negative side transfer switch 135b from being turned on in response to the output voltage CPOUT being lower than the input voltage VDD, and prevents the negative side transfer switch 135, the first capacitor 115, and the output voltage from turning on. The current output from the terminal CPP to the output terminal CPOUT via the circuit 145 is limited. The configuration of the current limiting circuit 140c is similar to the current limiting circuit 140a, so a description thereof will be omitted.

According to the current limiting circuits 140a to 140c described above, in response to the fact that the output voltage CPOUT is lower than the input voltage VDD, the positive side charging switch 120, the negative side charging switch 130, which includes semiconductor switches connected in parallel, And some semiconductor switches of each of the negative side transfer switches 135 are prevented from being turned on. As a result, the current limiting circuits 140a to 140c determine whether the charge pump booster circuit 110 outputs a current from the input terminal VDD or a current that the charge pump booster circuit 110 outputs from the terminal CPP in response to the fact that the output voltage CPOUT is lower than the input voltage VDD. At least one of the currents output to the circuit 145 can be limited to stabilize the operation of the charge pump device 100.

FIG. 9 shows the configuration of a gate control circuit 900 according to a first modification of this embodiment. Gate control circuit 900 is a first modification of gate control circuit 170 shown in FIG. Gate control circuit 900 includes a second capacitor 910 and a rectifying element 920. The second capacitor 910 is similar to the second capacitor 610 of FIG. 6, so a description thereof will be omitted.

The main terminals of the rectifying element 920 are connected between the input terminal VDD and the other end (positive side terminal) of the second capacitor 610. More specifically, the rectifying element 920 is an N-channel FET whose source is connected to the input terminal VDD, whose drain is connected to the second capacitor 910, and whose gate (control terminal) is connected to the input terminal VDD. With such a configuration, the rectifying element 920 allows current to flow from the input terminal VDD to the other end of the second capacitor 910 when the voltage at the other end of the second capacitor 910 is lower than or equal to VDD. When the voltage at the end exceeds VDD, reverse flow of current from the other end of the second capacitor 910 to the input terminal VDD is prevented.

FIG. 10 shows the configuration of a gate control circuit 1000 according to a second modification of this embodiment. Gate control circuit 1000 is a second modification of gate control circuit 170 shown in FIG. Gate control circuit 1000 includes a second capacitor 1010, a rectifying element 1020, a switch 1030, and a switch 1040. The second capacitor 1010 and the rectifying element 1020 are the same as the second capacitor 910 and the rectifying element 920 in FIG. 9, respectively, so the description thereof will be omitted.

Switch 1030 has its main terminals connected between input terminal VDD and rectifying element 1020, and receives power down signal PD at its gate. The switch 1030 according to this embodiment is, for example, a P-channel FET. Here, the power down signal PD is at logic L while the charge pump device 100 is in operation, and is set at logic H before the charge pump device 100 is powered off. While the power down signal PD is at logic L, the switch 1030 is in the on state. Accordingly, switch 1030 supplies input voltage VDD to node GATE_DI during normal operation of charge pump device 100. Thereby, the gate control circuit 1000 functions similarly to the gate control circuit 900. When the power down signal PD becomes logic H, the switch 1030 is turned off. As a result, the switch 1030 cuts off the supply of the input voltage VDD to the second capacitor 1010 before the charge pump device 100 is powered off.

The switch 1040 has a positive main terminal (drain as an example) connected to a node GATE_DI between the rectifying element 1020 and the switch 1030, a negative main terminal (source as an example) connected to ground VSS, and a power supply to the gate. Receives down signal PD. The switch 1040 according to this embodiment is an N-channel FET, for example. While the power down signal is at logic low, switch 1040 is in an off state. Thereby, switch 1040 cuts off between node GATE_DI and ground VSS during normal operation of charge pump device 100. When the power down signal PD becomes logic H, the switch 1040 is turned on. As a result, the switch 1040 connects the node GATE_DI to the ground VSS before the charge pump device 100 is powered off.

Here, when the node GATE_DI becomes the ground voltage VSS, the rectifying element 1020 has a gate voltage of VDD and a source voltage of VSS, and is turned on. Thereby, the rectifying element 1020 can discharge the charge stored in the second capacitor 1010 via the switch 1040 before the power of the charge pump device 100 is turned off.

FIG. 11 shows the configuration of a gate control circuit 1100 according to a third modification of this embodiment. Gate control circuit 1100 is a third modification of gate control circuit 170 shown in FIG. Gate control circuit 1100 includes a second capacitor 1110, a rectifying element 1120, a switch 1130, and a switch 1140. The second capacitor 1110 and the rectifying element 1120 are the same as the second capacitor 1010 and the rectifying element 1020 in FIG. 10, respectively, so a description thereof will be omitted.

Switch 1130 has its main terminals connected between input terminal VDD and rectifying element 1120, and receives signal UVDET_N at its gate. The switch 1130 according to this embodiment is, for example, a P-channel FET. When the signal UVDET_N is logic L (output voltage CPOUT>input voltage VDD), the switch 1130 is turned on. As a result, switch 1130 sets node GATE_DI to voltage VDD while charge pump device 100 outputs output voltage CPOUT exceeding input voltage VDD, and operates gate control circuit 1100 in the same manner as gate control circuit 900 in FIG. can be done. When the signal UVDET_N is at logic H (output voltage CPOUT≦input voltage VDD), the switch 1130 is turned off.

The switch 1140 has a positive side main terminal (for example, a drain) connected to a terminal CPP, a negative side main terminal (for example, a source) connected to a node GATE_DI between the rectifying element 1120 and the switch 1130, and has a signal UVDET_N applied to the gate. receive. The switch 1140 according to this embodiment is an N-channel FET, for example. When the signal UVDET_N is logic L (output voltage CPOUT>input voltage VDD), the switch 1040 is in the off state. When the signal UVDET_N is at logic H (output voltage CPOUT≦input voltage VDD), the switch 1140 is turned on. Accordingly, the switch 1140 supplies the voltage of the terminal CPP to the node GATE_DI while the charge pump device 100 is activated and before the power of the charge pump device 100 is turned off.

As a result, the gate control circuit 1100 supplies the voltage of the terminal CPP to the second capacitor 1110 when the output voltage CPOUT is less than or equal to the input voltage VDD, as shown in the "gate control" timing chart of FIG. be able to. As a result, in the charging phase, both the gate and source voltages of the positive transfer switch 150 become the voltage of the terminal CPP, and the gate-source voltage Vgs becomes substantially 0, so the positive transfer switch 150 is turned off. Become. Therefore, the gate control circuit 1100 can turn off the positive transfer switch 150 even when the voltage at the terminal CPP is low, such as immediately after switching to the charging phase.

In the transfer phase, the gate of the positive transfer switch 150 is boosted by the voltage of the terminal CPP with respect to the output voltage CPOUT, so the positive transfer switch 150 is turned on. Furthermore, the charge pump device 100 may have a function of entering a power-down state and lowering the terminal CPP to the ground voltage VSS before turning off the power. Thereby, the switch 1140 can discharge the second capacitor 1110 via the rectifying element 1120 in the power-down state.

FIG. 12 shows the configuration of a gate control circuit 1200 according to a fourth modification of the present embodiment together with positive side transfer switches 150a to 150b. In this modification, the positive transfer switch 150 includes a plurality of positive transfer switches 150a to 150b connected in parallel. The positive side transfer switch 150a, which is part of the plurality of positive side transfer switches 150a to 150b, inputs the control signal TRCP to its control terminal and switches on/off according to the control signal TRCP. The remaining positive side transfer switch 150b among the plurality of positive side transfer switches 150a to 150b inputs the output of the current limiting circuit 1250 to a control terminal, and switches on/off according to the output of the current limiting circuit 1250.

Gate control circuit 1200 is a fourth modification of gate control circuit 170 shown in FIG. 6, and is obtained by adding a function to limit the current flowing through positive transfer switch 150 to gate control circuit 1100 shown in FIG. The gate control circuit 1200 includes a plurality of second capacitors 1210a-b, a plurality of rectifying elements 1220a-b, a switch 1230, a switch 1240, and a current limiting circuit 1250.

Each of the plurality of second capacitors 1210a to 1210b is similar to the second capacitor 1110 in FIG. 11, except that the output of the current limiting circuit 1250 is input to one end of the second capacitor 1210b instead of the control signal TRCP. Since there is, I will omit the explanation. Each of the plurality of rectifying elements 1220a to 1220b is the same as the rectifying element 1120 of FIG. 11 except that each of the plurality of rectifying elements 1220a to 1220b is provided corresponding to each of the plurality of second capacitors 1210a to b, so a description thereof will be omitted. Further, the switch 1230 and the switch 1240 are the same as the switch 1130 and the switch 1140 in FIG. 11, so the description thereof will be omitted.

Current limiting circuit 1250 receives control signal TRCP from drive circuit 165 and signal UVDET_N from comparison circuit 155. When the signal UVDET_N is at logic H (when output voltage CPOUT≦input voltage VDD), current limiting circuit 1250 forces control signal TRCP to be at logic L and supplies it to second capacitor 1210b. As a result, current limiting circuit 1250 prevents positive side transfer switch 150b from turning on in response to output voltage CPOUT being lower than input voltage VDD, and current flows from charge pump booster circuit 110 to output terminal CPOUT. Limit current.

Current limiting circuit 1250 according to this modification includes a NOR element that NORs the inverted value of control signal TRCP and signal UVDET_N. As a result, current limiting circuit 1250 outputs logic L regardless of the logic value of control signal TRCP when signal UVDET_N is logic H.

According to the gate control circuit 1200 described above, the current flowing from the charge pump booster circuit 110 to the output terminal CPOUT is limited in response to the fact that the output voltage CPOUT is lower than the input voltage VDD. Thereby, the gate control circuit 1200 can stabilize the operation of the charge pump device 100 at startup, and can prevent overdischarge of the first capacitor 115.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the range described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the embodiments described above. It is clear from the claims that such modifications or improvements may be included within the technical scope of the present invention.

The order of execution of each process, such as the operation, procedure, step, and stage in the apparatus, system, program, and method shown in the claims, specification, and drawings, is specifically defined as "before" or "before". It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Even if the claims, specifications, and operational flows in the drawings are explained using "first," "next," etc. for convenience, this does not mean that it is essential to carry out the operations in this order. It's not a thing.

Reference Signs List 100 charge pump device, 110 charge pump booster circuit, 115 first capacitor, 120 positive side charging switch, 125 bulk control circuit, 130 negative side charging switch, 135 negative side transfer switch, 140a to c current limiting circuit, 145 output circuit, 150 positive side transfer switch, 155 comparison circuit, 160 switching circuit, 165 drive circuit, 170 gate control circuit, 310 logic NOT element, 320 level shifter, 410 timing generator, 420 clock buffer unit, 430a to d buffer, 610 second capacitor , 620 rectifying element, 900 gate control circuit, 910 second capacitor, 920 rectifying element, 1000 gate control circuit, 1010 second capacitor, 1020 rectifying element, 1030 switch, 1040 switch, 1100 gate control circuit, 1110 second capacitor, 1120 Rectifying element, 1130 switch, 1140 switch, 1200 gate control circuit, 1210a-b second capacitor, 1220a-b rectifying element, 1230 switch, 1240 switch, 1250 current limiting circuit

Claims (13)

a charge pump booster circuit that outputs a boosted voltage obtained by boosting an input voltage input from an input terminal;
an output circuit having a positive transfer switch that is a semiconductor switch that switches whether or not to output the boosted voltage as an output voltage ;
a comparison circuit that compares the input voltage and the output voltage;
a switching circuit that switches, depending on a result of the comparison, which of the input voltage and the output voltage is used to generate a control signal for controlling at least one semiconductor switch in the charge pump booster circuit;
a gate control circuit that boosts a control signal for the positive side transfer switch and supplies it to a control terminal of the positive side transfer switch when outputting the boosted voltage as the output voltage;
A charge pump device equipped with. The gate control circuit includes:
charging an offset voltage using the input voltage during at least a part of the off period of the positive side transfer switch;
The charge pump device according to claim 1 , wherein when the positive side transfer switch is turned on, the offset voltage is added to the voltage of the control signal for the positive side transfer switch and the resultant voltage is supplied to the control terminal of the positive side transfer switch. . a charge pump booster circuit that outputs a boosted voltage obtained by boosting an input voltage input from an input terminal;
an output circuit having a positive transfer switch that switches whether or not to output the boosted voltage as an output voltage;
When charging the offset voltage using the input voltage during at least part of the off period of the positive side transfer switch and turning on the positive side transfer switch, the voltage of the control signal for the positive side transfer switch is changed to the voltage of the control signal for the positive side transfer switch. a gate control circuit that applies an offset voltage and supplies it to a control terminal of the positive side transfer switch. a comparison circuit that compares the input voltage and the output voltage;
a switching circuit that switches, depending on a result of the comparison, which of the input voltage and the output voltage is used to generate a control signal for controlling at least one semiconductor switch in the charge pump booster circuit;
The charge pump device according to claim 3, comprising: The gate control circuit includes:
a second capacitor, one end of which receives a control signal for the positive transfer switch, and the other end connected to a control terminal of the positive transfer switch;
5. A rectifying element connected between the input terminal and the other end of the second capacitor to prevent reverse flow of current from the other end of the second capacitor to the input terminal. The charge pump device described in Section. 6. The charge pump device according to claim 1 , wherein the positive side transfer switch is an N-type MOSFET. From claim 1, further comprising a current limiting circuit that limits at least one of the current input to the charge pump booster circuit or the current output by the charge pump booster circuit in response to the output voltage being lower than the input voltage. 6. The charge pump device according to any one of 6 . a charge pump booster circuit that outputs a boosted voltage obtained by boosting an input voltage input from an input terminal;
an output circuit that outputs the boosted voltage as an output voltage;
a comparison circuit that compares the input voltage and the output voltage;
a switching circuit that switches, depending on the result of the comparison, which of the input voltage and the output voltage is used to generate a control signal for controlling at least one semiconductor switch in the charge pump booster circuit;
a current limiting circuit that limits at least one of the current input to the charge pump booster circuit or the current output by the charge pump booster circuit in response to the output voltage being lower than the input voltage;
A charge pump device equipped with. 9. The charge pump device according to claim 1, wherein the switching circuit generates the control signal using a higher voltage of the input voltage and the output voltage. The switching circuit outputs either the input voltage or the output voltage according to the result of the comparison,
The charge pump device according to any one of claims 1, 2, 4, 8, or 9, further comprising a drive circuit that generates the control signal using the voltage output by the switching circuit. the at least one semiconductor switch is an N-type MOSFET;
The charge pump device according to claim 10 , wherein the drive circuit generates the control signal that turns on the at least one semiconductor switch using the voltage output by the switching circuit. The charge pump booster circuit is
a first capacitor;
a positive side charging switch that is a semiconductor switch connected between the input terminal and one end of the first capacitor;
a negative side charging switch that is a semiconductor switch connected between the other end of the first capacitor and ground;
a negative side transfer switch that is a semiconductor switch connected between the input terminal and the other end of the first capacitor;
The charge according to claim 10 or 11 , wherein the drive circuit supplies a control signal generated using the voltage output by the switching circuit to at least one control terminal of the positive side charging switch or the negative side transfer switch. pump equipment. The charge pump booster circuit is configured to switch between a ground voltage and a voltage at one end of the first capacitor as the bulk voltage of the positive charging switch based on a control signal supplied to the positive charging switch. The charge pump device according to claim 12, comprising a control circuit.

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