JP2022006505A - Charge pump device - Google Patents

Abstract

To provide a charge pump device which limits an output current in response to a condition that an output voltage is lower than an input voltage.SOLUTION: A charge pump device 100 comprises: a charge pump step-up circuit 110 which outputs a step-up voltage obtained by stepping up an input voltage VDD inputted from an input terminal; an output circuit 145 which outputs the step-up voltage as an output voltage CPOUT; a comparator circuit 155 which compares the input voltage VDD and the output voltage CPOUT; and a changeover circuit 160 which performs, according to a result of the comparison, a changeover between the input voltage VDD and the output voltage CPOUT, as a voltage to be used for generating a control signal for controlling at least one semiconductor switch within the charge pump step-up circuit 110.SELECTED DRAWING: Figure 1

Description

The present invention relates to a charge pump device.

Patent Documents 1 to 3 describe a charge pump type booster. For example, in Patent Document 1, the booster circuit has switching transistors TR1 to 4 (paragraph 0004), the transistor TR2 is an N-channel field effect transistor (N-channel FET), and the transistors TR1, TR3, and TR4 are P-channels. It is a field effect transistor (P channel FET) (paragraph 0006). The same applies to Patent Documents 2 and 3 (see FIG. 1 of Patent Document 2, FIG. 1 of Patent Document 3, and the like).
[Prior Art Document]
[Patent Document]
[Patent Document 1] Japanese Patent Application Laid-Open No. 6-351229 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-283794 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-30327

Since the P-channel FET has a higher on-resistance than the N-channel FET of the same size, the size of the P-channel FET becomes larger than that of the N-channel FET in order to pass the same amount of current.

In the first aspect of the present invention, a charge pump device is provided. The charge pump device may include a charge pump booster circuit that outputs a boosted voltage obtained by boosting the input voltage input from the input terminal. The charge pump device may include an output circuit that outputs a boosted voltage as an output voltage. The charge pump device may include a comparison circuit that compares the input voltage and the output voltage. The charge pump device includes a switching circuit that switches between input voltage and output voltage to generate a control signal for controlling at least one semiconductor switch in the charge pump booster circuit, depending on the result of the comparison. It's okay.

The switching circuit may generate a control signal using the higher of the input voltage and the output voltage.

The switching circuit may output either an input voltage or an output voltage depending on the result of the comparison. The charge pump device may further include a drive circuit that generates a control signal using the voltage output by the switching circuit.

At least one semiconductor switch may be an N-type MOSFET. The drive circuit may use the voltage output by the switching circuit to generate a control signal that turns on at least one semiconductor switch.

The charge pump booster circuit may have a first capacitor. The charge pump booster circuit may have a positive charge switch, which is a semiconductor switch connected between the input terminal and one end of the first capacitor. The charge pump booster circuit may have a negative charge switch, which is a semiconductor switch connected between the other end of the first capacitor and the ground. The charge pump booster circuit may have a negative transfer switch, which is a semiconductor switch connected between an input terminal and another terminal of the first capacitor. The drive circuit may supply a control signal generated by using the voltage output by the changeover circuit to at least one control terminal of the positive side charging switch or the negative side transfer switch.

The output circuit may have a positive transfer switch, which is a semiconductor switch for switching whether or not to output a boosted voltage as an output voltage. The charge pump device may further include a gate control circuit that boosts the control signal for the positive transfer switch and supplies it to the control terminal of the positive transfer switch when the boost voltage is output as an output voltage.

The gate control circuit may use the input voltage to charge the offset voltage during at least part of the off period of the positive transfer switch. When the positive transfer switch is turned on, the gate control circuit may add an offset voltage to the voltage of the control signal for the positive transfer switch and supply it to the control terminal of the positive transfer switch.

In the second aspect of the present invention, a charge pump device is provided. The charge pump device may include a charge pump booster circuit that outputs a boosted voltage obtained by boosting the input voltage input from the input terminal. The charge pump device may include an output circuit having a positive transfer switch that switches whether to output the boosted voltage as an output voltage. The charge pump device uses the input voltage to charge the offset voltage during at least part of the off period of the positive transfer switch to the voltage of the control signal for the positive transfer switch when the positive transfer switch is turned on. It may be provided with a gate control circuit that applies an offset voltage and supplies it to the control terminal of the positive transfer switch.

The gate control circuit may have a second capacitor in which a control signal for a positive transfer switch is input to one end and the other end is connected to a control terminal of the positive transfer switch. The gate control circuit may have a rectifying element connected between the input terminal and the other end of the second capacitor to prevent backflow of current from the other end of the second capacitor to the input terminal.

The positive transfer switch may be an N-type MOSFET.

The charge pump device may include a current limiting circuit that limits at least one of the currents input by the charge pump booster circuit or the current output by the charge pump booster circuit, depending on whether the output voltage is lower than the input voltage.

The outline of the above invention does not list all the necessary features of the present invention. A subcombination of these feature groups can also be an invention.

The configuration of the charge pump device 100 according to this embodiment is shown. It is a timing chart which shows an example of the operation of the charge pump device 100 which concerns on this embodiment. The configuration of the switching circuit 160 according to this embodiment is shown. The configuration of the drive circuit 165 according to this embodiment is shown. It is a timing chart which shows an example of the operation of the drive circuit 165 which concerns on this embodiment. The configuration of the gate control circuit 170 according to this embodiment is shown. It is a timing chart which shows an example of the operation of the gate control circuit 170 which concerns on this embodiment. The configurations of the current limiting circuits 140a to 140c according to this embodiment are shown. The configuration of the gate control circuit 900 according to the first modification of this embodiment is shown. The configuration of the gate control circuit 1000 according to the second modification of this embodiment is shown. The configuration of the gate control circuit 1100 according to the third modification of this embodiment is shown. The configuration of the gate control circuit 1200 according to the 4th modification of this embodiment is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention to which the claims are made. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

FIG. 1 shows the configuration of the charge pump device 100 according to the present embodiment. The charge pump device 100 according to the present embodiment has these switches so that the positive side charge switch 120, the negative side transfer switch 135, and the positive side transfer switch 150 in the charge pump device 100 can be N-shaped. Generates an appropriate control voltage to be supplied to the control terminal (gate terminal) of.

The charge pump device 100 includes a charge pump booster circuit 110, an output circuit 145, a comparison circuit 155, a switching circuit 160, a drive circuit 165, and a gate control circuit 170. The charge pump booster circuit 110 charges the first capacitor 115 with the input voltage VDD input from the input terminal VDD in the charging phase, and boosts the input voltage VDD with the voltage charged in the first capacitor 115 in the transfer phase. The boost voltage is output from the positive charge pump terminal CPP. Here, for convenience of explanation, the voltage of the input terminal VDD is referred to as “voltage VDD”. The same applies to other terminals. The charge pump booster circuit 110 includes a first capacitor 115, a positive charging switch 120, a bulk control circuit 125, a negative charging switch 130, a negative transfer switch 135, and current limiting circuits 140a to 140c.

The first capacitor 115 is connected between the positive charge pump terminal CPP (also referred to as "terminal CPP") and the negative charge pump terminal CPN (also referred to as "terminal CPN"). The first capacitor 115 charges the input voltage VDD for boosting the charge pump booster circuit 110, and discharges when the boosted voltage is output.

The positive side charging switch 120 is a semiconductor switch in which the main terminals are connected between the input terminal VDD and the terminal CPP as one end (the terminal on the positive side) of the first capacitor 115. The positive charging switch 120 inputs the control signal CHCP (“a” in the figure) from the drive circuit 165 via the current limiting circuit 140a to the control terminal (gate), and the voltage between the gate and the source (gate-source voltage). When Vgs is equal to or less than the threshold voltage, the main terminals are electrically disconnected (off state), and when the gate-source voltage Vgs exceeds the threshold voltage, the main terminals are electrically connected (on state). In the present embodiment, the positive charging switch 120 is an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor: metal oxide semiconductor field effect transistor). Instead of this, the positive charging switch 120 may be a semiconductor switch such as another type of N-channel FET that is turned on when the control voltage exceeds the threshold value.

The bulk control circuit 125 is connected to the main terminal on the terminal CPP side of the positive charging switch 120, the ground VSS, and the drive circuit 165. The bulk control circuit 125 receives a control signal CHCP (“a” in the figure) for controlling the on / off of the positive charging switch 120 from the drive circuit 165. The bulk control circuit 125 switches whether the ground voltage VSS or the voltage of the terminal CPP is the bulk voltage of the positive charging switch 120 based on the control signal CHCP. In the bulk control circuit 125 according to the present embodiment, in the charging phase (control signal CHCP is logic H), the voltage of the terminal CPP is used as the bulk voltage of the positive charging switch 120, and the terminal CPP side of the positive charging switch 120 is used as the source. Make it work. Further, in the transfer phase (control signal CHCP is logic L), the bulk control circuit 125 functions the ground voltage VSS as the bulk voltage of the positive charging switch 120 and the input terminal VDD side of the positive charging switch 120 as the source. Prevents the boost voltage of the terminal CPP from flowing back to the input terminal. As an example, the bulk control circuit 125 is connected between the main terminal on the terminal CPP side of the positive charging switch 120 and the bulk, is turned on when the control signal CHCP is logic H, and is turned on when the control signal CHCP is logic L. A switching element that is connected between the bulk of the positive charging switch 120 and the ground VSS, and is turned off when the control signal CHCP is logic H, and turned on when the control signal CHCP is logic L. And may have.

In such a bulk control circuit 125, in the charging phase, the source of the positive charging switch 120 and the bulk can be set to the same potential, and the positive charging switch 120 can function as a low threshold switching element such as a low threshold MOS. The on-resistance can be made smaller than when a switching element having the same size and a normal threshold value is used. As a result, the charge pump device 100 can use the positive charge switch 120, which is smaller in size than the case where a switching element having a normal threshold value is used. Further, in the transfer phase, the bulk control circuit 125 increases the potential difference between the bulk and the source by setting the bulk voltage of the positive charging switch 120 to the ground voltage VSS. As a result, even if the bulk control circuit 125 uses a low threshold switching element as the positive charging switch 120, the threshold of the positive charging switch 120 is raised by the substrate bias effect to ensure that the terminal VDD and the terminal CPP are cut off. can do.

The negative charging switch 130 is a semiconductor switch in which the main terminal is connected between the terminal CPN as the other end (terminal on the negative side) of the first capacitor 115 and the ground VSS. The negative charging switch 130 inputs the control signal CHCN (“b” in the figure) from the drive circuit 165 via the current limiting circuit 140b to the control terminal (gate), and when the gate-source voltage Vgs is equal to or less than the threshold voltage. The main terminals are electrically disconnected, and when the gate-source voltage Vgs exceeds the threshold voltage, the main terminals are electrically connected. In the present embodiment, the negative charging switch 130 is an N-type MOSFET like the positive charging switch 120, and the drain is connected to the terminal CPN side and the source is connected to the ground VSS side. Here, the ground VSS has a ground potential, and the input voltage VDD> the ground voltage VSS. The negative charging switch 130 may be a semiconductor switch such as another type of N-channel FET.

The negative transfer switch 135 is a semiconductor switch in which the main terminals are connected between the input terminal VDD and the terminal CPN as the other end of the first capacitor 115. The negative transfer switch 135 inputs a control signal TRCN (“c” in the figure) from the drive circuit 165 to the control terminal (gate) via the current limiting circuit 140c, and when the gate-source voltage Vgs is equal to or less than the threshold voltage. The main terminals are electrically disconnected, and when the gate-source voltage Vgs exceeds the threshold voltage, the main terminals are electrically connected. In the present embodiment, the negative transfer switch 135 is an N-type MOSFET like the positive charging switch 120, and the drain is connected to the input terminal VDD side and the source is connected to the terminal CPN side. Instead of this, the negative charging switch 130 may be a semiconductor switch such as another type of N-channel FET.

The current limiting circuits 140a to 140c are connected between the drive circuit 165 and the positive side charging switch 120, the negative side charging switch 130, and the negative side transfer switch 135, respectively. The current limiting circuits 140a to c receive the signal UVDET_N indicating the comparison result of the input voltage VDD and the output voltage CPOUT from the comparison circuit 155, and the charge pump booster circuit 110 responds that the output voltage CPOUT is lower than the input voltage VDD. The current input from the input terminal VDD or the charge pump booster circuit 110 limits at least one of the currents output from the terminal CPP to the output circuit 145. The current limiting circuits 140a to 140 according to the present embodiment limit at least one of these currents even when the output voltage CPOUT is equal to or lower than the input voltage VDD.

The output circuit 145 is connected between the terminal CPP and the output terminal CPOUT, and outputs the boosted voltage output from the terminal CPP by the charge pump booster circuit 110 as the output voltage from the output terminal CPOUT. The output circuit 145 has a positive transfer switch 150.

The positive transfer switch 150 is a semiconductor switch in which the main terminals are connected between the terminal CPP and the output terminal CPOUT of the first capacitor 115. The positive transfer switch 150 inputs a control signal TRCP (“d” in the figure) from the drive circuit 165 to the control terminal (gate) via the gate control circuit 170, and when the gate-source voltage Vgs is equal to or less than the threshold voltage. The main terminals are electrically disconnected, and when the gate-source voltage Vgs exceeds the threshold voltage, the main terminals are electrically connected. As a result, the positive transfer switch 150 switches whether or not the boost voltage output from the terminal CPP by the charge pump booster circuit 110 is output from the output terminal CPOUT as an output voltage. In the present embodiment, the positive transfer switch 150 is an N-type MOSFET like the positive charging switch 120, and the drain is connected to the output terminal CPOUT side and the source is connected to the terminal CPP side. Instead, the positive transfer switch 150 may be a semiconductor switch such as another type of N-channel FET.

The comparison circuit 155 is connected to the input terminal VDD and the output terminal CPOUT. The comparison circuit 155 compares the input voltage VDD and the output voltage CPOUT, and outputs a signal UVDET_N indicating the comparison result of the input voltage VDD and the output voltage CPOUT. In the present embodiment, the signal UVDET_N becomes logic H when the output voltage CPOUT is equal to or less than the input voltage VDD, and becomes logic L when the output voltage CPOUT exceeds the input voltage VDD. Instead of this, the comparison circuit 155 may set the signal UVDET_N as the logic H when the difference obtained by subtracting the input voltage VDD from the output voltage CPOUT exceeds a predetermined threshold value.

The switching circuit 160 is connected to the input terminal VDD, the output terminal CPOUT, and the comparison circuit 155. The switching circuit 160 sets the logical H level of the control signal for controlling at least one semiconductor switch in the charge pump booster circuit 110 and the output circuit 145 as the input voltage VDD and the output voltage according to the result of the comparison by the comparison circuit 155. Switch whether to generate using any of CPOUT.

The switching circuit 160 according to the present embodiment uses the higher voltage of the input voltage VDD and the output voltage CPOUT as the source of the control signal based on the signal UVDET_N from the comparison circuit 155. The voltage VDD_SEL is output. The switching circuit 160 may output either the input voltage VDD or the output voltage CPOUT as the voltage VDD_SEL based on the signal UVDET_N.

The drive circuit 165 is connected to the switching circuit 160. The drive circuit 165 inputs the clock signal CPCLK used for switching the charge pump booster circuit 110 and the positive transfer switch 150, and uses the voltage VDD_SEL output by the switching circuit 160 to control signals CHCP (a), CHCN (b), and Generates TRCN (c) and TRCP (d). The drive circuit 165 controls the control signals CHCP, CHCN, TRCN, and TRCP generated by using the voltage VDD_SEL to control the positive side charging switch 120, the negative side charging switch 130, the negative side transfer switch 135, and the positive side transfer switch 150. Supply to each terminal.

The gate control circuit 170 is connected to the input terminal VDD, the terminal CPP, and the comparison circuit 155. When the gate control circuit 170 outputs the boosted voltage from the terminal CPP of the charge pump booster circuit 110 as the output voltage CPOUT, the gate control circuit 170 boosts the control signal TRCP for the positive transfer switch 150 to boost the control signal TRCP of the positive transfer switch 150. And turn on the positive transfer switch 150.

FIG. 2 is a timing chart showing an example of the operation of the charge pump device 100 according to the present embodiment. In this figure, the output voltage CPOUT, the result of power supply monitoring by the comparison circuit 155 (value of signal UVDET_N), the state of current limitation by the current limiting circuits 140a to c, and the state of switching the power supply of the control signal by the switching circuit 160 are shown in this figure. , Each time change of the state of the gate control by the gate control circuit 170 is shown.

(1) Output voltage CPOUT
The charge pump device 100 is powered on at time 0 and starts operation. The drive circuit 165 repeats the charging phase and the transfer phase based on the clock signal CPCLK. In the charging phase, the drive circuit 165 turns on the positive charging switch 120 and the negative charging switch 130 with the control signals CHCP and CHCN as logical H, and the negative transfer switch 135 and the positive side with the control signals TRCN and TRCP as logical L. The transfer switch 150 is turned off. As a result, the terminal CPP of the first capacitor 115 is connected to the input terminal VDD, and the terminal CPN of the first capacitor 115 is connected to the ground VSS. As a result, the first capacitor 115 is gradually charged in the charging phase until the voltage across the first capacitor 115 reaches the input voltage VDD.

In the transfer phase, the drive circuit 165 turns off the positive charging switch 120 and the negative charging switch 130 with the control signals CHCP and CHCN as the logic L, and the negative transfer switch 135 and the positive side with the control signals TRCN and TRCP as the logic H. Turn on the transfer switch 150. As a result, the terminal CPN of the first capacitor 115 is connected to the input terminal VDD, and the terminal CPP of the first capacitor 115 is connected to the output terminal CPOUT. As a result, the boosted voltage whose input voltage VDD is boosted by the charging voltage of the first capacitor 115 is output to the output terminal CPOUT.

By repeating the charging phase and the transfer phase, the output voltage CPOUT rises, and at time t1, the output voltage CPOUT reaches the input voltage VDD. After time t1, the output voltage CPOUT rises above the input voltage VDD. The output voltage CPOUT reaches twice the input voltage VDD at the maximum.

When the output load current flowing through the load connected to the output terminal CPOUT becomes larger than the rated output current of the charge pump device 100, the output voltage CPOUT decreases. The charge pump device 100 according to the present embodiment applies a current limit to the charge pump in response to the drop of the output voltage CPOUT to the input voltage VDD or less, and lowers the drive capacity. Instead of this, the charge pump device 100 may be in a power-down state and stop the output.

(2) Power supply monitoring The comparison circuit 155 monitors the input voltage VDD and the output voltage CPOUT. In the comparison circuit 155, the signal UVDET_N is set to logic H while the output voltage CPOUT is equal to or lower than the input voltage VDD (between time 0 and time t1 and after time t2). The comparison circuit 155 uses the signal UVDET_N as the logic L while the output voltage CPOUT exceeds the input voltage VDD (between time t1 and time t2).

(3) Current limiting In the current limiting circuits 140a to c, the positive side charging switch 120 and the negative side charging are performed during the period when the output voltage CPOUT is lower than the input voltage VDD (between time 0 and time t1 and after time t2). Limits the current flowing through the switch 130 and the negative transfer switch 135. As a result, the current limiting circuits 140a to 140c can prevent an excessive inrush current from flowing to the first capacitor 115 during the start-up of the charge pump device 100, and when the load connected to the output terminal CPOUT is short-circuited. It is possible to prevent an overcurrent from flowing to the load.

(4) Power supply switching The switching circuit 160 outputs the input voltage VDD as the voltage VDD_SEL during the period when the output voltage CPOUT is equal to or less than the input voltage VDD (between time 0 and time t1 and after time t2). The switching circuit 160 outputs the output voltage CPOUT as the voltage VDD_SEL during the period when the output voltage CPOUT exceeds the input voltage VDD (between time t1 and time t2).

As described above, in the present embodiment, the nanotube switch is used as the positive side charging switch 120, the negative side transfer switch 135, and the positive side transfer switch 150. Here, the polyclonal switch can be turned on by setting the control voltage supplied to the control signal to the ground voltage VSS. However, in order to turn on the nanotube switch, the control voltage must be increased so that the gate-source voltage Vgs exceeds the threshold voltage. In the positive charging switch 120, when the first capacitor 115 is charged to near the input voltage VDD, the source voltage approaches the input voltage VDD. Therefore, in order to allow a sufficient current to flow through the positive charging switch 120, it is desirable that the control voltage (gate voltage) of the positive charging switch 120 be higher than the input signal VDD. Therefore, the switching circuit 160 sets the voltage of the signal VDD_SEL as the output voltage CPOUT in order to generate the control signal CHCP of the positive charging switch 120 by using the output voltage CPOUT boosted from the input voltage VDD during normal operation (in the figure). "CPOUT" from time t1 to time t2).

However, the output voltage CPOUT does not rise when the charge pump device 100 is started, and the output voltage CPOUT becomes 0V immediately after the charge pump device 100 is started. Therefore, when the output voltage CPOUT is equal to or lower than the input voltage VDD, the switching circuit 160 sets the voltage of the signal VDD_SEL as the input voltage VDD in order to generate the control signal CHCP of the positive charging switch 120 using the input voltage VDD (the input voltage VDD). “VDD” between time 0 and time t1 in the figure and after time t2).

Further, the negative transfer switch 135 is turned on in the transfer phase, and an output current is passed from the input terminal VDD to the output terminal CPOUT via the first capacitor 115 and the positive transfer switch 150. Since the negative transfer switch 135 connects the input terminal VDD and the terminal CPN in the ON state, the source voltage becomes substantially equal to the input voltage VDD. In order to pass a sufficient current to the negative transfer switch 135 in this state, the switching circuit 160 also uses the output voltage CPOUT to send the control signal TRCN to the control signal TRCN when the output voltage CPOUT exceeds the input voltage VDD. When the output voltage CPOUT is equal to or lower than the input voltage VDD, the control signal TRCN is generated by using the input voltage VDD.

In the present embodiment, the switching circuit 160 also generates the control signal CHCN of the negative charging switch 130 in the same manner. Since the source of the negative charging switch 130 is connected to the ground VSS, the drive circuit 165 may generate the control signal CHCN by always using the input voltage VDD without using the output voltage CPOUT.

(5) Gate control of the positive transfer switch 150 The positive transfer switch 150 is turned on in the transfer phase and connects between the output terminal CPOUT and the terminal CPP. Therefore, when the positive transfer switch 150 is on, the source voltage becomes substantially equal to the output voltage CPOUT. In order to allow sufficient current to flow through the positive transfer switch 150 in this state, the switching circuit 160 and the drive circuit 165 have an output voltage when the output voltage CPOUT exceeds the input voltage VDD (between time t1 and time t2). The control signal TRCP is generated using CPOUT, and the gate control circuit 170 boosts the control signal TRCP and supplies it to the positive transfer switch 150. When the output voltage CPOUT is equal to or less than the input voltage VDD (between time 0 and time t1 and after time t2), the switching circuit 160 and the drive circuit 165 generate a control signal TRCP using the input voltage VDD. The gate control circuit 170 boosts the control signal TRCP and supplies it to the positive transfer switch 150. Here, the gate control circuit 170 boosts the control signal TRCP using the input voltage VDD when the output voltage CPOUT exceeds the input voltage VDD, and the terminal when the output voltage CPOUT is equal to or lower than the input voltage VDD. The control signal TRCP may be boosted using the voltage of the CPP. The function and configuration of the gate control circuit 170 for this purpose will be described later in relation to FIG.

According to the charge pump device 100 shown above, depending on the result of comparing the input voltage VDD and the output voltage CPOUT, either the input voltage VDD or the output voltage CPOUT is used for the positive side charging switch 120 and the negative side transfer switch 135. , And whether to generate the control signal of the positive transfer switch 150 can be switched. As a result, the charge pump device 100 supplies a sufficiently high voltage control signal to the positive side charging switch 120, the negative side transfer switch 135, and even when the N channel FET or the like is used as the positive side transfer switch 150. Can be turned on.

In the present embodiment, the changeover circuit 160 uses either the input voltage VDD or the output voltage CPOUT to control signals for all of the positive side charging switch 120, the negative side transfer switch 135, and the positive side transfer switch 150. A configuration is adopted in which the voltage level of the logic H of is switched. Instead, the changeover circuit 160 generates a control signal using this technique only for at least one semiconductor switch of the positive charge switch 120, the negative transfer switch 135, and the positive transfer switch 150. You may try to do it. In this case, the remaining semiconductor switch may be a P-channel FET.

FIG. 3 shows the configuration of the switching circuit 160 according to the present embodiment. The switching circuit 160 includes a logic denial element 310, a level shifter 320, a semiconductor switch MP_CPO, a semiconductor switch MP_B1, a semiconductor switch MP_B2, a semiconductor switch MP_ VDD, a semiconductor switch MP_B3, and a semiconductor switch MP_B4.

The logic negative element 310 inverts the logical value of the signal UVDET_N and outputs an inverted value which becomes logic L when the output voltage CPOUT is equal to or less than the input voltage VDD and becomes logic H when the output voltage CPOUT exceeds the input voltage VDD. do. The level shifter 320 is connected to the logic denial element 310. The level shifter 320 inputs the output voltage CPOUT and level-shifts the inverted value of the signal UVDET_N taking the voltage VDD and the voltage VSS to the signal UVDET_LS taking the voltage CPOUT and the voltage VSS. Here, the level shifter 320 can output the logic L even when the output voltage CPOUT is equal to or lower than the input voltage VDD.

In the semiconductor switch MP_CPO, the main terminals are connected between the output terminal CPOUT and the output terminal of the voltage VDD_SEL. The semiconductor switch MP_CPO inputs the signal UVDET_N to the control terminal, and is turned off when the signal UVDET_N is logic H (output voltage CPOUT ≦ input voltage VDD). Further, the semiconductor switch MP_CPO is turned on when the signal UVDET_N is a logic L (output voltage CPOUT> input voltage VDD), and outputs the output voltage CPOUT as the voltage VDD_SEL.

In the semiconductor switches MP_B1 and MP_B2, the main terminals are connected between the terminal on the output terminal CPOUT side of the semiconductor switch MP_CPO and the bulk, and between the terminal on the drive circuit 165 side and the bulk of the semiconductor switch MP_CPO. When the signal UVDET_N is logical H and the signal UVDET_LS is logical L (output voltage CPOUT ≤ input voltage VDD), the semiconductor switch MP_B1 is off, the semiconductor switch MP_B2 is on, and the bulk voltage of the semiconductor switch MP_CPO is the voltage on the drive circuit 165 side. Become. When the signal UVDET_N is logical L and the signal UVDET_LS is logical H (output voltage CPOUT> input voltage VDD), the semiconductor switch MP_B1 is on, the semiconductor switch MP_B2 is off, and the bulk voltage of the semiconductor switch MP_CPO is the voltage on the output terminal CPOUT side. Become.

The semiconductor switch MP_ VDD is connected between the main terminals of the input terminal VDD and the output terminal of the voltage VDD_SEL in the switching circuit 160. The semiconductor switch MP_ldap inputs the signal UVDET_LS to the control terminal, and is turned off when the signal UVDET_LS is logic H (output voltage CPOUT> input voltage VDD). Further, the semiconductor switch MP_ VDD is turned on when the signal UVDET_LS is a logic L (output voltage CPOUT ≦ input voltage VDD), and the input voltage VDD is output as the voltage VDD_SEL.

In the semiconductor switches MP_B3 and MP_B4, the main terminals are connected between the input terminal VDD side and the bulk of the semiconductor switch MP_ VDD, and between the drive circuit 165 side and the bulk of the semiconductor switch MP_ VDD. When the signal UVDET_N is logical H and the signal UVDET_LS is logical L (output voltage CPOUT ≤ input voltage VDD), the semiconductor switch MP_B3 is on, the semiconductor switch MP_B4 is off, and the bulk voltage of the semiconductor switch MP_ VDD is the voltage on the input terminal VDD side. Become. When the signal UVDET_N is logical L and the signal UVDET_LS is logical H (output voltage CPOUT> input voltage VDD), the semiconductor switch MP_B3 is off, the semiconductor switch MP_B4 is on, and the bulk voltage of the semiconductor switch MP_ VDD is the voltage on the output terminal CPOUT side. Become.

According to the switching circuit 160 shown above, the voltage VDD_SEL can be set as the output voltage CPOUT when the signal UVDET_N is the logic L, and the voltage VDD_SEL can be set as the input voltage VDD when the signal UVDET_N is the logic H. In the present embodiment, the switching circuit 160 uses P-channel MOSFETs as the semiconductor switches MP_CPO, MP_ VDD, and MP_B1 to MP_B1-4. Since these semiconductor switches do not carry a large current to be supplied to the load unlike the positive side charging switch 120, the negative side transfer switch 135, and the positive side transfer switch 150, the positive side charging switch 120 and the negative side transfer switch It can be realized with a very small size compared to 135 and the positive transfer switch 150. Therefore, by using the positive side charging switch 120, the negative side transfer switch 135, and the positive side transfer switch 150 as N-channel FETs, the size of the charge pump device 100 is still reduced even if a circuit such as a switching circuit 160 is added. be able to.

FIG. 4 shows the configuration of the drive circuit 165 according to the present embodiment. The drive circuit 165 has a timing generator 410 and a clock buffer unit 420.

The timing generator 410 inputs the clock signal CPCLK and generates control signals for the positive side charging switch 120, the negative side charging switch 130, the negative side transfer switch 135, and the positive side transfer switch 150. In the control signal generated by the timing generator 410, the voltage VDD is the logic H and the voltage VSS is the logic L. In the charging phase, the timing generator 410 has the control signal for the positive side charging switch 120 and the negative side charging switch 130 as logic H, and the control signal for the negative side transfer switch 135 and the positive side transfer switch 150 as logic L. .. Further, in the transfer phase, the timing generator 410 uses the control signal for the positive side charging switch 120 and the negative side charging switch 130 as the logic L, and the control signal for the negative side transfer switch 135 and the positive side transfer switch 150 as the logic H. And.

The clock buffer unit 420 is connected to the timing generator 410. The clock buffer unit 420 inputs the voltage VDD_SEL, and converts the voltage level of the control signal output by the timing generator 410 using the voltage VDD_SEL. The clock buffer unit 420 includes buffers 430a to 430a to d. In the buffers 430a to 430, the voltage of the logic H of the input control signal is level-converted to the voltage VDD_SEL, the voltage VDD_SEL is the logic H, and the voltage VSS is the logic L, and the control signal CHCP (“a” in FIG. 1). , CHCN (“b” in FIG. 1), TRCN (“c” in FIG. 1), and TRCP (“d” in FIG. 1) are output.

FIG. 5 is a timing chart showing an example of the operation of the drive circuit 165 according to the present embodiment. The upper part of this figure shows the time change of the voltage of the control signals CHCP and CHCN, and the lower part of this figure shows the time change of the voltage of the control signals TRCP and TRCN.

In the drive circuit 165, the control signals CHCP and CHCN and the control signals TRCP and TRCN are alternately set as logic H. Here, when the output voltage CPOUT is equal to or less than the input voltage VDD (between time 0 and time t1 in the figure), the buffers 430a to d input the input voltage VDD as the voltage VDD_SEL, and the logic H becomes the input voltage VDD. Output the control signal. When the output voltage CPOUT exceeds the input voltage VDD (time t2 or later in the figure), the buffers 430a to 430 input the output voltage CPOUT as the voltage VDD_SEL, and output a control signal in which the logic H becomes the output voltage CPOUT. In this way, the drive circuit 165 turns on the positive side charging switch 120, the negative side charging switch 130, the negative side transfer switch 135, and the positive side transfer switch 150 by using the voltage VDD_SEL output from the switching circuit 160. A control signal can be generated.

FIG. 6 shows the configuration of the gate control circuit 170 according to the present embodiment. The gate control circuit 170 uses the input voltage VDD to charge the offset voltage during at least a portion of the off period of the positive transfer switch 150. Then, when the positive transfer switch 150 is turned on, the gate control circuit 170 applies an offset voltage to the voltage of the control signal TRCP for the positive transfer switch 150 and supplies the offset voltage to the control terminal of the positive transfer switch 150.

The gate control circuit 170 includes a second capacitor 610 and a rectifying element 620. One end (negative terminal) of the second capacitor 610 is connected to the buffer 430d to input a control signal TRCP, and the other end (positive terminal) is connected to the control terminal of the positive transfer switch 150. .. The rectifying element 620 is connected between the input terminal VDD and the other end of the second capacitor 610.

FIG. 7 is a timing chart showing an example of the operation of the gate control circuit 170 according to the present embodiment. In this figure, in order from the top, the time of each voltage of the control signals CHCP and CHCN, the control signals TRCP and TRCN, the terminal CPP, and the boosted control signal supplied to the control terminal (gate) of the positive transfer switch 150. Show change.

In the charging phase, the drive circuit 165 has the control signals CHCP and CHCN as logic H and the control signals TRCP and TRCN as logic L. As a result, the positive charging switch 120 and the negative charging switch 130 are turned on, and the negative transfer switch 135 and the positive transfer switch 150 are turned off. As a result, the input voltage VDD is charged to the first capacitor 115, and the voltage of the terminal CPP becomes substantially the same as the input voltage VDD.

In the charging phase, the second capacitor 610 inputs the control signal TRCP of the logic L (voltage VSS) to one end, and inputs the input voltage VDD to the other end via the rectifying element 620. As a result, the second capacitor 610 charges the input voltage VDD as an offset voltage.

In the transfer phase, the drive circuit 165 has the control signals CHCP and CHCN as logic L and the control signals TRCP and TRCN as logic H. When the output voltage CPOUT exceeds the input voltage VDD, the gate control circuit 170 inputs the output voltage CPOUT to one end of the second capacitor 610 as the control signal TRCP of the logic H. As a result, a control signal whose output voltage CPOUT is boosted by the offset voltage charged in the second capacitor 610 is supplied to the control terminal of the positive transfer switch 150. The rectifying element 620 causes a current to flow in the direction from the input terminal VDD to the other end of the second capacitor 610, and prevents a backflow of the current from the other end of the second capacitor 610 to the input terminal VDD.

Since the positive transfer switch 150 has a parasitic capacitance at the gate, the parasitic capacitance of the second capacitor 610 and the positive transfer switch 150 depends on the output voltage CPOUT at one end of the second capacitor 610. Charges are redistributed between them. As a result, the control terminal of the positive transfer switch 150 becomes the voltage CPOUT + VDD × α obtained by adding the voltage VDD × α (0 <α <1) obtained by redistributing the offset voltage VDD to the output voltage CPOUT.

According to 170 shown above, while charging the input voltage VDD to the second capacitor 610 in the charging phase, the control signal of the voltage VDD is supplied to the control terminal of the positive transfer switch 150. Here, since the source of the positive transfer switch 150 is the input voltage VDD in the charging phase, the positive transfer switch 150 can be sufficiently turned off without dropping the control terminal to the voltage VSS. Then, by supplying the voltage VDD to the control terminal in the charging phase, the gate control circuit 170 can be in a state where the parasitic capacitance of the positive transfer switch 150 is charged to the amount corresponding to the voltage VDD. As a result, the gate control circuit 170 does not need to charge the parasitic capacitance of the positive transfer switch 150 from the amount equivalent to the voltage VSS due to the redistributing of the charge in the transfer phase, and the second capacitor 610 having a relatively small capacitance is used. It is possible to sufficiently boost the voltage of the control terminal.

Further, by inputting the control signal TRCP from the buffer 430d to one end of the second capacitor 610, the gate control circuit 170 is a semiconductor switch or the like for supplying an offset voltage from the second capacitor 610 to the positive transfer switch 150. It is not necessary to provide such a semiconductor switch, and it is possible to eliminate the need for timing control of such a semiconductor switch.

FIG. 8 shows the configuration of the current limiting circuits 140a to 140 according to the present embodiment together with the positive side charging switch 120, the negative side charging switch 130, and the negative side transfer switch 135. In the present embodiment, the positive charging switch 120 has a plurality of positive charging switches 120a to 120 connected in parallel. The positive charging switch 120a, which is a part of the plurality of positive charging switches 120a to 120b, inputs the control signal CHCP to the control terminal and switches on / off according to the control signal CHCP. The remaining positive charging switches 120b among the plurality of positive charging switches 120a to 120b input the output of the current limiting circuit 140a to the control terminal and switch on / off according to the output of the current limiting circuit 140a.

The current limiting circuit 140a inputs the control signal CHCP from the drive circuit 165 and the signal UVDET_N from the comparison circuit 155. The current limiting circuit 140a forcibly sets the control signal CHCP to the logic L when the signal UVDET_N is the logic H (when the output voltage CPOUT ≦ the input voltage VDD). As a result, the current limiting circuit 140a prevents the positive side charging switch 120b from being turned on in response to the output voltage CPOUT being lower than the input voltage VDD, and the first input terminal VDD in the charge pump booster circuit 110. Limits the current flowing into the capacitor 115.

The current limiting circuit 140a according to the present embodiment includes a NOR element that takes a NOR of the inverted value of the control signal CHCP and the signal UVDET_N. As a result, when the signal UVDET_N is the logic H, the current limiting circuit 140a outputs the logic L regardless of the logic value of the control signal CHCP.

The negative charging switch 130 has a plurality of negative charging switches 130a to 130 connected in parallel. The negative charging switch 130a, which is a part of the plurality of negative charging switches 130a to 130b, inputs the control signal CHCN to the control terminal and switches on / off according to the control signal CHCN. The remaining negative charging switches 130b among the plurality of negative charging switches 130a to 130b input the output of the current limiting circuit 140b to the control terminal, and switch on / off according to the output of the current limiting circuit 140b.

The current limiting circuit 140b inputs the control signal CHCN from the drive circuit 165 and the signal UVDET_N from the comparison circuit 155. The current limiting circuit 140b forcibly sets the control signal CHCN to the logic L when the signal UVDET_N is the logic H (when the output voltage CPOUT ≦ the input voltage VDD). As a result, the current limiting circuit 140b prevents the negative charging switch 130b from being turned on in response to the output voltage CPOUT being lower than the input voltage VDD, and the first input terminal VDD in the charge pump booster circuit 110. Limits the current flowing into the capacitor 115. Since the configuration of the current limiting circuit 140b is the same as that of the current limiting circuit 140a, the description thereof will be omitted.

The negative transfer switch 135 has a plurality of negative transfer switches 135a to 135 connected in parallel. The negative transfer switch 135a, which is a part of the plurality of negative transfer switches 135a to b, inputs the control signal TRCN to the control terminal and switches on / off according to the control signal TRCN. The remaining negative transfer switch 135b of the plurality of negative transfer switches 135a to b inputs the output of the current limiting circuit 140c to the control terminal, and switches on / off according to the output of the current limiting circuit 140c.

The current limiting circuit 140c inputs the control signal TRCN from the drive circuit 165 and the signal UVDET_N from the comparison circuit 155. The current limiting circuit 140c forcibly sets the control signal TRCN to the logic L when the signal UVDET_N is the logic H (when the output voltage CPOUT ≦ the input voltage VDD). As a result, the current limiting circuit 140c prevents the negative transfer switch 135b from being turned on in response to the output voltage CPOUT being lower than the input voltage VDD, so that the negative transfer switch 135, the first capacitor 115, and the output The current output from the terminal CPP to the output terminal CPOUT via the circuit 145 is limited. Since the configuration of the current limiting circuit 140c is the same as that of the current limiting circuit 140a, the description thereof will be omitted.

According to the current limiting circuits 140a to 140c shown above, the positive side charging switch 120 including the semiconductor switches connected in parallel, the negative side charging switch 130, depending on the output voltage CPOUT lower than the input voltage VDD. And prevent the semiconductor switch of each part of the negative transfer switch 135 from being turned on. As a result, in the current limiting circuits 140a to c, the current input by the charge pump booster circuit 110 from the input terminal VDD or the charge pump booster circuit 110 outputs from the terminal CPP according to the output voltage CPOUT lower than the input voltage VDD. The operation of the charge pump device 100 can be stabilized by limiting at least one of the currents output to the circuit 145.

FIG. 9 shows the configuration of the gate control circuit 900 according to the first modification of the present embodiment. The gate control circuit 900 is a first modification of the gate control circuit 170 shown in FIG. The gate control circuit 900 includes a second capacitor 910 and a rectifying element 920. Since the second capacitor 910 is the same as the second capacitor 610 of FIG. 6, the description thereof will be omitted.

In the rectifying element 920, the main terminals are connected between the input terminal VDD and the other end (terminal on the positive side) of the second capacitor 610. More specifically, the rectifying element 920 is an N-channel FET in which the source is connected to the input terminal VDD side, the drain is connected to the second capacitor 910 side, and the gate (control terminal) is connected to the input terminal VDD. With such a configuration, when the voltage at the other end of the second capacitor 910 is equal to or less than VDD, the rectifying element 920 causes a current to flow from the input terminal VDD to the other end of the second capacitor 910, and other than the second capacitor 910. When the voltage at the end exceeds VDD, the backflow of current from the other end of the second capacitor 910 to the input terminal VDD is prevented.

FIG. 10 shows the configuration of the gate control circuit 1000 according to the second modification of the present embodiment. The gate control circuit 1000 is a second modification of the gate control circuit 170 shown in FIG. The gate control circuit 1000 includes a second capacitor 1010, a rectifying element 1020, a switch 1030, and a switch 1040. Since the second capacitor 1010 and the rectifying element 1020 are the same as the second capacitor 910 and the rectifying element 920 of FIG. 9, the description thereof will be omitted.

The switch 1030 receives a power-down signal PD at the gate, with the main terminals connected between the input terminal VDD and the rectifying element 1020. The switch 1030 according to the present embodiment is a P-channel FET as an example. Here, the power-down signal PD is the logic L during the operation of the charge pump device 100, and is set to the logic H before the power of the charge pump device 100 is turned off. While the power-down signal PD is logical L, the switch 1030 is turned on. As a result, the switch 1030 supplies the input voltage VDD to the node GATE_DI during the normal operation of the charge pump device 100. As a result, the gate control circuit 1000 functions in the same manner as the gate control circuit 900. When the power-down signal PD becomes logic H, the switch 1030 is turned off. As a result, the switch 1030 cuts off the supply of the input voltage VDD to the second capacitor 1010 before the power of the charge pump device 100 is turned off.

In switch 1040, the positive main terminal (drain as an example) is connected to the node GATE_DI between the rectifying element 1020 and the switch 1030, and the negative main terminal (source as an example) is connected to the ground VSS to power the gate. Receives a down signal PD. The switch 1040 according to the present embodiment is an N-channel FET as an example. While the power-down signal is logical L, the switch 1040 is turned off. As a result, the switch 1040 cuts off between the node GATE_DI and the ground VSS during the normal operation of the charge pump device 100. When the power-down signal PD becomes logic H, the switch 1040 is turned on. Thereby, the switch 1040 connects the node GATE_DI to the ground VSS before the power of the charge pump device 100 is turned off.

Here, when the node GATE_DI becomes the ground voltage VSS, the gate voltage of the rectifying element 1020 becomes VDD and the source voltage becomes VSS, and the rectifying element 1020 is turned on. As a result, the rectifying element 1020 can discharge the electric charge charged in the second capacitor 1010 via the switch 1040 before the power of the charge pump device 100 is turned off.

FIG. 11 shows the configuration of the gate control circuit 1100 according to the third modification of the present embodiment. The gate control circuit 1100 is a third modification of the gate control circuit 170 shown in FIG. The gate control circuit 1100 includes a second capacitor 1110, a rectifying element 1120, a switch 1130, and a switch 1140. Since the second capacitor 1110 and the rectifying element 1120 are the same as the second capacitor 1010 and the rectifying element 1020 in FIG. 10, the description thereof will be omitted.

The switch 1130 is connected between the main terminals and between the input terminal VDD and the rectifying element 1120, and receives the signal UVDET_N at the gate. The switch 1130 according to the present embodiment is a P-channel FET as an example. When the signal UVDET_N is logic L (output voltage CPOUT> input voltage VDD), the switch 1130 is turned on. As a result, the switch 1130 operates with the node GATE_DI as the voltage VDD and the gate control circuit 1100 in the same manner as the gate control circuit 900 of FIG. 9 while the charge pump device 100 outputs the output voltage CPOUT exceeding the input voltage VDD. Can be made to. When the signal UVDET_N is logic H (when the output voltage CPOUT ≦ the input voltage VDD), the switch 1130 is turned off.

In switch 1140, the positive main terminal (drain as an example) is connected to the terminal CPP, the negative main terminal (source as an example) is connected to the node GATE_DI between the rectifying element 1120 and the switch 1130, and the signal UVDET_N is sent to the gate. receive. The switch 1140 according to the present embodiment is an N-channel FET as an example. When the signal UVDET_N is the logic L (when the output voltage CPOUT> the input voltage VDD), the switch 1040 is turned off. When the signal UVDET_N is logic H (when the output voltage CPOUT ≦ the input voltage VDD), the switch 1140 is turned on. As a result, the switch 1140 supplies the voltage of the terminal CPP to the node GATE_DI during the activation of the charge pump device 100 and before the power of the charge pump device 100 is turned off.

As a result, the gate control circuit 1100 supplies the voltage of the terminal CPP to the second capacitor 1110 when the output voltage CPOUT is equal to or lower than the input voltage VDD, as shown in the timing chart of “gate control” in FIG. be able to. As a result, in the charging phase, the gate and source voltages of the positive transfer switch 150 both become the voltage of the terminal CPP, and the gate-source voltage Vgs becomes substantially 0, so that the positive transfer switch 150 is in the off state. Become. Therefore, the gate control circuit 1100 can turn off the positive transfer switch 150 even when the voltage of the terminal CPP is low immediately after switching to the charging phase or the like.

In the transfer phase, the gate of the positive transfer switch 150 is boosted by the voltage of the terminal CPP with respect to the output voltage CPOUT, so that the positive transfer switch 150 is turned on. Further, the charge pump device 100 may have a function of being in a power-down state and lowering the terminal CPP to the ground voltage VSS before the power is turned off. As a result, the switch 1140 can discharge the second capacitor 1110 via the rectifying element 1120 in the power-down state.

FIG. 12 shows the configuration of the gate control circuit 1200 according to the fourth modification of the present embodiment together with the positive transfer switches 150a to 150b. In this modification, the positive transfer switch 150 has a plurality of positive transfer switches 150a to 150 connected in parallel. The positive transfer switch 150a, which is a part of the plurality of positive transfer switches 150a to 150b, inputs the control signal TRCP to the control terminal and switches on / off according to the control signal TRCP. The remaining positive transfer switches 150b among the plurality of positive transfer switches 150a to 150b input the output of the current limiting circuit 1250 to the control terminal and switch on / off according to the output of the current limiting circuit 1250.

The gate control circuit 1200 is a fourth modification of the gate control circuit 170 shown in FIG. 6, and has a function of limiting the current flowing through the positive transfer switch 150 added to the gate control circuit 1100 of FIG. The gate control circuit 1200 includes a plurality of second capacitors 1210a to b, a plurality of rectifying elements 1220a to b, a switch 1230, a switch 1240, and a current limiting circuit 1250.

Each of the plurality of second capacitors 1210a to 1210 is the same as the second capacitor 1110 in FIG. 11 except that the output of the current limiting circuit 1250 is input to one end of the second capacitor 1210b instead of the control signal TRCP. Since there is, the explanation is omitted. Each of the plurality of rectifying elements 1220a to 122b is the same as the rectifying element 1120 of FIG. 11, except that each of the plurality of rectifying elements 1220a to 1210b is provided corresponding to each of the plurality of second capacitors 1210a to b, and thus the description thereof will be omitted. Further, since the switch 1230 and the switch 1240 are the same as the switch 1130 and the switch 1140 in FIG. 11, the description thereof will be omitted.

The current limiting circuit 1250 inputs the control signal TRCP from the drive circuit 165 and the signal UVDET_N from the comparison circuit 155. When the signal UVDET_N is the logic H (when the output voltage CPOUT ≦ the input voltage VDD), the current limiting circuit 1250 forcibly supplies the control signal TRCP as the logic L to the second capacitor 1210b. As a result, the current limiting circuit 1250 flows out from the charge pump booster circuit 110 to the output terminal CPOUT so that the positive transfer switch 150b is not turned on in response to the output voltage CPOUT being lower than the input voltage VDD. Limit the current.

The current limiting circuit 1250 according to this modification includes a NOR element that takes a NOR of the inverted value of the control signal TRCP and the signal UVDET_N. As a result, when the signal UVDET_N is the logic H, the current limiting circuit 1250 outputs the logic L regardless of the logic value of the control signal TRCP.

According to the gate control circuit 1200 shown above, the current flowing out from the charge pump booster circuit 110 to the output terminal CPOUT is limited according to the fact that the output voltage CPOUT is lower than the input voltage VDD. As a result, the gate control circuit 1200 can stabilize the operation of the charge pump device 100 at startup and prevent the first capacitor 115 from being over-discharged.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the form with such changes or improvements may be included in the technical scope of the present invention.

The order of execution of each process such as operation, procedure, step, and step in the apparatus, system, program, and method shown in the claims, specification, and drawings is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

100 charge pump device, 110 charge pump booster circuit, 115 first capacitor, 120 positive side charge switch, 125 bulk control circuit, 130 negative side charge switch, 135 negative side transfer switch, 140a-c current limit circuit, 145 output circuit, 150 forward transfer switch, 155 comparison circuit, 160 switching circuit, 165 drive circuit, 170 gate control circuit, 310 logic negative element, 320 level shifter, 410 timing generator, 420 clock buffer section, 430a to d buffer, 610 second capacitor , 620 rectifying element, 900 gate control circuit, 910 second capacitor, 920 rectifying element, 1000 gate control circuit, 1010 second capacitor, 1020 rectifying element, 1030 switch, 1040 switch, 1100 gate control circuit, 1110 second capacitor, 1120 Rectifier element, 1130 switch, 1140 switch, 1200 gate control circuit, 1210a-b second capacitor, 1220a-b rectifier element, 1230 switch, 1240 switch, 1250 current limiting circuit

Claims (11)

A charge pump booster circuit that outputs a boosted voltage that boosts the input voltage input from the input terminal,
An output circuit that outputs the boosted voltage as an output voltage,
A comparison circuit that compares the input voltage and the output voltage,
A switching circuit that switches whether to generate a control signal for controlling at least one semiconductor switch in the charge pump booster circuit using either the input voltage or the output voltage according to the result of the comparison. Charge pump device equipped. The charge pump device according to claim 1, wherein the switching circuit uses a higher voltage of the input voltage and the output voltage to generate the control signal. The switching circuit outputs either the input voltage or the output voltage according to the result of the comparison.
The charge pump device according to claim 1 or 2, further comprising a drive circuit that generates the control signal using the voltage output by the switching circuit. The at least one semiconductor switch is an N-type MOSFET.
The charge pump device according to claim 3, wherein the drive circuit uses a voltage output by the switching circuit to generate the control signal for turning on the at least one semiconductor switch. The charge pump booster circuit
With the first capacitor
A positive charging switch, which is a semiconductor switch connected between the input terminal and one end of the first capacitor,
A negative charging switch, which is a semiconductor switch connected between the other end of the first capacitor and the ground,
It has a negative transfer switch, which is a semiconductor switch connected between the input terminal and the other end of the first capacitor.
The charge according to claim 3 or 4, wherein the drive circuit supplies a control signal generated by using the voltage output by the changeover circuit to at least one control terminal of the positive side charge switch or the negative side transfer switch. Pump device. The output circuit has a positive transfer switch which is a semiconductor switch for switching whether or not to output the boosted voltage as the output voltage.
Any of claims 1 to 5, further comprising a gate control circuit that boosts the control signal for the positive transfer switch and supplies it to the control terminal of the positive transfer switch when the boost voltage is output as the output voltage. The charge pump device according to item 1. The gate control circuit is
During at least a portion of the positive transfer switch off period, the input voltage is used to charge the offset voltage.
The charge pump device according to claim 6, wherein when the positive transfer switch is turned on, the offset voltage is added to the voltage of the control signal for the positive transfer switch and supplied to the control terminal of the positive transfer switch. .. A charge pump booster circuit that outputs a boosted voltage that boosts the input voltage input from the input terminal,
An output circuit having a positive transfer switch for switching whether or not to output the boosted voltage as an output voltage, and
When the offset voltage is charged using the input voltage during at least a part of the off period of the positive transfer switch and the positive transfer switch is turned on, the voltage of the control signal for the positive transfer switch is changed to the voltage of the control signal. A charge pump device including a gate control circuit that applies an offset voltage and supplies it to the control terminal of the positive transfer switch. The gate control circuit is
A second capacitor in which a control signal for the positive transfer switch is input to one end and the other end is connected to the control terminal of the positive transfer switch.
Any one of claims 6 to 8 having a rectifying element connected between the input terminal and the other end of the second capacitor and preventing backflow of current from the other end of the second capacitor to the input terminal. The charge pump device described in the section. The charge pump device according to any one of claims 6 to 9, wherein the positive transfer switch is an N-type MOSFET. From claim 1, the present invention comprises a current limiting circuit that limits at least one of a current input by the charge pump booster circuit or a current output by the charge pump booster circuit depending on whether the output voltage is lower than the input voltage. The charge pump device according to any one of 10.

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