JPH0865131A - Output circuit - Google Patents

Abstract

PURPOSE: To prevent decrease in the operating speed, increase in power consumption and occurrence of a fault or the like in advance corresponding to the application of a different power supply voltage. CONSTITUTION: A pull-up output transistor(TR) 1 and a pull-down output TR 2 are connected in series between a high potential power supply and a low potential power supply. Drains of the TRs 1, 2 are connected to an output terminal To, input signals IN1, IN2 are given to gates of the TRs 1, 2, an output signal OUT is outputted from an output terminal To, and either the power supply Vcc supplied to an internal circuit or a power supply VccQ whose level is higher than the level of the power supply Vcc is applied to the source of the TR 1. A power supply changeover circuit 2 applying the power supply Vcc when the output signal OUT is at an H or an L level and applying the power supply VccQ when the output signal OUT is in a high impedance state is connected to the source of the TR 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of a semiconductor device. Recent semiconductor devices are 5V to 3
The power supply voltage is being reduced to V. In such a situation, a large number of semiconductor devices that constitute one system coexist with those that operate at a power supply voltage of 5V and those that operate at a power supply voltage of 3V. Therefore, in order to output the output signal of the semiconductor device which operates at the power supply voltage of 3V to the semiconductor device which operates at the power supply voltage of 5V, the internal circuit operates at the power supply voltage of 3V and is based on the power supply voltage of 5V. An output circuit that outputs an output signal is required.

[0002]

2. Description of the Related Art A conventional example of a semiconductor device used in a system in which power supply voltages of 3 V and 5 V are used together will be described with reference to FIG. 3, in which an input signal IN is input to inverter circuits 1a and 1b.

The output signal of the inverter circuit 1a is passed through the inverter circuits 1c to 1e and the pull-up side output transistor T which is a P-channel MOS transistor.
It is output to the gate of r1.

The inverter circuits 1a to 1e are connected as a high potential side power source to a 3V power source Vcc, and the inverter circuits 1a, 1d and 1e are connected as a low potential side power source to the ground GND. Further, either the power supply Vcc of 3V or the power supply VccQ of 5V is supplied to the source of the output transistor Tr1.

The inverter circuit 1c is an N channel MO.
It is connected to the ground GND through the S transistor Tr3, and the output terminal of the inverter circuit 1c is a P channel M
It is connected to the power supply Vcc through the OS transistor Tr4.
The output control signal C is input to the gates of the transistors Tr3 and Tr4.

The output signal of the inverter circuit 1b is passed through the inverter circuits 1f to 1h to the pull-down side output transistor T which is an N-channel MOS transistor.
It is output to the gate of r2.

The inverter circuits 1b and 1f to 1h are
The low potential side power source is connected to the ground GND, and the inverter circuits 1b, 1g, 1h are 3V as the high potential side power source.
Is connected to the power source Vcc. Also, the output transistor Tr2
Source is connected to the ground GND.

The inverter circuit 1f is a P channel MO.
It is connected to the power supply Vcc via the S transistor Tr5, and the output terminal of the inverter circuit 1f is connected to the ground GND via the N channel MOS transistor Tr6. The output control signal C is input to the gates of the transistors Tr5 and Tr6.

The drains of the output transistors Tr1 and Tr2 are connected to the output terminal To, and the output signal OUT is output from the output terminal To. In the output circuit configured as described above, when the output control signal C becomes L level and the output control signal / C becomes H level, the gate of the output transistor Tr1 becomes H level regardless of the input signal IN, and The gate of the output transistor Tr2 becomes L level.

Therefore, the output transistors Tr1 and Tr2 are both turned off, and the output signal OUT is in a high impedance state. With the output control signal C at the H level and the output control signal / bar C at the L level, the input signal I
When N becomes H level, the output signals of the inverter circuits 1e and 1h become H level.

Then, the output transistor Tr1 is turned off and the output transistor Tr2 is turned on to output the output signal OU.
T becomes L level. On the other hand, when the input signal IN becomes L level, the output signals of the inverter circuits 1e and 1h become L level.

Then, the output transistor Tr1 is turned on, the output transistor Tr2 is turned off, and the output signal OU is output.
T becomes H level. At this time, when the semiconductor device to which the output signal OUT is input is operating with the power supply VccQ of 5V, the power supply VccQ is supplied to the source of the output transistor Tr1 and the output signal OUT of H level becomes approximately 5V. .

Further, when the semiconductor device outputting the output signal OUT is operated by the power supply Vcc of 3V, the power supply Vcc is supplied to the source of the output transistor Tr1 so that the H level output signal OUT is almost 3V. Becomes

[0014]

In the output circuit described above, the source of the output transistor Tr1 has a power supply Vcc of 3V.
In some cases, a voltage of 5 V from the power source VccQ may be applied to the data bus line connected to the output terminal To while supplying and using.

In such a case, the output transistor T
When an H-level signal is input to the gate of r1 and the output transistor Tr1 must be turned off, the potential of the output terminal To becomes higher than the gate potential by about 2V.

Therefore, a current flows from the output terminal To to the power supply Vcc, or a current flows from the output terminal To to the substrate via the output transistor Tr1. As a result, it may adversely affect other internal circuits or cause a failure.

When the source of the output transistor Tr1 is supplied with the power supply VccQ and is used, when the input signal IN becomes H level and the output signals of the inverter circuits 1e and 1h both become H level, the inverter circuit becomes. 1e, 1
Since h operates on the power supply Vcc, the output transistor T
The potential difference between the source and gate of r1 is about 2V.

Then, since the output transistor Tr1 to be turned off is turned on and the output transistor Tr2 is turned on, a through current flows from the power supply VccQ to the ground GND, and power consumption increases. Further, there is a problem in that the operation speed is reduced due to the inability to output the L-level output signal OUT and the decrease in the falling speed of the output signal OUT.

An object of the present invention is to provide an output circuit capable of preventing problems such as a decrease in operating speed, an increase in power consumption, and occurrence of a failure while dealing with different power supply voltages.

[0020]

FIG. 1 is a diagram illustrating the principle of the present invention. That is, a pull-up side output transistor Tr1 composed of a P-channel MOS transistor and a pull-down side output transistor Tr2 composed of an N-channel MOS transistor are connected in series between the high potential side power source and the low potential side power source. To be done. The drains of the pull-up side output transistor Tr1 and the pull-down side output transistor Tr2 are connected to the output terminal To, and the input signals IN1 and 1N2 are input to the gates of the pull-up side output transistor Tr1 and the pull-down side output transistor Tr2.
An output signal OUT is output from the output terminal To, and the source of the pull-up side output transistor Tr1 has a first power supply voltage Vcc supplied to an internal circuit and a second power supply voltage higher than the first power supply voltage Vcc. One of the power supply voltage VccQ is supplied as the high potential side power supply. The output signal O is connected to the source of the pull-up side output transistor Tr1.
A power supply switching circuit 2 that supplies the first power supply voltage Vcc when the UT becomes the H level or the L level and supplies the second power supply voltage VccQ when the output signal OUT becomes the high impedance is connected.

Further, each of the output transistors Tr1 and Tr2 is
Is output by the output control circuit that operates based on the output control signals C and C input from the outside.
Is set to H level or L level based on the input signal IN or high impedance regardless of the input signal IN, and the power supply switching circuit 2 is based on the output control signal C. The second power supply voltage Vcc, VccQ is switched.

Further, each of the output transistors Tr1 and Tr2 is
To the pull-up side output transistor Tr1 and the preceding inverter circuit 1e based on the output control signal C. Either the first or second power supply voltage Vcc or VccQ is supplied.

The power supply switching circuit 2 outputs the first and second power supply voltages Vcc and VccQ to the pull-up side output transistor Tr1 via the first and second switch circuits Tr8 and Tr9, and the preceding stage thereof. Of the first and second switch circuits Tr8 and Tr9 are closed and the other is opened based on the output control signal C.

The first and second switch circuits have P-channel MOS transistors Tr8 and Tr9 whose complementary signals are input to their gates based on the output control signal C.
Composed of.

[0025]

Operation: Output signal O based on input signals IN1 and IN2
When UT becomes H level or L level, the first power supply voltage Vcc is supplied to the source of the pull-up side output transistor Tr1 as the high-potential side power supply, so when the output signal OUT is L level output, pull-up is performed. The side output transistor Tr1 is surely turned off. When the output signal OUT has a high impedance, the source of the pull-up side output transistor Tr1 is supplied with the second power supply voltage VccQ as a high-potential side power supply, so that the output terminal To has the second power supply voltage VccQ level. However, no current flows from the output terminal To to the high potential side power source.

The first and second power supply voltages Vcc,
Since VccQ is switched by the power supply switching circuit 2 based on the output control signal C, it is synchronized when the input signal IN is input and when it is not input.

Further, the second power supply voltage VccQ is supplied to the pull-up side output transistor Tr1 and the inverter circuit 1e in the preceding stage thereof by the power supply switching circuit 2, so that the input signal IN becomes H level. At this time, the gate potential of the pull-up side output transistor Tr1 matches the source potential thereof, and the pull-up side output transistor Tr1 is surely turned off.

The first and second power supply voltages Vcc,
Based on the output control signal C, one of VccQ is supplied to the pull-up side output transistor Tr1 and the inverter circuit 1e in the preceding stage via the first and second switch circuits Tr8 and Tr9.

The switch circuit is a P channel MO.
Since it is composed of S-transistors Tr8 and Tr9, the first and second power supply voltages Vcc and VccQ are supplied to the pull-up side output transistor Tr1 and the inverter circuit 1e in the preceding stage while minimizing the voltage drop due to the switch circuit. To be done.

[0030]

FIG. 2 shows an embodiment embodying the present invention. The same components as those in the conventional example will be described with the same reference numerals.

This embodiment has a configuration in which a power supply switching circuit 2 is added to the output circuit of the conventional example. The configuration of the power supply switching circuit 2 will be described. The output control signal C is input to the inverter circuit 1i, and the inverter circuit 1i is connected to the 5V power source VccQ via the P-channel MOS transistor Tr7. The transistor T
The gate of r7 is connected to its drain, and is turned on when the inverter circuit 1i outputs an H level signal,
The inverter circuit 1i is supplied with a voltage of about 4V obtained by stepping down the power supply VccQ by 1V as a high potential side power supply. A ground GND level is supplied to the inverter circuit 1i as a low potential side power source.

The output signal of the inverter circuit 1i is input to the inverter circuit 1j, the output signal of the inverter circuit 1j is input to the inverter circuit 1k, and
It is input to the gate of the P-channel MOS transistor Tr9.

The inverter circuits 1j and 1k are supplied with a power supply VccQ as a high potential side power supply and a ground GND as a low potential side power supply. The inverter circuit 1
The output signal of k is input to the gate of the P-channel MOS transistor Tr8. The source of the transistor Tr8 is supplied with the power supply Vcc, and the source of the transistor Tr9 is supplied with the power supply VccQ.

The drains of the transistors Tr8 and Tr9 are P-channel MO which constitutes the inverter circuit 1e.
Source of S-transistor and output transistor Tr1
Connected to the source of.

In the output circuit configured as described above, when the output control signal C is at L level and the output control signal / bar C is at H level, the output signal OUT is in a high impedance state.

At this time, the output signal of the inverter circuit 1i becomes H level, and the output signal of the inverter circuit 1j is L level.
The level, the output signal of the inverter circuit 1k becomes H level. Then, the transistor Tr9 is turned on, the transistor Tr8 is turned off, and the power supply VccQ is supplied to the output transistor Tr1 and the inverter circuit 1e.

In this state, the power supply VccQ is applied to the output terminal To.
Even if a level is applied, the source / drain of the output transistor Tr1 becomes almost the same level, and the output signal of the inverter circuit 1e becomes almost the power supply VccQ level, so that the output transistor Tr1 is maintained in the off state.

On the other hand, when the output control signal C is at H level and the output control signal / bar C is at L level, the output signals of the inverter circuits 1i and 1k in the power supply switching circuit 2 are at L level.
The level, the output signal of the inverter circuit 1j becomes H level.

Then, the transistor Tr8 is turned on, the transistor Tr9 is turned off, and the power source Vcc is supplied to the output transistor Tr1 and the inverter circuit 1e. In this state, when the input signal IN becomes H level, the source and gate of the output transistor Tr1 become the same level at approximately 3V, and the output transistor Tr1 is surely turned off. Further, the output transistor Tr2 is turned on, and the output signal OU
T becomes L level.

As described above, in the output circuit, when the output signal OUT is in the high impedance state based on the output control signal C.multidot.C, the output transistor Tr1 and the inverter circuit 1e are supplied with the power supply VccQ as the high potential side power supply. Supplied. Therefore, even if the power supply VccQ level is applied to the output terminal To, the output transistor T
No current flows through the power supply VccQ or the substrate via r1, and it is possible to prevent the occurrence of defects in other internal circuits due to this current.

The output signal OU based on the input signal IN
When T is output, the power supply Vcc is supplied to the output transistor Tr1 and the inverter circuit 1e as the high potential side power supply. When the input signal IN is at H level,
Both the source and the gate of the output transistor Tr1 become approximately 3V, the output transistor Tr1 is surely turned off, the output transistor Tr2 is turned on, and the output signal OU is output.
T becomes L level. When the input signal IN becomes L level, the output transistor Tr1 is turned on and
The output transistor Tr2 is turned off, and the output signal OUT becomes the H level of approximately 3V.

Therefore, a through current flowing from the power supply Vcc to the ground GND is prevented, power consumption is reduced, and a decrease in operating speed can be prevented. The output control signals C and C may be an output control signal / bar OE for controlling the operation of the output circuit of the semiconductor memory device or a write control signal / bar WE for controlling the write operation.

In the above embodiment, the output control signals C,
Although the power supply voltage is selected based on the bar C, the power supply voltage may be selected by detecting whether or not the output signal OUT has high impedance.

The technical ideas other than the claims that can be understood from the above-described embodiments will be described below along with their effects. (1) In claim 1, the power supply switching circuit connects three stages of inverter circuits in series, inputs the output control signal to the first stage inverter circuit, and outputs the output signals of the second stage and final stage inverter circuits. It is input to the P-channel MOS transistor, the second power supply voltage is supplied to the first-stage inverter circuit as a high-potential-side power supply via the P-channel MOS transistor, and the second-stage and last-stage inverter circuits are supplied with a second voltage. The second power supply voltage was supplied as the high potential side power supply. The level conversion operation is performed by the three-stage inverter circuit.

[0045]

As described above in detail, the present invention provides an output circuit capable of preventing a malfunction such as a decrease in operating speed, an increase in power consumption, and a failure while supporting different power supply voltages. be able to.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an example.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 2 Power supply switching circuit Tr1 Pull-up side output transistor Tr2 Pull-down side output transistor To Output terminal IN1, IN2 Input signal OUT Output signal Vcc First power supply voltage VccQ Second power supply voltage

Claims (5)

[Claims] 1. A high potential side power source and a low potential side power source,
A pull-up side output transistor composed of a P-channel MOS transistor and a pull-down side output transistor composed of an N-channel MOS transistor are connected in series to output the pull-up side output transistor and the drain of the pull-down side output transistor. The input signal is input to the gates of the pull-up side output transistor and the pull-down side output transistor, the output signal is output from the output terminal, and the source of the pull-up side output transistor is connected to the internal circuit. An output circuit for supplying, as a high-potential-side power supply, either a first power-supply voltage to be supplied or a second power-supply voltage having a level higher than the first power-supply voltage, the source of the pull-up side output transistor Means that the output signal is H level or L level based on the input signal. And a power supply switching circuit that supplies the second power supply voltage when the output signal becomes high impedance regardless of the input signal. 2. Each of the output transistors sets an output signal to an H level or an L level based on the input signal by an output control circuit which operates based on an output control signal input from the outside, or 2. The output circuit according to claim 1, wherein regardless of whether the impedance is high impedance or not, the power supply switching circuit switches the first and second power supply voltages based on the output control signal. 3. The input signal is input to each of the output transistors through an even number of stages of inverter circuits, and the power supply switching circuit, based on the output control signal, the pull-up side output transistor and the preceding stage thereof. 3. The output circuit according to claim 2, wherein any one of the first power supply voltage and the second power supply voltage is supplied to the inverter circuit. 4. The power supply switching circuit supplies the first and second power supply voltages to the pull-up side output transistor and an inverter circuit in the preceding stage through the first and second switch circuits, and The output circuit according to claim 3, wherein one of the first and second switch circuits is closed and the other is opened based on a control signal. 5. The output circuit according to claim 4, wherein the first and second switch circuits are P-channel MOS transistors whose complementary signals are input to their gates based on the control signal. .