JPH0864871A - Gallium nitride compound semiconductor element - Google Patents

Gallium nitride compound semiconductor element

Info

Publication number
JPH0864871A
JPH0864871A JP19637494A JP19637494A JPH0864871A JP H0864871 A JPH0864871 A JP H0864871A JP 19637494 A JP19637494 A JP 19637494A JP 19637494 A JP19637494 A JP 19637494A JP H0864871 A JPH0864871 A JP H0864871A
Authority
JP
Japan
Prior art keywords
electrode
layer
type
gallium nitride
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19637494A
Other languages
Japanese (ja)
Other versions
JP3494478B2 (en
Inventor
Masayuki Senoo
雅之 妹尾
Takao Yamada
孝夫 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichia Chemical Industries Ltd
Original Assignee
Nichia Chemical Industries Ltd
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Filing date
Publication date
Application filed by Nichia Chemical Industries Ltd filed Critical Nichia Chemical Industries Ltd
Priority to JP19637494A priority Critical patent/JP3494478B2/en
Publication of JPH0864871A publication Critical patent/JPH0864871A/en
Application granted granted Critical
Publication of JP3494478B2 publication Critical patent/JP3494478B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE: To improve the ohmic contact of a p-type gallium nitride compound semiconductor with its electrode and to reduce the Vf of a light emitting element and a light receiving element using it by using Mg or its alloy to the side in contact with its p-type layer as the electrode of a p-type gallium nitride compound semiconductor device. CONSTITUTION: A mask of a predetermined shape is formed on the surface of the p-type GaN layer 7 of a wafer, the layer 7 is etched by dry etching, and the part of an n-type GaN layer 3 to be formed with an electrode is exposed, Then, Ti is evaporated as an n-type electrode 8 and Al in a predetermined shape on the Ti is deposited on the surface of the layer 3. Further, Mg is evaporated, Ni is deposited on the Mg, and further Au is evaporated on the Mg on the substantially entire surface of the layer 7 as a p-type electrode 99. After the evaporations, the wafer is annealed in an inert gas atmosphere, both the electrodes are alloyed, the electrode 99 is made light-transmissive, annealed, and the wafer is then cut in a predetermined shape as a light emitting chip.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はレーザダイオード、発光
ダイオード等の発光素子、および太陽電池等の受光素子
に使用される窒化ガリウム系化合物半導体(InXAlY
Ga1-X-YN、0≦X、0≦Y、X+Y≦1)素子の細部の
構造に係り、特にその素子のp型窒化ガリウム系化合物
半導体層に形成される電極に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gallium nitride-based compound semiconductor (In X Al Y ) used for light emitting devices such as laser diodes and light emitting diodes, and light receiving devices such as solar cells.
Ga 1-XY N, 0 ≦ X, 0 ≦ Y, X + Y ≦ 1) The present invention relates to a detailed structure of an element, and particularly to an electrode formed on a p-type gallium nitride compound semiconductor layer of the element.

【0002】[0002]

【従来の技術】広ワイドギャップ半導体である窒化ガリ
ウム系化合物半導体(InXAlYGa1-X-YN、0≦X、
0≦Y、X+Y≦1)は青色発光ダイオード(LED)、
青色レーザダイオード、また太陽電池の材料として注目
されており、最近この材料を用いた光度1000mcd
の青色LEDが実用化されたばかりである。
2. Description of the Related Art A gallium nitride-based compound semiconductor (InXAlYGa1-X-YN, 0≤X, which is a wide and wide gap semiconductor)
0 ≦ Y, X + Y ≦ 1) is a blue light emitting diode (LED),
It has attracted attention as a material for blue laser diodes and solar cells, and recently has a luminous intensity of 1000 mcd using this material.
The blue LED has just been put into practical use.

【0003】このLED素子の構造を図1に示す。この
素子はサファイア基板1の表面にGaNバッファ層2
と、n型GaN層3と、n型AlGaN層4と、InG
aN活性層5と、p型AlGaN層6と、p型GaN層
7とが順に積層されたダブルへテロ構造を有している。
n型GaN層3の表面にはTiとAlよりなるn電極8
が形成されており、p型GaN層の表面にはNiとAu
よりなるp電極9が形成されて、それぞれの電極がワイ
ヤーボンディングされている。n電極8、およびp電極
9はそれぞれの層と良好なオーミック接触を得ており、
If20mAにおいて、Vf3.6Vと非常に良好な特
性を示している。
The structure of this LED element is shown in FIG. This device has a GaN buffer layer 2 on the surface of a sapphire substrate 1.
, N-type GaN layer 3, n-type AlGaN layer 4, InG
It has a double hetero structure in which an aN active layer 5, a p-type AlGaN layer 6, and a p-type GaN layer 7 are sequentially stacked.
An n electrode 8 made of Ti and Al is formed on the surface of the n-type GaN layer 3.
Are formed, and Ni and Au are formed on the surface of the p-type GaN layer.
The p-electrode 9 is formed, and each electrode is wire-bonded. The n-electrode 8 and the p-electrode 9 have good ohmic contact with each layer,
At If20mA, it shows a very good characteristic of Vf3.6V.

【0004】[0004]

【発明が解決しようとする課題】しかし、前記青色LE
Dにおいても、理論的にはまだVfを低下させる余地が
十分にある。そこで本発明の目的とするところは、窒化
ガリウム系化合物半導体、特にp型窒化ガリウム系化合
物半導体と良好なオーミック接触が得られる電極を提供
することにより、窒化ガリウム系化合物半導体を用いた
発光素子、受光素子等のVfを低下させて効率を向上さ
せることにある。
However, the above-mentioned blue LE
Even in D, theoretically, there is still sufficient room for reducing Vf. Therefore, an object of the present invention is to provide a light emitting device using a gallium nitride-based compound semiconductor by providing an electrode capable of obtaining good ohmic contact with a gallium nitride-based compound semiconductor, particularly a p-type gallium nitride-based compound semiconductor, The purpose is to reduce Vf of the light receiving element and the like to improve efficiency.

【0005】[0005]

【課題を解決するための手段】本発明の窒化ガリウム系
化合物半導体素子は、p型の窒化ガリウム系化合物半導
体層を有し、その半導体層に電極が形成されてなる窒化
ガリウム系化合物半導体素子において、前記p型層の電
極は、そのp型層に接する側にマグネシウム(Mg)、
または少なくともMgを含む合金が使用されていること
を特徴とする。
A gallium nitride-based compound semiconductor device according to the present invention is a gallium nitride-based compound semiconductor device having a p-type gallium nitride-based compound semiconductor layer and an electrode formed on the semiconductor layer. , The electrode of the p-type layer has magnesium (Mg) on the side in contact with the p-type layer,
Alternatively, an alloy containing at least Mg is used.

【0006】前記Mgを含む合金には、Mgの他に、M
gよりも電気陰性度の大きい金属、例えばNi、Sn、
Al、Au、Pt等を含む合金を用いることが好まし
く、最も良好なオーミック接触を得る目的ではNiとM
gとを含む合金、またはNiとMgとAuとを含む合金
を使用することが好ましい。このようにMgよりも電気
陰性度の大きい金属を含む合金を使用することにより、
Mgが酸化されにくくなり、電極の変質による素子の劣
化を防止することができる。
The alloy containing Mg includes M, in addition to Mg.
metals with a higher electronegativity than g, such as Ni, Sn,
It is preferable to use an alloy containing Al, Au, Pt and the like, and Ni and M are used for the purpose of obtaining the best ohmic contact.
It is preferable to use an alloy containing g or an alloy containing Ni, Mg and Au. By using an alloy containing a metal having a higher electronegativity than Mg,
Mg is less likely to be oxidized and deterioration of the element due to alteration of the electrode can be prevented.

【0007】図2は本発明の一実施例の素子におけるp
型層7表面の電極99を拡大して示す模式断面図であ
る。この図に示すように、本発明の素子において、p型
層の電極99は、マグネシウム(Mg)またはMgを含
む合金の表面に、さらにAuが積層された少なくとも2
層構造とされていることが好ましく、最も好ましくはワ
イヤーボンディングのボール10と接触する層をAuと
する。Mgの表面にAuを積層した構造とすると、前記
のようにMgが酸化により変質するのを防止する作用が
あると共に、図1のようにp型層の電極をワイヤーボン
ディングで接続した際に、ボール10とp電極9との接
着性を高めて、金ワイヤーが電極から剥がれるのを防止
できる。さらに好都合なことに、Auは他の金属に比べ
て、p層に接したMgによる良好なオーミック接触を損
なうことがない。
FIG. 2 shows p in the element of one embodiment of the present invention.
It is a schematic cross section showing an electrode 99 on the surface of the mold layer 7 in an enlarged manner. As shown in this figure, in the device of the present invention, the electrode 99 of the p-type layer has at least 2 in which Au is further laminated on the surface of magnesium (Mg) or an alloy containing Mg.
It is preferable to have a layered structure, and most preferably Au is the layer that comes into contact with the ball 10 for wire bonding. The structure in which Au is laminated on the surface of Mg has the function of preventing the deterioration of Mg by oxidation as described above, and when the electrodes of the p-type layer are connected by wire bonding as shown in FIG. The adhesion between the ball 10 and the p-electrode 9 can be improved to prevent the gold wire from peeling off from the electrode. More advantageously, Au does not impair the good ohmic contact with Mg in contact with the p-layer as compared to other metals.

【0008】p型層7の表面に直接形成するMgまたは
Mgを含む合金の膜厚は1μm以下、さらに好ましくは
50オングストローム〜0.5μmとすることが好まし
い。1μmよりも厚いとMgによる良好なオーミックが
得られにくくなる傾向にあるからである。次にAuを積
層して2層構造とする場合、Auの膜厚は特に問うもの
ではない。しかしながら、p型層側を発光観測面とする
発光素子、または受光側とする受光素子を実現した場
合、電極99により光が遮断されるので、電極99を透
光性とする必要がある。電極99を透光性にするために
は、電極99をアニーリングして膜厚を1μm以下に調
整することが好ましい。
The film thickness of Mg or an alloy containing Mg formed directly on the surface of the p-type layer 7 is preferably 1 μm or less, more preferably 50 Å to 0.5 μm. If it is thicker than 1 μm, it tends to be difficult to obtain a good ohmic property due to Mg. Next, when Au is laminated to form a two-layer structure, the film thickness of Au does not matter. However, when a light emitting element having a p-type layer side as an emission observation surface or a light receiving element having a light receiving side is realized, light is blocked by the electrode 99, and therefore the electrode 99 needs to be translucent. In order to make the electrode 99 transparent, it is preferable to anneal the electrode 99 to adjust the film thickness to 1 μm or less.

【0009】[0009]

【作用】図3は、Mgがドープされたp型Al0.02Ga
0.98N層表面に種々の電極を作成し、その電極とp層と
の電流電圧特性を測定することにより、電極のオーミッ
ク特性を調べた結果を示す図である。具体的には、p型
Al0.02Ga0.98N層層表面に、 A・・Mgを0.5μmの膜厚で蒸着、 B・・Mgを0.05μm、その上にNiを0.45μ
mの膜厚で蒸着、 C・・Mgを0.05μm、その上にAuを0.45μ
mの膜厚で蒸着、 D・・Mgを0.05μm、その上にNiを0.05μ
m、最後にAuを0.4μmの膜厚で蒸着した後、50
0℃でアニーリングを行い、電極を合金化して、同一種
類の電極間の電流電圧特性を調べたものである。
[Operation] FIG. 3 shows Mg-doped p-type Al0.02Ga.
It is a figure which shows the result of having investigated the ohmic characteristic of the electrode by producing various electrodes on the surface of 0.98 N layer, and measuring the current-voltage characteristic of the electrode and p layer. Specifically, on the surface of the p-type Al0.02Ga0.98N layer layer, A..Mg is vapor-deposited with a thickness of 0.5 μm, B..Mg is 0.05 μm, and Ni is 0.45 μm on it.
Vapor deposition with a film thickness of m, C ·· Mg of 0.05 μm, and Au of 0.45 μm
Vapor deposition with a thickness of m, D..Mg 0.05 μm, and Ni 0.05 μm
m, and finally after depositing Au to a film thickness of 0.4 μm, 50
Annealing was performed at 0 ° C. to alloy the electrodes, and the current-voltage characteristics between electrodes of the same type were examined.

【0010】A〜Dに示すように、いずれの電極におい
てもp層と好ましいオーミック接触が得られていること
がわかる。さらにMg単独の電極Aでは電極が酸化され
やすいせいか、他の電極に比べて抵抗が大きくなってお
り、MgにNi、Au等の酸化されにくい金属を含有さ
せることにより電極自体が安定化し、抵抗が小さくなる
傾向にある。
As shown in A to D, it can be seen that favorable ohmic contact with the p layer is obtained in any of the electrodes. Further, the electrode A of Mg alone may have a higher resistance than other electrodes, probably because the electrode is easily oxidized, and the electrode itself is stabilized by adding a metal such as Ni or Au which is not easily oxidized, to Mg. Resistance tends to decrease.

【0011】[0011]

【実施例】以下、図1および図2を元に本発明の素子を
詳説する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The device of the present invention will be described in detail below with reference to FIGS.

【0012】[実施例1]2インチφのサファイア基板
1の表面に、GaNバッファ層2を200オングストロ
ームと、Siドープn型GaN層3を4μmと、Siド
ープn型AlGaN層4を0.1μmと、ZnおよびS
iドープInGaN活性層5を0.05μmと、Mgド
ープp型AlGaN層6を0.1μmと、Mgドープp
型GaN層7を0.5μmの膜厚で順に積層したウェー
ハを用意する。
Example 1 A GaN buffer layer 2 of 200 Å, a Si-doped n-type GaN layer 3 of 4 μm and a Si-doped n-type AlGaN layer 4 of 0.1 μm were formed on the surface of a 2-inch φ sapphire substrate 1. And Zn and S
The i-doped InGaN active layer 5 is 0.05 μm, the Mg-doped p-type AlGaN layer 6 is 0.1 μm, and the Mg-doped p-type AlGaN layer 6 is 0.1 μm.
A wafer is prepared in which the type GaN layer 7 is sequentially stacked with a film thickness of 0.5 μm.

【0013】次にこのウェーハのp型GaN層7の表面
に所定の形状のマスクを形成し、ドライエッチングによ
り、p型GaN層7側からエッチングを行い、電極を形
成するべきn型GaN層3の一部を露出させる。
Next, a mask having a predetermined shape is formed on the surface of the p-type GaN layer 7 of this wafer, and etching is performed from the p-type GaN layer 7 side by dry etching to form an n-type GaN layer 3 on which an electrode is to be formed. Expose part of.

【0014】次にn型GaN層3の表面に、n電極8と
してTiを0.5μm、Tiの上にAlを2μmの膜厚
で、所定の形状で蒸着する。
Next, on the surface of the n-type GaN layer 3, Ti is deposited as the n-electrode 8 in a predetermined shape with a thickness of 0.5 μm and Al on the Ti with a thickness of 2 μm.

【0015】さらに、p電極99として、p型GaN層
7表面のほぼ全面に亙って、Mgを0.05μm、Mg
の上にNiを0.1μm、さらにMg上にAuを0.5
μmの膜厚で蒸着する。
Further, as the p-electrode 99, Mg of 0.05 μm and Mg are provided over the substantially entire surface of the p-type GaN layer 7.
Ni on top of 0.1 μm, and on Mg over 0.5 μm
Deposition with a film thickness of μm.

【0016】蒸着後、前記ウェーハに不活性ガス雰囲気
中でアニーリングを施し、両電極を合金化すると共に、
p電極99を透光性にする。アニーリング後、ウェーハ
を所定の形状にカットして、発光チップとし、それぞれ
の電極に金線で100μmφのボールを形成してワイヤ
ーボンディングを行いLEDとした。
After vapor deposition, the wafer is annealed in an inert gas atmosphere to alloy both electrodes and
The p-electrode 99 is made transparent. After annealing, the wafer was cut into a predetermined shape to form a light emitting chip, and a ball of 100 μmφ was formed on each electrode with a gold wire and wire bonding was performed to form an LED.

【0017】このLEDは、If20mAにおいて、V
f3.2Vを達成し、光度1200mcd、発光出力
1.6mWと非常に優れた性能を示した。さらに、前記
条件で連続して点灯させたところ、1000時間経過後
において、Vfの変化はなかった。さらにまたp層のワ
イヤーの引っ張り試験を行ったところ、ボールが剥がれ
ることはなく、金ワイヤーが途中で切れてしまった。
This LED has a V voltage of If 20 mA.
It achieved f3.2V, and showed extremely excellent performance with a luminous intensity of 1200 mcd and an emission output of 1.6 mW. Furthermore, when the light was continuously turned on under the above conditions, there was no change in Vf after 1000 hours had elapsed. Furthermore, when a pulling test was performed on the p-layer wire, the ball was not peeled off, and the gold wire was broken on the way.

【0018】[実施例2]p電極99を形成する際、p
層側から順にMgを0.1μmとMgの上にAuを0.
4μmで蒸着する他は実施例1と同様にしてLEDとし
た。このLEDは、If20mAにおいて、同じくVf
3.2Vを達成し、光度、発光出力、および1000時
間経過後のVfの変化、ワイヤーの引っ張り試験におい
ても、実施例1のLEDと同一であった。
Example 2 When forming the p-electrode 99, p
0.1 μm of Mg in order from the layer side, and Au on the Mg layer of 0.1 μm.
An LED was prepared in the same manner as in Example 1 except that vapor deposition was performed at 4 μm. This LED has the same Vf at If20mA.
It achieved the same value as 3.2V, and it was the same as the LED of Example 1 in the luminous intensity, the emission output, the change in Vf after 1000 hours, and the wire pulling test.

【0019】[実施例3]p電極99を形成する際、p
層側から順にMgを0.05μmとMgの上にNiを
0.5μmで蒸着する他は実施例1と同様にしてLED
とした。このLEDは、If20mAにおいて、同じく
Vf3.2Vを達成し、光度、発光出力とも実施例1と
ほぼ同一であったが、1000時間経過後のVfは3.
4Vであった。また、ワイヤーの引っ張り試験では金ワ
イヤーが切れる前に、ボールがp層から剥がれた。
[Embodiment 3] When the p electrode 99 is formed, p
LED in the same manner as in Example 1 except that Mg is deposited in the order of 0.05 μm from the layer side and Ni is deposited on the Mg at 0.5 μm.
And This LED also achieved Vf3.2V at If20mA, and the luminous intensity and the light emission output were almost the same as those in Example 1, but the Vf after 1000 hours was 3.
It was 4V. Further, in the wire pull test, the ball was peeled from the p layer before the gold wire was cut.

【0020】[実施例4]p電極99を形成する際、p
層側にMgを0.5μmの膜厚で蒸着する他は実施例1
と同様にしてLEDとした。このLEDはIf20mA
においてVf3.3Vを達成し、光度、発光出力は実施
例1とほぼ同一であった。さらに、1000時間経過後
のVfは3.5Vであった。またワイヤーの引っ張り試
験では実施例3と同じく、金ワイヤーが切れる前に、ボ
ールがp層から剥がれてしまった。
[Embodiment 4] When the p electrode 99 is formed, p
Example 1 except that Mg is vapor-deposited to a layer thickness of 0.5 μm.
In the same manner as above, an LED was prepared. This LED is If20mA
Vf of 3.3 V was achieved, and the luminous intensity and the emission output were almost the same as in Example 1. Furthermore, Vf after 1000 hours was 3.5V. Also, in the wire pull test, as in Example 3, the ball was peeled off from the p layer before the gold wire was cut.

【0021】[0021]

【発明の効果】以上説明したように、本発明の窒化ガリ
ウム系化合物半導体素子はp層に接する電極を良好なオ
ーミック接触が得られるMgとしているため、Vfが低
下した高効率な素子が実現できる。さらに、Mgでオー
ミック接触を得ると共に、Mgの酸化を防止する目的
で、他の酸化しにくい金属をMgに含有させて合金とす
ることにより素子の寿命を向上させることが可能であ
る。その中でもAuおよびNiは、オーミック接触を損
なうことがなく非常に好適な材料である。さらにAuは
p電極をワイヤーボンドする際にボールとの接着力を高
め、素子の信頼性を高めることができる。
As described above, in the gallium nitride-based compound semiconductor device of the present invention, the electrode in contact with the p-layer is made of Mg capable of obtaining a good ohmic contact, so that a highly efficient device with reduced Vf can be realized. . Further, in order to obtain ohmic contact with Mg and prevent the oxidation of Mg, it is possible to improve the life of the element by adding Mg to another metal that is difficult to oxidize to form an alloy. Among them, Au and Ni are very suitable materials without damaging ohmic contact. Further, Au can enhance the adhesive force with the ball when wire-bonding the p electrode, and can enhance the reliability of the device.

【図面の簡単な説明】[Brief description of drawings]

【図1】 従来の窒化ガリウム系化合物半導体素子の構
造を示す模式断面図。
FIG. 1 is a schematic cross-sectional view showing the structure of a conventional gallium nitride-based compound semiconductor device.

【図2】 本発明の一実施例の素子の電極部分を拡大し
て示す模式断面図。
FIG. 2 is a schematic cross-sectional view showing an electrode portion of an element of an embodiment of the present invention in an enlarged manner.

【図3】 本発明の素子に用いられるp電極の電流電圧
特性を示す図。
FIG. 3 is a diagram showing current-voltage characteristics of a p-electrode used in the device of the present invention.

【符号の説明】[Explanation of symbols]

7・・・p型GaN層 10・・・ボール 99・・・p電極 7 ... p-type GaN layer 10 ... ball 99 ... p electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 p型の窒化ガリウム系化合物半導体層を
有し、その半導体層に電極が形成されてなる窒化ガリウ
ム系化合物半導体素子において、前記p型層の電極は、
そのp型層に接する側にマグネシウム(Mg)、または
少なくともMgを含む合金が使用されていることを特徴
とする窒化ガリウム系化合物半導体素子。
1. A gallium nitride-based compound semiconductor device having a p-type gallium nitride-based compound semiconductor layer and an electrode formed on the semiconductor layer, wherein the electrode of the p-type layer is:
A gallium nitride-based compound semiconductor device, characterized in that magnesium (Mg) or an alloy containing at least Mg is used on the side in contact with the p-type layer.
【請求項2】 前記p型層の電極は、マグネシウム(M
g)またはMgを含む合金の表面に、さらに金(Au)
が積層された少なくとも2層構造とされていることを特
徴とする請求項1に記載の窒化ガリウム系化合物半導体
素子。
2. The electrode of the p-type layer is made of magnesium (M
g) or on the surface of the alloy containing Mg, gold (Au)
The gallium nitride-based compound semiconductor device according to claim 1, wherein the gallium nitride-based compound semiconductor device has at least a two-layer structure in which the above are stacked.
JP19637494A 1994-08-22 1994-08-22 Gallium nitride based compound semiconductor device Expired - Lifetime JP3494478B2 (en)

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Application Number Priority Date Filing Date Title
JP19637494A JP3494478B2 (en) 1994-08-22 1994-08-22 Gallium nitride based compound semiconductor device

Publications (2)

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JPH0864871A true JPH0864871A (en) 1996-03-08
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Country Link
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