JPH0864871A - Gallium nitride compound semiconductor element - Google Patents
Gallium nitride compound semiconductor elementInfo
- Publication number
- JPH0864871A JPH0864871A JP19637494A JP19637494A JPH0864871A JP H0864871 A JPH0864871 A JP H0864871A JP 19637494 A JP19637494 A JP 19637494A JP 19637494 A JP19637494 A JP 19637494A JP H0864871 A JPH0864871 A JP H0864871A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- type
- gallium nitride
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- -1 Gallium nitride compound Chemical class 0.000 title abstract description 4
- 239000000956 alloy Substances 0.000 claims abstract description 14
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 14
- 239000011777 magnesium Substances 0.000 claims description 40
- 239000010931 gold Substances 0.000 claims description 17
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 15
- 150000001875 compounds Chemical class 0.000 claims description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052749 magnesium Inorganic materials 0.000 claims description 5
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000011261 inert gas Substances 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Light Receiving Elements (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はレーザダイオード、発光
ダイオード等の発光素子、および太陽電池等の受光素子
に使用される窒化ガリウム系化合物半導体（ＩｎXＡｌY
Ｇａ1-X-YＮ、０≦X、０≦Y、X＋Y≦１）素子の細部の
構造に係り、特にその素子のｐ型窒化ガリウム系化合物
半導体層に形成される電極に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gallium nitride-based compound semiconductor (In X Al Y ) used for light emitting devices such as laser diodes and light emitting diodes, and light receiving devices such as solar cells.
Ga 1-XY N, 0 ≦ X, 0 ≦ Y, X + Y ≦ 1) The present invention relates to a detailed structure of an element, and particularly to an electrode formed on a p-type gallium nitride compound semiconductor layer of the element.
【０００２】[0002]
【従来の技術】広ワイドギャップ半導体である窒化ガリ
ウム系化合物半導体（ＩｎXＡｌYＧａ1-X-YＮ、０≦X、
０≦Y、X＋Y≦１）は青色発光ダイオード（ＬＥＤ）、
青色レーザダイオード、また太陽電池の材料として注目
されており、最近この材料を用いた光度１０００ｍｃｄ
の青色ＬＥＤが実用化されたばかりである。2. Description of the Related Art A gallium nitride-based compound semiconductor (InXAlYGa1-X-YN, 0≤X, which is a wide and wide gap semiconductor)
0 ≦ Y, X + Y ≦ 1) is a blue light emitting diode (LED),
It has attracted attention as a material for blue laser diodes and solar cells, and recently has a luminous intensity of 1000 mcd using this material.
The blue LED has just been put into practical use.
【０００３】このＬＥＤ素子の構造を図１に示す。この
素子はサファイア基板１の表面にＧａＮバッファ層２
と、ｎ型ＧａＮ層３と、ｎ型ＡｌＧａＮ層４と、ＩｎＧ
ａＮ活性層５と、ｐ型ＡｌＧａＮ層６と、ｐ型ＧａＮ層
７とが順に積層されたダブルへテロ構造を有している。
ｎ型ＧａＮ層３の表面にはＴｉとＡｌよりなるｎ電極８
が形成されており、ｐ型ＧａＮ層の表面にはＮｉとＡｕ
よりなるｐ電極９が形成されて、それぞれの電極がワイ
ヤーボンディングされている。ｎ電極８、およびｐ電極
９はそれぞれの層と良好なオーミック接触を得ており、
Ｉｆ２０ｍＡにおいて、Ｖｆ３．６Ｖと非常に良好な特
性を示している。The structure of this LED element is shown in FIG. This device has a GaN buffer layer 2 on the surface of a sapphire substrate 1.
, N-type GaN layer 3, n-type AlGaN layer 4, InG
It has a double hetero structure in which an aN active layer 5, a p-type AlGaN layer 6, and a p-type GaN layer 7 are sequentially stacked.
An n electrode 8 made of Ti and Al is formed on the surface of the n-type GaN layer 3.
Are formed, and Ni and Au are formed on the surface of the p-type GaN layer.
The p-electrode 9 is formed, and each electrode is wire-bonded. The n-electrode 8 and the p-electrode 9 have good ohmic contact with each layer,
At If20mA, it shows a very good characteristic of Vf3.6V.
【０００４】[0004]
【発明が解決しようとする課題】しかし、前記青色ＬＥ
Ｄにおいても、理論的にはまだＶｆを低下させる余地が
十分にある。そこで本発明の目的とするところは、窒化
ガリウム系化合物半導体、特にｐ型窒化ガリウム系化合
物半導体と良好なオーミック接触が得られる電極を提供
することにより、窒化ガリウム系化合物半導体を用いた
発光素子、受光素子等のＶｆを低下させて効率を向上さ
せることにある。However, the above-mentioned blue LE
Even in D, theoretically, there is still sufficient room for reducing Vf. Therefore, an object of the present invention is to provide a light emitting device using a gallium nitride-based compound semiconductor by providing an electrode capable of obtaining good ohmic contact with a gallium nitride-based compound semiconductor, particularly a p-type gallium nitride-based compound semiconductor, The purpose is to reduce Vf of the light receiving element and the like to improve efficiency.
【０００５】[0005]
【課題を解決するための手段】本発明の窒化ガリウム系
化合物半導体素子は、ｐ型の窒化ガリウム系化合物半導
体層を有し、その半導体層に電極が形成されてなる窒化
ガリウム系化合物半導体素子において、前記ｐ型層の電
極は、そのｐ型層に接する側にマグネシウム（Ｍｇ）、
または少なくともＭｇを含む合金が使用されていること
を特徴とする。A gallium nitride-based compound semiconductor device according to the present invention is a gallium nitride-based compound semiconductor device having a p-type gallium nitride-based compound semiconductor layer and an electrode formed on the semiconductor layer. , The electrode of the p-type layer has magnesium (Mg) on the side in contact with the p-type layer,
Alternatively, an alloy containing at least Mg is used.
【０００６】前記Ｍｇを含む合金には、Ｍｇの他に、Ｍ
ｇよりも電気陰性度の大きい金属、例えばＮｉ、Ｓｎ、
Ａｌ、Ａｕ、Ｐｔ等を含む合金を用いることが好まし
く、最も良好なオーミック接触を得る目的ではＮｉとＭ
ｇとを含む合金、またはＮｉとＭｇとＡｕとを含む合金
を使用することが好ましい。このようにＭｇよりも電気
陰性度の大きい金属を含む合金を使用することにより、
Ｍｇが酸化されにくくなり、電極の変質による素子の劣
化を防止することができる。The alloy containing Mg includes M, in addition to Mg.
metals with a higher electronegativity than g, such as Ni, Sn,
It is preferable to use an alloy containing Al, Au, Pt and the like, and Ni and M are used for the purpose of obtaining the best ohmic contact.
It is preferable to use an alloy containing g or an alloy containing Ni, Mg and Au. By using an alloy containing a metal having a higher electronegativity than Mg,
Mg is less likely to be oxidized and deterioration of the element due to alteration of the electrode can be prevented.
【０００７】図２は本発明の一実施例の素子におけるｐ
型層７表面の電極９９を拡大して示す模式断面図であ
る。この図に示すように、本発明の素子において、ｐ型
層の電極９９は、マグネシウム（Ｍｇ）またはＭｇを含
む合金の表面に、さらにＡｕが積層された少なくとも２
層構造とされていることが好ましく、最も好ましくはワ
イヤーボンディングのボール１０と接触する層をＡｕと
する。Ｍｇの表面にＡｕを積層した構造とすると、前記
のようにＭｇが酸化により変質するのを防止する作用が
あると共に、図１のようにｐ型層の電極をワイヤーボン
ディングで接続した際に、ボール１０とｐ電極９との接
着性を高めて、金ワイヤーが電極から剥がれるのを防止
できる。さらに好都合なことに、Ａｕは他の金属に比べ
て、ｐ層に接したＭｇによる良好なオーミック接触を損
なうことがない。FIG. 2 shows p in the element of one embodiment of the present invention.
It is a schematic cross section showing an electrode 99 on the surface of the mold layer 7 in an enlarged manner. As shown in this figure, in the device of the present invention, the electrode 99 of the p-type layer has at least 2 in which Au is further laminated on the surface of magnesium (Mg) or an alloy containing Mg.
It is preferable to have a layered structure, and most preferably Au is the layer that comes into contact with the ball 10 for wire bonding. The structure in which Au is laminated on the surface of Mg has the function of preventing the deterioration of Mg by oxidation as described above, and when the electrodes of the p-type layer are connected by wire bonding as shown in FIG. The adhesion between the ball 10 and the p-electrode 9 can be improved to prevent the gold wire from peeling off from the electrode. More advantageously, Au does not impair the good ohmic contact with Mg in contact with the p-layer as compared to other metals.
【０００８】ｐ型層７の表面に直接形成するＭｇまたは
Ｍｇを含む合金の膜厚は１μｍ以下、さらに好ましくは
５０オングストローム〜０．５μｍとすることが好まし
い。１μｍよりも厚いとＭｇによる良好なオーミックが
得られにくくなる傾向にあるからである。次にＡｕを積
層して２層構造とする場合、Ａｕの膜厚は特に問うもの
ではない。しかしながら、ｐ型層側を発光観測面とする
発光素子、または受光側とする受光素子を実現した場
合、電極９９により光が遮断されるので、電極９９を透
光性とする必要がある。電極９９を透光性にするために
は、電極９９をアニーリングして膜厚を１μｍ以下に調
整することが好ましい。The film thickness of Mg or an alloy containing Mg formed directly on the surface of the p-type layer 7 is preferably 1 μm or less, more preferably 50 Å to 0.5 μm. If it is thicker than 1 μm, it tends to be difficult to obtain a good ohmic property due to Mg. Next, when Au is laminated to form a two-layer structure, the film thickness of Au does not matter. However, when a light emitting element having a p-type layer side as an emission observation surface or a light receiving element having a light receiving side is realized, light is blocked by the electrode 99, and therefore the electrode 99 needs to be translucent. In order to make the electrode 99 transparent, it is preferable to anneal the electrode 99 to adjust the film thickness to 1 μm or less.
【０００９】[0009]
【作用】図３は、Ｍｇがドープされたｐ型Ａｌ0.02Ｇａ
0.98Ｎ層表面に種々の電極を作成し、その電極とｐ層と
の電流電圧特性を測定することにより、電極のオーミッ
ク特性を調べた結果を示す図である。具体的には、ｐ型
Ａｌ0.02Ｇａ0.98Ｎ層層表面に、 Ａ・・Ｍｇを０．５μｍの膜厚で蒸着、 Ｂ・・Ｍｇを０．０５μｍ、その上にＮｉを０．４５μ
ｍの膜厚で蒸着、 Ｃ・・Ｍｇを０．０５μｍ、その上にＡｕを０．４５μ
ｍの膜厚で蒸着、 Ｄ・・Ｍｇを０．０５μｍ、その上にＮｉを０．０５μ
ｍ、最後にＡｕを０．４μｍの膜厚で蒸着した後、５０
０℃でアニーリングを行い、電極を合金化して、同一種
類の電極間の電流電圧特性を調べたものである。[Operation] FIG. 3 shows Mg-doped p-type Al0.02Ga.
It is a figure which shows the result of having investigated the ohmic characteristic of the electrode by producing various electrodes on the surface of 0.98 N layer, and measuring the current-voltage characteristic of the electrode and p layer. Specifically, on the surface of the p-type Al0.02Ga0.98N layer layer, A..Mg is vapor-deposited with a thickness of 0.5 μm, B..Mg is 0.05 μm, and Ni is 0.45 μm on it.
Vapor deposition with a film thickness of m, C ·· Mg of 0.05 μm, and Au of 0.45 μm
Vapor deposition with a thickness of m, D..Mg 0.05 μm, and Ni 0.05 μm
m, and finally after depositing Au to a film thickness of 0.4 μm, 50
Annealing was performed at 0 ° C. to alloy the electrodes, and the current-voltage characteristics between electrodes of the same type were examined.
【００１０】Ａ〜Ｄに示すように、いずれの電極におい
てもｐ層と好ましいオーミック接触が得られていること
がわかる。さらにＭｇ単独の電極Ａでは電極が酸化され
やすいせいか、他の電極に比べて抵抗が大きくなってお
り、ＭｇにＮｉ、Ａｕ等の酸化されにくい金属を含有さ
せることにより電極自体が安定化し、抵抗が小さくなる
傾向にある。As shown in A to D, it can be seen that favorable ohmic contact with the p layer is obtained in any of the electrodes. Further, the electrode A of Mg alone may have a higher resistance than other electrodes, probably because the electrode is easily oxidized, and the electrode itself is stabilized by adding a metal such as Ni or Au which is not easily oxidized, to Mg. Resistance tends to decrease.
【００１１】[0011]
【実施例】以下、図１および図２を元に本発明の素子を
詳説する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The device of the present invention will be described in detail below with reference to FIGS.
【００１２】［実施例１］２インチφのサファイア基板
１の表面に、ＧａＮバッファ層２を２００オングストロ
ームと、Ｓｉドープｎ型ＧａＮ層３を４μｍと、Ｓｉド
ープｎ型ＡｌＧａＮ層４を０．１μｍと、ＺｎおよびＳ
ｉドープＩｎＧａＮ活性層５を０．０５μｍと、Ｍｇド
ープｐ型ＡｌＧａＮ層６を０．１μｍと、Ｍｇドープｐ
型ＧａＮ層７を０．５μｍの膜厚で順に積層したウェー
ハを用意する。Example 1 A GaN buffer layer 2 of 200 Å, a Si-doped n-type GaN layer 3 of 4 μm and a Si-doped n-type AlGaN layer 4 of 0.1 μm were formed on the surface of a 2-inch φ sapphire substrate 1. And Zn and S
The i-doped InGaN active layer 5 is 0.05 μm, the Mg-doped p-type AlGaN layer 6 is 0.1 μm, and the Mg-doped p-type AlGaN layer 6 is 0.1 μm.
A wafer is prepared in which the type GaN layer 7 is sequentially stacked with a film thickness of 0.5 μm.
【００１３】次にこのウェーハのｐ型ＧａＮ層７の表面
に所定の形状のマスクを形成し、ドライエッチングによ
り、ｐ型ＧａＮ層７側からエッチングを行い、電極を形
成するべきｎ型ＧａＮ層３の一部を露出させる。Next, a mask having a predetermined shape is formed on the surface of the p-type GaN layer 7 of this wafer, and etching is performed from the p-type GaN layer 7 side by dry etching to form an n-type GaN layer 3 on which an electrode is to be formed. Expose part of.
【００１４】次にｎ型ＧａＮ層３の表面に、ｎ電極８と
してＴｉを０．５μｍ、Ｔｉの上にＡｌを２μｍの膜厚
で、所定の形状で蒸着する。Next, on the surface of the n-type GaN layer 3, Ti is deposited as the n-electrode 8 in a predetermined shape with a thickness of 0.5 μm and Al on the Ti with a thickness of 2 μm.
【００１５】さらに、ｐ電極９９として、ｐ型ＧａＮ層
７表面のほぼ全面に亙って、Ｍｇを０．０５μｍ、Ｍｇ
の上にＮｉを０．１μｍ、さらにＭｇ上にＡｕを０．５
μｍの膜厚で蒸着する。Further, as the p-electrode 99, Mg of 0.05 μm and Mg are provided over the substantially entire surface of the p-type GaN layer 7.
Ni on top of 0.1 μm, and on Mg over 0.5 μm
Deposition with a film thickness of μm.
【００１６】蒸着後、前記ウェーハに不活性ガス雰囲気
中でアニーリングを施し、両電極を合金化すると共に、
ｐ電極９９を透光性にする。アニーリング後、ウェーハ
を所定の形状にカットして、発光チップとし、それぞれ
の電極に金線で１００μｍφのボールを形成してワイヤ
ーボンディングを行いＬＥＤとした。After vapor deposition, the wafer is annealed in an inert gas atmosphere to alloy both electrodes and
The p-electrode 99 is made transparent. After annealing, the wafer was cut into a predetermined shape to form a light emitting chip, and a ball of 100 μmφ was formed on each electrode with a gold wire and wire bonding was performed to form an LED.
【００１７】このＬＥＤは、Ｉｆ２０ｍＡにおいて、Ｖ
ｆ３．２Ｖを達成し、光度１２００ｍｃｄ、発光出力
１．６ｍＷと非常に優れた性能を示した。さらに、前記
条件で連続して点灯させたところ、１０００時間経過後
において、Ｖｆの変化はなかった。さらにまたｐ層のワ
イヤーの引っ張り試験を行ったところ、ボールが剥がれ
ることはなく、金ワイヤーが途中で切れてしまった。This LED has a V voltage of If 20 mA.
It achieved f3.2V, and showed extremely excellent performance with a luminous intensity of 1200 mcd and an emission output of 1.6 mW. Furthermore, when the light was continuously turned on under the above conditions, there was no change in Vf after 1000 hours had elapsed. Furthermore, when a pulling test was performed on the p-layer wire, the ball was not peeled off, and the gold wire was broken on the way.
【００１８】［実施例２］ｐ電極９９を形成する際、ｐ
層側から順にＭｇを０．１μｍとＭｇの上にＡｕを０．
４μｍで蒸着する他は実施例１と同様にしてＬＥＤとし
た。このＬＥＤは、Ｉｆ２０ｍＡにおいて、同じくＶｆ
３．２Ｖを達成し、光度、発光出力、および１０００時
間経過後のＶｆの変化、ワイヤーの引っ張り試験におい
ても、実施例１のＬＥＤと同一であった。Example 2 When forming the p-electrode 99, p
0.1 μm of Mg in order from the layer side, and Au on the Mg layer of 0.1 μm.
An LED was prepared in the same manner as in Example 1 except that vapor deposition was performed at 4 μm. This LED has the same Vf at If20mA.
It achieved the same value as 3.2V, and it was the same as the LED of Example 1 in the luminous intensity, the emission output, the change in Vf after 1000 hours, and the wire pulling test.
【００１９】［実施例３］ｐ電極９９を形成する際、ｐ
層側から順にＭｇを０．０５μｍとＭｇの上にＮｉを
０．５μｍで蒸着する他は実施例１と同様にしてＬＥＤ
とした。このＬＥＤは、Ｉｆ２０ｍＡにおいて、同じく
Ｖｆ３．２Ｖを達成し、光度、発光出力とも実施例１と
ほぼ同一であったが、１０００時間経過後のＶｆは３．
４Ｖであった。また、ワイヤーの引っ張り試験では金ワ
イヤーが切れる前に、ボールがｐ層から剥がれた。[Embodiment 3] When the p electrode 99 is formed, p
LED in the same manner as in Example 1 except that Mg is deposited in the order of 0.05 μm from the layer side and Ni is deposited on the Mg at 0.5 μm.
And This LED also achieved Vf3.2V at If20mA, and the luminous intensity and the light emission output were almost the same as those in Example 1, but the Vf after 1000 hours was 3.
It was 4V. Further, in the wire pull test, the ball was peeled from the p layer before the gold wire was cut.
【００２０】［実施例４］ｐ電極９９を形成する際、ｐ
層側にＭｇを０．５μｍの膜厚で蒸着する他は実施例１
と同様にしてＬＥＤとした。このＬＥＤはＩｆ２０ｍＡ
においてＶｆ３．３Ｖを達成し、光度、発光出力は実施
例１とほぼ同一であった。さらに、１０００時間経過後
のＶｆは３．５Ｖであった。またワイヤーの引っ張り試
験では実施例３と同じく、金ワイヤーが切れる前に、ボ
ールがｐ層から剥がれてしまった。[Embodiment 4] When the p electrode 99 is formed, p
Example 1 except that Mg is vapor-deposited to a layer thickness of 0.5 μm.
In the same manner as above, an LED was prepared. This LED is If20mA
Vf of 3.3 V was achieved, and the luminous intensity and the emission output were almost the same as in Example 1. Furthermore, Vf after 1000 hours was 3.5V. Also, in the wire pull test, as in Example 3, the ball was peeled off from the p layer before the gold wire was cut.
【００２１】[0021]
【発明の効果】以上説明したように、本発明の窒化ガリ
ウム系化合物半導体素子はｐ層に接する電極を良好なオ
ーミック接触が得られるＭｇとしているため、Ｖｆが低
下した高効率な素子が実現できる。さらに、Ｍｇでオー
ミック接触を得ると共に、Ｍｇの酸化を防止する目的
で、他の酸化しにくい金属をＭｇに含有させて合金とす
ることにより素子の寿命を向上させることが可能であ
る。その中でもＡｕおよびＮｉは、オーミック接触を損
なうことがなく非常に好適な材料である。さらにＡｕは
ｐ電極をワイヤーボンドする際にボールとの接着力を高
め、素子の信頼性を高めることができる。As described above, in the gallium nitride-based compound semiconductor device of the present invention, the electrode in contact with the p-layer is made of Mg capable of obtaining a good ohmic contact, so that a highly efficient device with reduced Vf can be realized. . Further, in order to obtain ohmic contact with Mg and prevent the oxidation of Mg, it is possible to improve the life of the element by adding Mg to another metal that is difficult to oxidize to form an alloy. Among them, Au and Ni are very suitable materials without damaging ohmic contact. Further, Au can enhance the adhesive force with the ball when wire-bonding the p electrode, and can enhance the reliability of the device.
【図１】 従来の窒化ガリウム系化合物半導体素子の構
造を示す模式断面図。FIG. 1 is a schematic cross-sectional view showing the structure of a conventional gallium nitride-based compound semiconductor device.
【図２】 本発明の一実施例の素子の電極部分を拡大し
て示す模式断面図。FIG. 2 is a schematic cross-sectional view showing an electrode portion of an element of an embodiment of the present invention in an enlarged manner.
【図３】 本発明の素子に用いられるｐ電極の電流電圧
特性を示す図。FIG. 3 is a diagram showing current-voltage characteristics of a p-electrode used in the device of the present invention.
７・・・ｐ型ＧａＮ層 １０・・・ボール ９９・・・ｐ電極 7 ... p-type GaN layer 10 ... ball 99 ... p electrode
Claims (2)
有し、その半導体層に電極が形成されてなる窒化ガリウ
ム系化合物半導体素子において、前記ｐ型層の電極は、
そのｐ型層に接する側にマグネシウム（Ｍｇ）、または
少なくともＭｇを含む合金が使用されていることを特徴
とする窒化ガリウム系化合物半導体素子。1. A gallium nitride-based compound semiconductor device having a p-type gallium nitride-based compound semiconductor layer and an electrode formed on the semiconductor layer, wherein the electrode of the p-type layer is:
A gallium nitride-based compound semiconductor device, characterized in that magnesium (Mg) or an alloy containing at least Mg is used on the side in contact with the p-type layer.
ｇ）またはＭｇを含む合金の表面に、さらに金（Ａｕ）
が積層された少なくとも２層構造とされていることを特
徴とする請求項１に記載の窒化ガリウム系化合物半導体
素子。2. The electrode of the p-type layer is made of magnesium (M
g) or on the surface of the alloy containing Mg, gold (Au)
The gallium nitride-based compound semiconductor device according to claim 1, wherein the gallium nitride-based compound semiconductor device has at least a two-layer structure in which the above are stacked.
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|---|---|---|---|
| JP19637494A JP3494478B2 (en) | 1994-08-22 | 1994-08-22 | Gallium nitride based compound semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19637494A JP3494478B2 (en) | 1994-08-22 | 1994-08-22 | Gallium nitride based compound semiconductor device |
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|---|---|
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| JP3494478B2 JP3494478B2 (en) | 2004-02-09 |
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Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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| EXPY | Cancellation because of completion of term |