JPH0864472A - Manufacture of chip type thick capacitor - Google Patents

Manufacture of chip type thick capacitor

Info

Publication number
JPH0864472A
JPH0864472A JP6201669A JP20166994A JPH0864472A JP H0864472 A JPH0864472 A JP H0864472A JP 6201669 A JP6201669 A JP 6201669A JP 20166994 A JP20166994 A JP 20166994A JP H0864472 A JPH0864472 A JP H0864472A
Authority
JP
Japan
Prior art keywords
film
electrode film
capacitor
films
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6201669A
Other languages
Japanese (ja)
Inventor
Toshihiro Hanamura
敏裕 花村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP6201669A priority Critical patent/JPH0864472A/en
Priority to KR1019960702104A priority patent/KR100206621B1/en
Priority to CN95190820A priority patent/CN1046817C/en
Priority to PCT/JP1995/001664 priority patent/WO1996007188A1/en
Priority to US08/596,326 priority patent/US5691877A/en
Publication of JPH0864472A publication Critical patent/JPH0864472A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To effectively reduce a defective occurrence rate by simultaneously so forming a lower layer electrode film and an auxiliary electrode film as to have an electrical continuity with an upper surface electrode film for a connecting terminal, and the upper electrode film of the upper surface of a dielectric film on the lower layer film with the auxiliary electrode film. CONSTITUTION: A pair of upper surface electrode films 12, 13 for left and right connecting terminals are formed on the upper surface of a chip piece 11. Simultaneously, a lower layer electrode film 14 and an auxiliary electrode film 20 for constituting a capacitor are so formed that the one end of the film 14 is superposed on the film 12 for the one connecting terminal of the films 12, 12 for both the terminals and the part of the film 20 is superposed on the film 12 for the other terminal. A dielectric film 15 for forming a capacitor is formed on the upper surface of the film 14, and an upper layer electrode film 15 for forming the capacitor is formed on the upper surface of the film 15 in such a manner that the one end of the film 16 is superposed on the films 20.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、絶縁体製チップ片の上
面に、コンデンサを厚膜状に形成して成るいわゆるチッ
プ型厚膜コンデンサを製造する方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a so-called chip type thick film capacitor in which a capacitor is formed in a thick film on the upper surface of an insulating chip piece.

【0002】[0002]

【従来の技術】一般に、この種のチップ型厚膜コンデン
サは、図7及び図8に示すように、セラミック等の絶縁
体製チップ片1の上面に、左右一対の接続端子用上面電
極膜2,3を形成すると共に、コンデンサを構成する下
層電極膜4を、当該下層電極膜4の一端が前記両接続端
子用上面電極膜2,3のうち一方の接続端子用上面電極
膜2に重なるように形成して、この下層電極膜4の上面
に、コンデンサを構成する誘電体膜5を形成し、更に、
この誘電体膜5の上面に、コンデンサを構成する上層電
極膜6を、当該上層電極膜6が前記両接続端子用上面電
極膜2,3のうち他方の接続端子用上面電極膜3に重な
るように形成したものに構成している。
2. Description of the Related Art Generally, as shown in FIGS. 7 and 8, a chip type thick film capacitor of this type includes a pair of left and right upper surface electrode films 2 for connection terminals on the upper surface of a chip 1 made of an insulator such as ceramic. , 3 is formed, and the lower layer electrode film 4 constituting the capacitor is formed such that one end of the lower layer electrode film 4 overlaps with one of the connection terminal upper surface electrode films 2 and 3. And a dielectric film 5 forming a capacitor on the upper surface of the lower electrode film 4, and further,
On the upper surface of the dielectric film 5, an upper electrode film 6 constituting a capacitor is arranged so that the upper electrode film 6 overlaps the other upper electrode film 3 for connecting terminals of the upper electrode films 2 for connecting terminals. It is configured to be formed in.

【0003】なお、符号7,8は、前記チップ片1にお
ける左右両端面の各々に、前記両接続端子用上面電極膜
2,3に電気的に導通するように形成した接続端子用側
面電極膜を、符号9は、ガラス等のオーバーコートを示
し、前記両接続端子用上面電極膜2,3及び両接続端子
用側面電極膜7,8の外表面には、半田ゆれ性を向上す
るための適宜の金属メッキ層が形成されている。
Reference numerals 7 and 8 denote side surface electrode films for connection terminals formed on both left and right end surfaces of the chip piece 1 so as to be electrically connected to the upper surface electrode films 2, 3 for both connection terminals. Reference numeral 9 indicates an overcoat made of glass or the like, and the outer surfaces of the upper electrode films 2 and 3 for both connection terminals and the side electrode films 7 and 8 for both connection terminals are used to improve solderability. An appropriate metal plating layer is formed.

【0004】従来、このチップ型厚膜コンデンサの製造
に際しては、先づ、チップ片1の上面に、左右一対の接
続端子用上面電極膜2,3を、第1スクリーンを使用し
たスクリーン印刷にて形成し、次いで、前記チップ片1
の上面に、下層電極膜4を、第2スクリーンを使用した
スクリーン印刷にて形成し、更に、誘電体膜5を、第3
スクリーンを使用したスクリーン印刷にて形成したの
ち、上層電極膜6を、第4スクリーンを使用したスクリ
ーン印刷にて形成すると言う方法を採用している。
Conventionally, when manufacturing this chip type thick film capacitor, first, a pair of left and right upper surface electrode films for connection terminals are formed on the upper surface of the chip piece 1 by screen printing using a first screen. Formed and then the chip piece 1
A lower electrode film 4 is formed on the upper surface of the substrate by screen printing using a second screen, and a dielectric film 5 is formed on the third electrode
A method is adopted in which after forming by screen printing using a screen, the upper electrode film 6 is formed by screen printing using a fourth screen.

【0005】[0005]

【発明が解決しようとする課題】しかし、最終的に金属
メッキが施される左右一対の両接続端子用上面電極膜
2,3を、スクリーン印刷にて形成し、次いで、コンデ
ンサ用の下層電極膜4及び上層電極膜6を、スクリーン
印刷にて形成するに際しては、その各々のスクリーン印
刷工程が異なることのために、その相互間に相対的な位
置のずれが必然的に存在するものであるから、この相対
的な位置のずれが、他方の接続端子用上面電極膜3及び
上層電極膜6と、下層電極膜4とが互いに接近する方向
に発生した場合には、他方の接続端子用上面電極膜3又
は上層電極膜6と下層電極膜4との間に電気的なショー
トが発生して、不良品に至ることになる。
However, a pair of left and right upper surface electrode films 2 and 3 for connection terminals, which are finally metal-plated, are formed by screen printing, and then a lower layer electrode film for a capacitor is formed. 4 and the upper electrode film 6 are formed by screen printing, there is necessarily a relative positional deviation between them due to the different screen printing steps. When this relative positional deviation occurs in the direction in which the other connection terminal upper surface electrode film 3 and the upper layer electrode film 6 and the lower layer electrode film 4 approach each other, the other connection terminal upper surface electrode An electrical short circuit occurs between the film 3 or the upper electrode film 6 and the lower electrode film 4, resulting in a defective product.

【0006】すなわち、従来の製造方法では、前記した
ように、各電極膜の形成するときにおける相対的な位置
のずれに起因しての不良品の発生率が高いと言う問題が
あった。本発明は、この問題を、つまり、不良品の発生
率を確実に低減できるようにした製造方法を提供するこ
とを技術的課題とするものである。
That is, in the conventional manufacturing method, as described above, there is a problem that the defective product rate is high due to the relative displacement of the electrode films when they are formed. An object of the present invention is to provide a manufacturing method capable of reliably reducing this problem, that is, the incidence of defective products.

【0007】[0007]

【課題を解決するための手段】この技術的的課題を達成
するため本発明は、「絶縁体製チップ片の上面に、左右
一対の接続端子用上面電極膜を形成し、次いで、コンデ
ンサ用の下層電極膜と、この下層電極膜と適宜間隔を隔
てた補助電極膜とを、下層電極膜が前記両接続端子用上
面電極膜のうち一方の接続端子用上面電極膜に、補助電
極膜が他方の接続端子用上面電極膜に各々電気的に導通
するように同時に形成し、前記下層電極膜の上面にコン
デンサ用の誘電体膜を形成したのち、この誘電体膜の上
面にコンデンサ用の上層電極膜を、当該上層電極膜が前
記補助電極膜に電気的に導通するように形成する。」こ
とにした。
In order to achieve this technical object, the present invention provides a method of forming a pair of left and right upper surface electrode films for connection terminals on the upper surface of an insulator chip piece, and then forming a capacitor terminal film. A lower layer electrode film and an auxiliary electrode film spaced apart from the lower layer electrode film as appropriate are provided, wherein the lower layer electrode film is one of the connection terminal upper surface electrode films and the auxiliary electrode film is the other. Are simultaneously formed on the upper electrode film for connecting terminals so as to be electrically connected to each other, a dielectric film for a capacitor is formed on the upper surface of the lower electrode film, and then the upper electrode for the capacitor is formed on the upper surface of the dielectric film. The film is formed so that the upper electrode film is electrically connected to the auxiliary electrode film. ”

【0008】[0008]

【作 用】このように、左右一対の両接続端子用上面
電極膜のうち一方の接続端子用上面電極膜に対して電気
的に導通するコンデンサ用下層電極膜と、他方の接続端
子用上面電極膜及びコンデンサ用上層電極膜に電気的に
導通する補助電極膜とを、同時に形成することにより、
その間における相対的な位置のずれをなくすることがで
き、換言すると、その間における間隔を常に一定に確保
することができるから、各電極膜を形成するに際して、
その相互間に相対的な位置のずれが存在しても、前記一
方の接続端子用上面電極膜に電気的に導通するコンデン
サ用下層電極膜が、他方の接続端子用上面電極膜及びコ
ンデンサ用上層電極膜に対して電気的にショートするこ
とを、前記補助電極膜をコンデンサ用下層電極膜と同時
に形成することによって、確実に回避することができる
のである。
[Operation] As described above, of the pair of left and right upper surface electrode films for both connecting terminals, the lower electrode film for capacitors electrically conducting to the upper surface electrode film for one connecting terminal and the upper electrode for the other connecting terminal By simultaneously forming the film and the auxiliary electrode film electrically conducting to the capacitor upper electrode film,
It is possible to eliminate the relative positional deviation between them, in other words, since the interval between them can always be kept constant, when forming each electrode film,
Even if there is a relative positional deviation between them, the lower electrode film for a capacitor electrically connected to the upper electrode film for a connecting terminal is the upper electrode film for a connecting terminal and the upper electrode film for a capacitor. By electrically forming the auxiliary electrode film at the same time as the capacitor lower layer electrode film, it is possible to surely avoid electrical short-circuit with respect to the electrode film.

【0009】[0009]

【発明の効果】従って、本発明によると、各電極膜の形
成するときにおける相対的な位置のずれに起因しての不
良品の発生率を、大幅に低減できる効果を有する。
Therefore, according to the present invention, there is an effect that the incidence of defective products due to the relative displacement of each electrode film can be greatly reduced.

【0010】[0010]

【実施例】以下、本発明の実施例を、図1〜図6の図面
について説明する。図1及び図2は、本発明の方法によ
って製造されたチップ型厚膜コンデンサを示し、このチ
ップ型厚膜コンデンサは、セラミック等の絶縁体製のチ
ップ片11の上面に、左右一対の接続端子用上面電極膜
12,13を形成すると共に、コンデンサを構成する下
層電極膜14及び補助電極膜20を、当該下層電極膜1
4の一端が前記両接続端子用上面電極膜12,13のう
ち一方の接続端子用上面電極膜12に、補助電極膜20
の一部が他方の接続端子用上面電極膜13に各々に重な
るように形成し、前記下層電極膜14の上面に、コンデ
ンサを構成する誘電体膜15を形成し、更に、この誘電
体膜15の上面に、コンデンサを構成する上層電極膜1
6を、当該上層電極膜16の一端が前記両補助電極膜2
0に重なるように形成したものに構成されている。
Embodiments of the present invention will be described below with reference to the drawings of FIGS. 1 and 2 show a chip type thick film capacitor manufactured by the method of the present invention. This chip type thick film capacitor has a pair of left and right connecting terminals on the upper surface of a chip piece 11 made of an insulator such as ceramics. And the lower electrode film 14 and the auxiliary electrode film 20 constituting the capacitor are formed on the lower electrode film 1
4 has one end of the connection terminal upper surface electrode film 12 and the connection terminal upper surface electrode film 12 connected to the auxiliary electrode film 20.
Is formed so as to partially overlap the upper surface electrode film 13 for the other connection terminal, and a dielectric film 15 constituting a capacitor is formed on the upper surface of the lower layer electrode film 14. Further, the dielectric film 15 is formed. The upper electrode film 1 that constitutes the capacitor on the upper surface of the
6, one end of the upper layer electrode film 16 has both the auxiliary electrode films 2
It is formed so as to overlap zero.

【0011】なお、符号17,18は、前記チップ片1
1における左右両端面の各々に、前記両接続端子用上面
電極膜12,13に電気的に導通するように形成した接
続端子用側面電極膜を、符号19は、ガラス等のオーバ
ーコートを示し、前記両接続端子用上面電極膜12,1
3及び両接続端子用側面電極膜17,18の外表面に
は、半田ゆれ性を向上するための適宜の金属メッキ層が
形成されている。
Reference numerals 17 and 18 denote the chip pieces 1 described above.
Reference numeral 19 denotes a side electrode film for connection terminals formed so as to be electrically connected to the upper surface electrode films 12 and 13 for both connection terminals on each of the left and right end surfaces in 1, and reference numeral 19 denotes an overcoat such as glass, Upper surface electrode films 12, 1 for both connection terminals
On the outer surface of the side electrode films 17 for both 3 and both connection terminals, an appropriate metal plating layer for improving solderability is formed.

【0012】この構成のチップ型厚膜コンデンサを製造
するに際しては、先づ、図3に示すように、チップ片1
1の上面に、前記左右一対の接続端子用上面電極膜1
2,13を、第1スクリーン21を使用したスクリーン
印刷にて形成し、次いで、前記チップ片11の上面に、
図4に示すように、下層電極膜14と補助電極膜20と
を、第2スクリーン22を使用したスクリーン印刷にて
形成する。
In manufacturing the chip type thick film capacitor having this structure, first, as shown in FIG.
1 on the upper surface of the upper and lower electrode film 1 for connecting terminals
2, 13 are formed by screen printing using the first screen 21, and then, on the upper surface of the chip piece 11,
As shown in FIG. 4, the lower electrode film 14 and the auxiliary electrode film 20 are formed by screen printing using the second screen 22.

【0013】更に、前記下層電極膜14の上面に、図5
に示すように、誘電体膜15を、第3スクリーン23を
使用したスクリーン印刷にて形成する。次いで、前記誘
電体膜15の上面に、図6に示すように、上層電極膜1
6を、第4スクリーン24を使用したスクリーン印刷に
て形成する。そして、前記チップ片11の左右両端面に
接続端子用側面電極膜17,18を形成し、更に、オー
バーコート19を施したのち、前記両接続端子用上面電
極膜12,13及び両接続端子用側面電極膜17,18
の外表面に対して金属メッキを施すことによって完成品
にするのである。
Further, on the upper surface of the lower electrode film 14, as shown in FIG.
As shown in, the dielectric film 15 is formed by screen printing using the third screen 23. Then, on the upper surface of the dielectric film 15, as shown in FIG.
6 is formed by screen printing using the fourth screen 24. Then, side electrode films 17 and 18 for connecting terminals are formed on both left and right end surfaces of the chip piece 11, and an overcoat 19 is further applied. Then, the upper electrode films 12 and 13 for both connecting terminals and both connecting terminals are formed. Side electrode film 17, 18
The metal is plated on the outer surface of the to make a finished product.

【0014】このように、左右一対の両接続端子用上面
電極膜12,13のうち一方の接続端子用上面電極膜1
2に対して電気的に導通するコンデンサ用下層電極膜1
4と、他方の接続端子用上面電極膜13及びコンデンサ
用上層電極膜16に電気的に導通する補助電極膜20と
を、第2スクリーン22を使用したスクリーン印刷にて
同時に形成することにより、その間における相対的な位
置のずれをなくすることができ、換言すると、その間に
おける間隔寸法Tを常に一定に確保することができるか
ら、各種の電極膜を形成するに際して、その相互間に相
対的な位置のずれが存在しても、前記一方の接続端子用
上面電極膜12に電気的に導通するコンデンサ用下層電
極膜14が、他方の接続端子用上面電極膜13及びコン
デンサ用上層電極膜16に対して電気的にショートする
ことを、前記補助電極膜20をコンデンサ用下層電極膜
14と同時に形成することによって、確実に回避するこ
とができるのである。
As described above, one of the pair of left and right upper surface electrode films 12 for connecting terminals is the upper surface electrode film 1 for connecting terminal.
Capacitor lower electrode film 1 electrically conducting to 2
4 and the auxiliary electrode film 20 electrically connected to the other upper electrode film 13 for connection terminals and the upper electrode film 16 for capacitors are simultaneously formed by screen printing using the second screen 22, It is possible to eliminate the relative positional deviation in the above, in other words, since the interval dimension T between them can be always kept constant, when forming various electrode films, the relative positions between them are Even if there is a deviation, the capacitor lower electrode film 14 electrically connected to the one connection terminal upper electrode film 12 is different from the other connection terminal upper electrode film 13 and the capacitor upper electrode film 16. By forming the auxiliary electrode film 20 at the same time as the lower electrode film 14 for a capacitor, it is possible to surely avoid the electrical short circuit. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例によるチップ型厚膜コンデンサ
の縦断正面図である。
FIG. 1 is a vertical sectional front view of a chip type thick film capacitor according to an embodiment of the present invention.

【図2】図1の平面図である。FIG. 2 is a plan view of FIG.

【図3】チップ片の上面に接続端子用上面電極膜を形成
している状態を示す縦断正面図である。
FIG. 3 is a vertical cross-sectional front view showing a state in which an upper surface electrode film for a connection terminal is formed on the upper surface of a chip piece.

【図4】チップ片の上面にコンデンサ用下層電極膜と補
助電極膜とを形成している状態を示す縦断正面図であ
る。
FIG. 4 is a vertical cross-sectional front view showing a state in which a lower electrode film for a capacitor and an auxiliary electrode film are formed on the upper surface of a chip piece.

【図5】前記コンデンサ用下層電極膜の上面に誘電体膜
を形成している状態を示す縦断正面図である。
FIG. 5 is a vertical sectional front view showing a state in which a dielectric film is formed on the upper surface of the lower electrode film for a capacitor.

【図6】前記誘電体膜の上面にコンデンサ用上層電極膜
を形成している状態を示す縦断正面図である。
FIG. 6 is a vertical sectional front view showing a state in which a capacitor upper layer electrode film is formed on the upper surface of the dielectric film.

【図7】従来におけるチップ型厚膜コンデンサの縦断正
面図である。
FIG. 7 is a vertical sectional front view of a conventional chip type thick film capacitor.

【図8】図7の平面図である。FIG. 8 is a plan view of FIG.

【符号の説明】[Explanation of symbols]

11 チップ片 12,13 接続端子用上面電極膜 14 コンデンサ用下層電極膜 15 誘電体膜 16 コンデンサ用上層電極膜 17,18 接続端子用側面電極膜 19 オーバーコート 20 補助電極膜 11 Chip Pieces 12, 13 Upper Electrode Film for Connection Terminal 14 Lower Electrode Film for Capacitor 15 Dielectric Film 16 Upper Electrode Film for Capacitor 17, 18 Side Electrode Film for Connection Terminal 19 Overcoat 20 Auxiliary Electrode Film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁体製チップ片の上面に、左右一対の接
続端子用上面電極膜を形成し、次いで、コンデンサ用の
下層電極膜と、この下層電極膜と適宜間隔を隔てた補助
電極膜とを、下層電極膜が前記両接続端子用上面電極膜
のうち一方の接続端子用上面電極膜に、補助電極膜が他
方の接続端子用上面電極膜に各々電気的に導通するよう
に同時に形成し、前記下層電極膜の上面にコンデンサ用
の誘電体膜を形成したのち、この誘電体膜の上面にコン
デンサ用の上層電極膜を、当該上層電極膜が前記補助電
極膜に電気的に導通するように形成することを特徴とす
るチップ型厚膜コンデンサの製造方法。
1. A pair of left and right upper surface electrode films for connection terminals are formed on the upper surface of an insulating chip piece, and then a lower layer electrode film for a capacitor and an auxiliary electrode film which is appropriately spaced from the lower layer electrode film. And the lower electrode film are simultaneously formed so as to be electrically connected to the upper electrode film for one connecting terminal of the upper electrode films for both connecting terminals, and the auxiliary electrode film is electrically connected to the upper electrode film for the other connecting terminal, respectively. Then, after forming a dielectric film for a capacitor on the upper surface of the lower electrode film, an upper electrode film for a capacitor is formed on the upper surface of the dielectric film, and the upper electrode film electrically connects to the auxiliary electrode film. A method of manufacturing a chip-type thick film capacitor, which is characterized in that
JP6201669A 1994-08-26 1994-08-26 Manufacture of chip type thick capacitor Pending JPH0864472A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP6201669A JPH0864472A (en) 1994-08-26 1994-08-26 Manufacture of chip type thick capacitor
KR1019960702104A KR100206621B1 (en) 1994-08-26 1995-08-23 Chip type thick film capacitor and method of making the same
CN95190820A CN1046817C (en) 1994-08-26 1995-08-23 Chip type thick film capacitor and method of making the same
PCT/JP1995/001664 WO1996007188A1 (en) 1994-08-26 1995-08-23 Chip type thick film capacitor and method of making the same
US08/596,326 US5691877A (en) 1994-08-26 1996-02-16 Chip type thick film capacitor and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6201669A JPH0864472A (en) 1994-08-26 1994-08-26 Manufacture of chip type thick capacitor

Publications (1)

Publication Number Publication Date
JPH0864472A true JPH0864472A (en) 1996-03-08

Family

ID=16444940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6201669A Pending JPH0864472A (en) 1994-08-26 1994-08-26 Manufacture of chip type thick capacitor

Country Status (1)

Country Link
JP (1) JPH0864472A (en)

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