JPH0862304A - Pattern generator - Google Patents

Abstract

PURPOSE: To provide a pattern generator capable of testing a memory device having a latency action of an arbitrary cycle in the case of testing by using a plurality of pattern generators. CONSTITUTION: Pattern generating parts 22 each outputting a dry pattern and expected value signal are equipped in pattern generators 1, 2, N-1, N. A cycle shift circuit 124 of one cycle fixed for outputting the delay expected value signal obtained by shifting the expected value signal by one cycle based on action period of the pattern generator. A selector 128 of N:1 is equipped for selecting an arbitrary signal out of the expected value signals outputted from the pattern generators 1, 2, N-1, N and the delay expected value signals outputted from a plurality of pattern generators other than itself. A cycle shift part 21 is equipped for outputting the expected value pattern by delaying the output of a signal selected by the selector 128 by action period of the determined pattern generator. A plurality of those pattern generators are used to generate an arbitrary cycle shift from the expected value pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator capable of testing a memory device having a latency operation in data output.

[0002]

2. Description of the Related Art The basic structure of a conventional memory test apparatus is shown in FIG.
Shown in In the pattern generator 20, the pattern generating section 22 generates a driver pattern including an address signal, a test data signal, and a control signal and an expected value signal to be given to the memory under test 10 by a preset algorithm. The cycle shift unit 21 also delays the expected value signal by a preset number of cycles,
Output as expected value pattern. The waveform shaper 12 uses the pattern generator 2 according to a preset waveform mode.
A driver waveform is generated by the driver pattern from 0 and CLOCK from the timing generator 11, and is applied to the memory under test 10. The memory under test 10 outputs data according to the applied driver waveform. The output data is compared in the logical comparator 13 with the expected value pattern from the pattern generator 20 at the timing of the STRB from the timing generator 11, and the pass / fail of the memory under test 10 is judged by the coincidence or non-coincidence.

FIG. 5 is a timing chart of a test operation of a high speed memory device having a latency operation of 2 cycles for output data. Here, the latency operation is an operation in which read data is output at a fixed cycle delay from an address input cycle during a read operation in a semiconductor memory that performs a high-speed read / write operation in synchronization with an external clock. , Determined by the frequency of the target semiconductor memory and external clock. The driver pattern is waveform-shaped by CLOCK and drives the memory under test 10 with the driver waveform. The memory under test 10 having a 2-cycle latency operation outputs the output data with a delay of 2 cycles. On the other hand, the expected value signal is delayed by two cycles in the cycle shift unit 21 and output to the logical comparator 13 as an expected value pattern. The logical comparator 13 is S
At the timing of TRB, the output data and the expected value pattern are compared, and the quality is judged.

When the operating frequency of the pattern generator 20 is lower than the operating frequency of the memory under test 10, by having a plurality of pattern generators 20 as shown in FIG. 6, it corresponds to the operating frequency of the device. For example, when the memory under test 10 having the operating frequency M is tested using the pattern generator 20 having the operating frequency L, when M> L, N pattern generators 20 are set so that M ≦ N × L. To use. The N pattern generators 20 process the driver patterns and the expected value patterns of 1 to n steps in parallel, and give each driver pattern to the waveform shaper 112 and each expected value pattern to the logical comparator 113. The waveform shaper 112 uses each driver pattern and step C corresponding to each driver pattern.
A driver waveform of frequency M is synthesized by LOCK and applied to the memory under test 10. The logical comparator 113 judges pass / fail of each expected value pattern and output data corresponding to each expected value pattern at the frequency M by STRB.

FIG. 7 is an operation timing chart when N pattern generators 20 are used in a general case where there is no latency operation. In this case, the memory under test 10 operates n cycles for one cycle of the pattern generator 20. The driver patterns are the pattern generators 20 from the pattern generator 1 to the pattern generator n.
From the waveform generator 11 in the cycle of the pattern generator 20.
2 is output. C output from the timing generator 11
LOCK selects the driver pattern input to the waveform shaper 112 in the operation cycle of the memory under test 10,
The driver waveform is supplied to the memory under test 10. On the other hand, the expected value pattern is output from each pattern generator 20 from the pattern generator 1 to the pattern generator N to the logical comparator 113 in the cycle of the pattern generator 20. The STRB output from the timing generator 11 compares the output data output from the memory under test 10 with the expected value pattern in the operation cycle of the memory under test 10 to make a pass / fail judgment.

[0006]

FIG. 8 shows a case in which N pattern generators 20 are used for testing and each pattern generator 2 is used.
The timing chart at the time of carrying out 1 cycle shift by the cycle shift part 21 of 0 is shown. In this case, the pattern generator 2
For one cycle of 0, the memory under test 10 operates for n cycles. The driver pattern is output from each pattern generator 20 from the pattern generator 1 to the pattern generator N to the waveform shaper 112 in the cycle of the pattern generator 20. The CLOCK output from the timing generator 11 selects the driver pattern input to the waveform shaper 112 in the operation cycle of the memory under test 10 and supplies the driver waveform to the memory under test 10. On the other hand, the expected value signal output from the pattern generator 22 is output from the respective pattern generators 22 from the pattern generator 1 to the pattern generator N to the cycle shift unit 21 in the cycle of the pattern generator 20. When 1 is set in the cycle shift section 21, the expected value pattern generated from the pattern generator 20 is shifted by n cycles in the cycle of the memory under test 10. Therefore, when N pattern generators 20 are used, the cycle shift unit 21
In the cycle of the memory under test 10, the value set to is set to N times the set value, and the cycle delay value can be set to only a multiple of N. This is because the relationship between the operating frequencies of the memory under test 10 having the operating frequency M and the pattern generator 20 having the operating frequency L is M> L, and it is necessary to use N pattern generators in which M ≦ N × L. At times, the cycle delay of the output data cannot generate an expected value pattern of the memory under test 10 having a value other than a multiple of N. In FIG. 8, the expected value pattern is uncertain between D1 and Dn−1, and the expected value pattern E1 of D1 is compared in Dn, and the cycle of the expected value pattern and the timing of the output data are Do not fit. It is an object of the present invention to realize a pattern generator capable of testing a memory device having a latency operation of an arbitrary cycle when using a plurality of pattern generators for testing.

[0007]

To achieve the above object, the pattern generator of the present invention is provided with a pattern generator for outputting a driver pattern and an expected value signal. Then, the expected value signal is shifted by one cycle in the operation cycle of the pattern generator to output a delayed expected value signal 1
A cycle shift circuit with a fixed cycle is provided. Further, there is provided an N-to-1 selector for selecting an arbitrary signal from the expected value signals output from the plurality of pattern generators including itself and the delay expected value signals output from the plurality of pattern generators excluding itself. The output of the signal selected by the N-to-1 selector is provided with a cycle shift unit that delays the set value by the operation cycle of the pattern generator and outputs the expected value pattern. In order to generate an arbitrary cycle shift from the expected value pattern, a plurality of pattern generators having the above configuration are used. By inputting multiple driver patterns output from the pattern generator, the CLO of the operating cycle of the memory under test is input.
A waveform shaper that outputs a driver waveform with a CK signal is provided. Further, a logical comparator is provided which inputs a plurality of expected value patterns output from the pattern generator and compares the output data output from the memory under test with the STRB signal of the operation cycle of the memory under test.

[0008]

In the pattern generator configured as described above,
When testing with multiple pattern generators, memory devices with arbitrary cycle latency behavior can be tested.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows an A-th pattern generator 12 of the present invention.
0 shows a block diagram of 0. In this block, an N: 1 selector 123 and a 1-cycle fixed cycle shift circuit 124 are inserted between the pattern generation unit 22 and the cycle shift unit 21 in the conventional pattern generator 20. As a result, all the pattern generators 120 output the expected value signals output from the pattern generator 22 of the pattern generator 120 or the cycle shift circuit 124 fixed for one cycle.
The delay expected value signal output from the pattern generator 120 can be output as an expected value pattern through the N: 1 selector 123. At this time, the cycle shift circuit 124, which is fixed for one cycle, is
Delay the expected value signal output from 2 by one cycle,
Output as a delay expected value signal.

FIG. 1 shows a connection block diagram when N pattern generators 120 are connected. At this time, the N-to-1 selector 123, in the case of the memory under test that performs the latency operation of R cycles, when R is smaller than N, in the case of the A-th pattern generator 120, the AR-th pattern generator 120. The expected value signal output from the pattern generation unit 22 is selected. However, when (A−R) ≦ 0, A−R +
The delay expected value signal output from the N-th cycle fixed cycle shift circuit 124 is selected. For example, in FIG. 1, when A = 2 and R = 1, that is, the N-to-1 selector 123 of the pattern generator 2 has the pattern generator 2 of the first pattern generator 120 from AR = 1.
The expected value signal output from 2 is selected. Further, in FIG. 1, in the case of A = 1 and R = 1, that is, the N-to-1 selector 123 of the pattern generator 1 has A-R = 0 ≦ 0,
A−R + N = N, the delay expected value signal output from the Nth cycle fixed cycle shift circuit 124 is selected.

The relationship between the operating frequency of the memory under test 10 having the operating frequency M and the operating frequency of the pattern generator 120 having the operating frequency L is M.
> L and M ≦ N × L, N pattern generators 120 are used, and when the memory under test 10 having a cycle delay of output data of R is tested, each pattern generator 1
The value S of the integer part of R / N is set in the cycle shift unit 21 of 20. Next, the remainder value T of R ÷ N is set in the N: 1 selector 123. As a result, the N-to-1 selector 123 of the A-th pattern generator 120 selects the AT-th expected value signal. However, if (A−T) ≦ 0, the A−T + Nth delay expected value signal is selected.
In the cycle shift unit 21, the expected value pattern is generated in synchronization with the cycle delay R of the output data of the memory under test 10 by performing the cycle shift by the set value S. For example, in FIG. 1, when N = 4 and R = 5, S
= 1 and T = 1. A = 2, that is, the N-to-1 selector 123 of the second pattern generator 120 has A-T =
Select the first expected value signal. Further, A = 1, that is, the N-to-1 selector 123 of the first pattern generator 120 has A-T = 0≤0, and therefore A-T + N = N = 4.
Select the th delay expected value signal. Further, since S = 1, the cycle is unconditionally delayed by one cycle of the pattern generator 120 and N = 4.

FIG. 3 shows a timing chart when N pattern generators 120 are used for testing and the cycle delay is 1. In this case, the memory under test 10 operates n cycles for one cycle of the pattern generator 120. The driver pattern is generated by the waveform shaper 11 from each pattern generator 120 from the pattern generator 1 to the pattern generator N in the cycle of the pattern generator 120.
2 is output. C output from the timing generator 11
LOCK selects the driver pattern input to the waveform shaper 112 in the operation cycle of the memory under test 10,
The driver waveform is supplied to the memory under test 10. On the other hand, the expected value signal output from the pattern generator 22 is the N-to-1 selector 123 and one cycle in the cycle of the pattern generator 120 from each pattern generator 22 from the pattern generator 1 to the pattern generator N. It is output to the fixed cycle shift circuit 124. The delay expected value signal generated from the cycle shift circuit 124 fixed for one cycle is shifted by n cycles in the cycle of the memory under test 10 and output. The N: 1 selector 123 outputs 1 from the expected value signal from the pattern generator 22 and the expected delay signal from the cycle shift circuit 124 fixed for one cycle.
One of the signals is selected and output as an expected value pattern to the logical comparator 113 in the cycle of the pattern generator 120 through the cycle shift unit 21. Timing generator 1
The STRB output from 1 compares the output data output from the memory under test 10 with the expected value pattern in the operation cycle of the memory under test 10 to determine pass / fail.

[0013]

Since the present invention is configured as described above, it is possible to test a memory device having a latency operation of an arbitrary cycle even when using a plurality of pattern generators for testing. It will be possible.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a memory test using a plurality of pattern generators of the present invention.

FIG. 2 is a circuit block diagram of an A-th pattern generator of the present invention.

FIG. 3 is a timing diagram of a memory test using a plurality of pattern generators of the present invention.

FIG. 4 is a basic configuration diagram of a conventional memory test device.

FIG. 5 is a test operation timing diagram of a memory device having a latency operation when there is one pattern generator.

FIG. 6 is a circuit block diagram of a memory test using a plurality of conventional pattern generators.

FIG. 7 is an operation timing diagram when there is no latency operation using a plurality of conventional pattern generators.

FIG. 8 is a timing diagram in the case of cycle shifting using a plurality of conventional pattern generators.

[Explanation of symbols]

 10 Memory under Test 11 Timing Generator 12, 112 Waveform Shaper 13, 113 Logical Comparator 20, 120 Pattern Generator 21 Cycle Shift Unit 22 Pattern Generator 123 N-to-1 Selector 124 1 Cycle Fixed Cycle Shift Circuit

Claims (2)

[Claims] 1. A pattern generator (22) for outputting a driver pattern and an expected value signal, and an expected value signal for one operation cycle of the pattern generator (120).
Cycle-shifted, delay expected signal output 1
From a cycle shift circuit (124) with a fixed cycle and an expected value signal output from a plurality of pattern generators (120) including itself and a delay expected value signal output from a plurality of pattern generators (120) excluding itself The N-to-1 selector (123) that selects an arbitrary signal and the signal selected by the N-to-1 selector (123) are expected to be delayed by the set value in the operation cycle of the pattern generator (120). A pattern generator comprising: a cycle shift unit (21) for outputting a value pattern. 2. A pattern generator comprising a plurality of connected pattern generators (12
0) and at least one driver pattern output from the pattern generator (120) are input, and the memory under test (1
0) The waveform shaper (112) that outputs the driver waveform with the CLOCK signal of the operation cycle, and at least one expected value pattern that is output from the pattern generator (120) are input to the memory under test (10).
A logical comparator (113) for comparing the output data output from the memory with the STRB signal of the operation cycle of the memory under test (10).
And a pattern generator comprising: